InstrEmitter.cpp revision 33a537a5c41e60507ac9a4ea987c1a395cbb74fe
19c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 29c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// 39c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// The LLVM Compiler Infrastructure 49c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// 59c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// This file is distributed under the University of Illinois Open Source 69c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// License. See LICENSE.TXT for details. 79c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// 89c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek//===----------------------------------------------------------------------===// 99c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// 109c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// This implements the Emit routines for the SelectionDAG class, which creates 119c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// MachineInstrs based on the decisions of the SelectionDAG instruction 129c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// selection. 139c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek// 149c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek//===----------------------------------------------------------------------===// 159c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 169c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#define DEBUG_TYPE "instr-emitter" 179c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "InstrEmitter.h" 189c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "SDNodeDbgValue.h" 199c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/CodeGen/MachineConstantPool.h" 209c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/CodeGen/MachineFunction.h" 219c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/CodeGen/MachineInstrBuilder.h" 229c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/CodeGen/MachineRegisterInfo.h" 239c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Target/TargetData.h" 249c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Target/TargetMachine.h" 259c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Target/TargetInstrInfo.h" 269c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Target/TargetLowering.h" 279c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/ADT/Statistic.h" 289c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Support/Debug.h" 299c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Support/ErrorHandling.h" 309c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek#include "llvm/Support/MathExtras.h" 319c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekusing namespace llvm; 329c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 339c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// MinRCSize - Smallest register class we allow when constraining virtual 349c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// registers. If satisfying all register class constraints would require 359c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// using a smaller register class, emit a COPY to a new virtual register 369c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// instead. 379c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekconst unsigned MinRCSize = 4; 389c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 399c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// CountResults - The results of target nodes have register or immediate 409c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// operands first, then an optional chain, and optional glue operands (which do 419c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// not go into the resulting MachineInstr). 429c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekunsigned InstrEmitter::CountResults(SDNode *Node) { 439c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned N = Node->getNumValues(); 449c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek while (N && Node->getValueType(N - 1) == MVT::Glue) 459c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek --N; 469c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (N && Node->getValueType(N - 1) == MVT::Other) 479c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek --N; // Skip over chain result. 489c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return N; 499c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 509c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 519c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// countOperands - The inputs to target nodes have any actual inputs first, 529c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// followed by an optional chain operand, then an optional glue operand. 539c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// Compute the number of actual operands that will go into the resulting 549c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// MachineInstr. 559c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// 569c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 579c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// the chain and glue. These operands may be implicit on the machine instr. 589c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekstatic unsigned countOperands(SDNode *Node, unsigned &NumImpUses) { 599c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned N = Node->getNumOperands(); 609c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 619c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek --N; 629c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 639c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek --N; // Ignore chain if it exists. 649c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 659c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 669c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek for (unsigned I = N; I; --I) { 679c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 689c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek continue; 699c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 709c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 719c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek continue; 729c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek NumImpUses = N - I; 739c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek break; 749c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 759c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 769c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return N; 779c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 789c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 799c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 809c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// implicit physical register output. 819c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekvoid InstrEmitter:: 829c9bd84383f742513b3cfd656948bab16d752937Ted KremenekEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 839c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 849c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned VRBase = 0; 859c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 869c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Just use the input register directly! 879c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDValue Op(Node, ResNo); 889c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (IsClone) 899c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBaseMap.erase(Op); 909c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 919c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek (void)isNew; // Silence compiler warning. 929c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(isNew && "Node emitted out of order - early"); 939c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return; 949c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 959c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 969c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If the node is only used by a CopyToReg and the dest reg is a vreg, use 979c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // the CopyToReg'd destination register instead of creating a new vreg. 989c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool MatchReg = true; 999c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *UseRC = NULL; 1009c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek EVT VT = Node->getValueType(ResNo); 1019c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1029c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Stick to the preferred register classes for legal types. 1039c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TLI->isTypeLegal(VT)) 1049c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek UseRC = TLI->getRegClassFor(VT); 1059c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1069c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (!IsClone && !IsCloned) 1079c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 1089c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek UI != E; ++UI) { 1099c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDNode *User = *UI; 1109c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool Match = true; 1119c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (User->getOpcode() == ISD::CopyToReg && 1129c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getNode() == Node && 1139c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getResNo() == ResNo) { 1149c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 1159c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 1169c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = DestReg; 1179c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Match = false; 1189c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (DestReg != SrcReg) 1199c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Match = false; 1209c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else { 1219c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 1229c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDValue Op = User->getOperand(i); 1239c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (Op.getNode() != Node || Op.getResNo() != ResNo) 1249c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek continue; 1259c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek EVT VT = Node->getValueType(Op.getResNo()); 1269c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (VT == MVT::Other || VT == MVT::Glue) 1279c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek continue; 1289c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Match = false; 1299c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (User->isMachineOpcode()) { 1309c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 1319c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *RC = 0; 1329c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (i+II.getNumDefs() < II.getNumOperands()) { 1339c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek RC = TRI->getAllocatableClass( 1349c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 1359c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1369c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (!UseRC) 1379c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek UseRC = RC; 1389c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek else if (RC) { 1399c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *ComRC = 1409c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TRI->getCommonSubClass(UseRC, RC); 1419c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If multiple uses expect disjoint register classes, we emit 1429c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // copies in AddRegisterOperand. 1439c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (ComRC) 1449c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek UseRC = ComRC; 1459c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1469c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1479c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1489c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1499c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MatchReg &= Match; 1509c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (VRBase) 1519c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek break; 1529c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1539c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1549c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 1559c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 1569c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1579c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Figure out the register class to create for the destreg. 1589c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (VRBase) { 1599c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DstRC = MRI->getRegClass(VRBase); 1609c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (UseRC) { 1619c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1629c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DstRC = UseRC; 1639c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else { 1649c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DstRC = TLI->getRegClassFor(VT); 1659c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1669c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1679c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If all uses are reading from the src physical register and copying the 1689c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // register is either impossible or very expensive, then don't create a copy. 1699c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (MatchReg && SrcRC->getCopyCost() < 0) { 1709c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = SrcReg; 1719c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else { 1729c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Create the reg, emit the copy. 1739c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = MRI->createVirtualRegister(DstRC); 1749c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 1759c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase).addReg(SrcReg); 1769c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 1779c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1789c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDValue Op(Node, ResNo); 1799c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (IsClone) 1809c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBaseMap.erase(Op); 1819c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 1829c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek (void)isNew; // Silence compiler warning. 1839c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(isNew && "Node emitted out of order - early"); 1849c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 1859c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1869c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// getDstOfCopyToRegUse - If the only use of the specified result number of 1879c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// node is a CopyToReg, return its destination register. Return 0 otherwise. 1889c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 1899c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned ResNo) const { 1909c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (!Node->hasOneUse()) 1919c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return 0; 1929c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 1939c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDNode *User = *Node->use_begin(); 1949c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (User->getOpcode() == ISD::CopyToReg && 1959c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getNode() == Node && 1969c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getResNo() == ResNo) { 1979c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 1989c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TargetRegisterInfo::isVirtualRegister(Reg)) 1999c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return Reg; 2009c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2019c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return 0; 2029c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 2039c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2049c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 2059c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const MCInstrDesc &II, 2069c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool IsClone, bool IsCloned, 2079c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DenseMap<SDValue, unsigned> &VRBaseMap) { 2089c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 2099c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 2109c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2119c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek for (unsigned i = 0; i < II.getNumDefs(); ++i) { 2129c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If the specific node value is only used by a CopyToReg and the dest reg 2139c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // is a vreg in the same register class, use the CopyToReg'd destination 2149c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // register instead of creating a new vreg. 2159c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned VRBase = 0; 2169c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *RC = 2179c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 2189c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (II.OpInfo[i].isOptionalDef()) { 2199c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Optional def must be a physical register. 2209c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned NumResults = CountResults(Node); 2219c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 2229c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 2239c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 2249c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2259c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2269c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (!VRBase && !IsClone && !IsCloned) 2279c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2289c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek UI != E; ++UI) { 2299c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDNode *User = *UI; 2309c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (User->getOpcode() == ISD::CopyToReg && 2319c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getNode() == Node && 2329c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek User->getOperand(2).getResNo() == i) { 2339c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 2349c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (TargetRegisterInfo::isVirtualRegister(Reg)) { 2359c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 2369c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (RegRC == RC) { 2379c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = Reg; 2389c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateReg(Reg, true)); 2399c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek break; 2409c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2419c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2429c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2439c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2449c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2459c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Create the result registers for this node and add the result regs to 2469c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // the machine instruction. 2479c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (VRBase == 0) { 2489c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(RC && "Isn't a register operand!"); 2499c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBase = MRI->createVirtualRegister(RC); 2509c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 2519c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2529c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2539c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek SDValue Op(Node, i); 2549c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (IsClone) 2559c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VRBaseMap.erase(Op); 2569c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 2579c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek (void)isNew; // Silence compiler warning. 2589c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(isNew && "Node emitted out of order - early"); 2599c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2609c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 2619c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2629c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// getVR - Return the virtual register corresponding to the specified result 2639c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// of the specified node. 2649c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekunsigned InstrEmitter::getVR(SDValue Op, 2659c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DenseMap<SDValue, unsigned> &VRBaseMap) { 2669c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (Op.isMachineOpcode() && 2679c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 2689c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Add an IMPLICIT_DEF instruction before every use. 2699c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 2709c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 2719c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // does not include operand register class info. 2729c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (!VReg) { 2739c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 2749c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VReg = MRI->createVirtualRegister(RC); 2759c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2769c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 2779c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 2789c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return VReg; 2799c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 2809c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2819c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 2829c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 2839c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek return I->second; 2849c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 2859c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2869c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 2879c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// AddRegisterOperand - Add the specified register as an operand to the 2889c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// specified machine instr. Insert register copies if the register is 2899c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// not in the required register class. 2909c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekvoid 2919c9bd84383f742513b3cfd656948bab16d752937Ted KremenekInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 2929c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned IIOpNum, 2939c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const MCInstrDesc *II, 2949c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DenseMap<SDValue, unsigned> &VRBaseMap, 2959c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool IsDebug, bool IsClone, bool IsCloned) { 2969c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(Op.getValueType() != MVT::Other && 2979c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Op.getValueType() != MVT::Glue && 2989c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek "Chain and glue operands should occur at end of operand list!"); 2999c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Get/emit the operand. 3009c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned VReg = getVR(Op, VRBaseMap); 3019c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 3029c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 3039c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const MCInstrDesc &MCID = MI->getDesc(); 3049c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isOptDef = IIOpNum < MCID.getNumOperands() && 3059c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MCID.OpInfo[IIOpNum].isOptionalDef(); 3069c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 3079c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If the instruction requires a register in a different class, create 3089c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // a new virtual register and copy the value into it, but first attempt to 3099c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // shrink VReg's register class within reason. For example, if VReg == GR32 3109c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 3119c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (II) { 3129c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const TargetRegisterClass *DstRC = 0; 3139c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (IIOpNum < II->getNumOperands()) 3149c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 3159c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) && 3169c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek "Don't have operand info for this instruction!"); 3179c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 3189c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned NewVReg = MRI->createVirtualRegister(DstRC); 3199c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 3209c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 3219c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek VReg = NewVReg; 3229c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 3239c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 3249c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 3259c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // If this value has only one use, that use is a kill. This is a 3269c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // conservative approximation. InstrEmitter does trivial coalescing 3279c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // with CopyFromReg nodes, so don't emit kill flags for them. 3289c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Avoid kill flags on Schedule cloned nodes, since there will be 3299c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // multiple uses. 3309c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Tied operands are never killed, so we need to check that. And that 3319c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // means we need to determine the index of the operand. 3329c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isKill = Op.hasOneUse() && 3339c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Op.getNode()->getOpcode() != ISD::CopyFromReg && 3349c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek !IsDebug && 3359c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek !(IsClone || IsCloned); 3369c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (isKill) { 3379c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned Idx = MI->getNumOperands(); 3389c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek while (Idx > 0 && 3399c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3409c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek --Idx; 3419c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 3429c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (isTied) 3439c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek isKill = false; 3449c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } 3459c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 3469c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 3479c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek false/*isImp*/, isKill, 3489c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek false/*isDead*/, false/*isUndef*/, 3499c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek false/*isEarlyClobber*/, 3509c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 0/*SubReg*/, IsDebug)); 3519c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek} 3529c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek 3539c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// AddOperand - Add the specified operand to the specified machine instr. II 3549c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// specifies the instruction information for the node, and IIOpNum is the 3559c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek/// operand number (in the II) that we are adding. 3569c9bd84383f742513b3cfd656948bab16d752937Ted Kremenekvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 3579c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned IIOpNum, 3589c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const MCInstrDesc *II, 3599c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek DenseMap<SDValue, unsigned> &VRBaseMap, 3609c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool IsDebug, bool IsClone, bool IsCloned) { 3619c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (Op.isMachineOpcode()) { 3629c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3639c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek IsDebug, IsClone, IsCloned); 3649c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3659c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 3669c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3679c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek const ConstantFP *CFP = F->getConstantFPValue(); 3689c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateFPImm(CFP)); 3699c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 3709c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // Turn additional physreg operands into implicit uses on non-variadic 3719c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // instructions. This is used by call and return instructions passing 3729c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // arguments in registers. 3739c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 3749c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp)); 3759c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 3769c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask())); 3779c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3789c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3799c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek TGA->getTargetFlags())); 3809c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 3819c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 3829c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 3839c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 3849c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3859c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3869c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek JT->getTargetFlags())); 3879c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 3889c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek int Offset = CP->getOffset(); 3899c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek unsigned Align = CP->getAlignment(); 3909c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Type *Type = CP->getType(); 3919c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek // MachineConstantPool wants an explicit alignment. 3929c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek if (Align == 0) { 3939c9bd84383f742513b3cfd656948bab16d752937Ted Kremenek Align = TM->getTargetData()->getPrefTypeAlignment(Type); 394 if (Align == 0) { 395 // Alignment of vector types. FIXME! 396 Align = TM->getTargetData()->getTypeAllocSize(Type); 397 } 398 } 399 400 unsigned Idx; 401 MachineConstantPool *MCP = MF->getConstantPool(); 402 if (CP->isMachineConstantPoolEntry()) 403 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 404 else 405 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 406 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 407 CP->getTargetFlags())); 408 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 409 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 410 ES->getTargetFlags())); 411 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 412 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 413 BA->getTargetFlags())); 414 } else { 415 assert(Op.getValueType() != MVT::Other && 416 Op.getValueType() != MVT::Glue && 417 "Chain and glue operands should occur at end of operand list!"); 418 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 419 IsDebug, IsClone, IsCloned); 420 } 421} 422 423unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 424 EVT VT, DebugLoc DL) { 425 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 426 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 427 428 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 429 // within reason. 430 if (RC && RC != VRC) 431 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 432 433 // VReg has been adjusted. It can be used with SubIdx operands now. 434 if (RC) 435 return VReg; 436 437 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 438 // register instead. 439 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 440 assert(RC && "No legal register class for VT supports that SubIdx"); 441 unsigned NewReg = MRI->createVirtualRegister(RC); 442 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 443 .addReg(VReg); 444 return NewReg; 445} 446 447/// EmitSubregNode - Generate machine code for subreg nodes. 448/// 449void InstrEmitter::EmitSubregNode(SDNode *Node, 450 DenseMap<SDValue, unsigned> &VRBaseMap, 451 bool IsClone, bool IsCloned) { 452 unsigned VRBase = 0; 453 unsigned Opc = Node->getMachineOpcode(); 454 455 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 456 // the CopyToReg'd destination register instead of creating a new vreg. 457 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 458 UI != E; ++UI) { 459 SDNode *User = *UI; 460 if (User->getOpcode() == ISD::CopyToReg && 461 User->getOperand(2).getNode() == Node) { 462 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 463 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 464 VRBase = DestReg; 465 break; 466 } 467 } 468 } 469 470 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 471 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 472 // constraints on the %dst register, COPY can target all legal register 473 // classes. 474 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 475 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); 476 477 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 478 MachineInstr *DefMI = MRI->getVRegDef(VReg); 479 unsigned SrcReg, DstReg, DefSubIdx; 480 if (DefMI && 481 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 482 SubIdx == DefSubIdx) { 483 // Optimize these: 484 // r1025 = s/zext r1024, 4 485 // r1026 = extract_subreg r1025, 4 486 // to a copy 487 // r1026 = copy r1024 488 VRBase = MRI->createVirtualRegister(TRC); 489 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 490 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 491 MRI->clearKillFlags(SrcReg); 492 } else { 493 // VReg may not support a SubIdx sub-register, and we may need to 494 // constrain its register class or issue a COPY to a compatible register 495 // class. 496 VReg = ConstrainForSubReg(VReg, SubIdx, 497 Node->getOperand(0).getValueType(), 498 Node->getDebugLoc()); 499 500 // Create the destreg if it is missing. 501 if (VRBase == 0) 502 VRBase = MRI->createVirtualRegister(TRC); 503 504 // Create the extract_subreg machine instruction. 505 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 506 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 507 } 508 } else if (Opc == TargetOpcode::INSERT_SUBREG || 509 Opc == TargetOpcode::SUBREG_TO_REG) { 510 SDValue N0 = Node->getOperand(0); 511 SDValue N1 = Node->getOperand(1); 512 SDValue N2 = Node->getOperand(2); 513 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 514 515 // Figure out the register class to create for the destreg. It should be 516 // the largest legal register class supporting SubIdx sub-registers. 517 // RegisterCoalescer will constrain it further if it decides to eliminate 518 // the INSERT_SUBREG instruction. 519 // 520 // %dst = INSERT_SUBREG %src, %sub, SubIdx 521 // 522 // is lowered by TwoAddressInstructionPass to: 523 // 524 // %dst = COPY %src 525 // %dst:SubIdx = COPY %sub 526 // 527 // There is no constraint on the %src register class. 528 // 529 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); 530 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 531 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 532 533 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 534 VRBase = MRI->createVirtualRegister(SRC); 535 536 // Create the insert_subreg or subreg_to_reg machine instruction. 537 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 538 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 539 540 // If creating a subreg_to_reg, then the first input operand 541 // is an implicit value immediate, otherwise it's a register 542 if (Opc == TargetOpcode::SUBREG_TO_REG) { 543 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 544 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 545 } else 546 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 547 IsClone, IsCloned); 548 // Add the subregster being inserted 549 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 550 IsClone, IsCloned); 551 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 552 MBB->insert(InsertPos, MI); 553 } else 554 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 555 556 SDValue Op(Node, 0); 557 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 558 (void)isNew; // Silence compiler warning. 559 assert(isNew && "Node emitted out of order - early"); 560} 561 562/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 563/// COPY_TO_REGCLASS is just a normal copy, except that the destination 564/// register is constrained to be in a particular register class. 565/// 566void 567InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 568 DenseMap<SDValue, unsigned> &VRBaseMap) { 569 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 570 571 // Create the new VReg in the destination class and emit a copy. 572 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 573 const TargetRegisterClass *DstRC = 574 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 575 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 576 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 577 NewVReg).addReg(VReg); 578 579 SDValue Op(Node, 0); 580 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 581 (void)isNew; // Silence compiler warning. 582 assert(isNew && "Node emitted out of order - early"); 583} 584 585/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 586/// 587void InstrEmitter::EmitRegSequence(SDNode *Node, 588 DenseMap<SDValue, unsigned> &VRBaseMap, 589 bool IsClone, bool IsCloned) { 590 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 591 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 592 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 593 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 594 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 595 unsigned NumOps = Node->getNumOperands(); 596 assert((NumOps & 1) == 1 && 597 "REG_SEQUENCE must have an odd number of operands!"); 598 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 599 for (unsigned i = 1; i != NumOps; ++i) { 600 SDValue Op = Node->getOperand(i); 601 if ((i & 1) == 0) { 602 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 603 // Skip physical registers as they don't have a vreg to get and we'll 604 // insert copies for them in TwoAddressInstructionPass anyway. 605 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 606 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 607 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 608 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 609 const TargetRegisterClass *SRC = 610 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 611 if (SRC && SRC != RC) { 612 MRI->setRegClass(NewVReg, SRC); 613 RC = SRC; 614 } 615 } 616 } 617 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 618 IsClone, IsCloned); 619 } 620 621 MBB->insert(InsertPos, MI); 622 SDValue Op(Node, 0); 623 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 624 (void)isNew; // Silence compiler warning. 625 assert(isNew && "Node emitted out of order - early"); 626} 627 628/// EmitDbgValue - Generate machine instruction for a dbg_value node. 629/// 630MachineInstr * 631InstrEmitter::EmitDbgValue(SDDbgValue *SD, 632 DenseMap<SDValue, unsigned> &VRBaseMap) { 633 uint64_t Offset = SD->getOffset(); 634 MDNode* MDPtr = SD->getMDPtr(); 635 DebugLoc DL = SD->getDebugLoc(); 636 637 if (SD->getKind() == SDDbgValue::FRAMEIX) { 638 // Stack address; this needs to be lowered in target-dependent fashion. 639 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 640 unsigned FrameIx = SD->getFrameIx(); 641 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 642 } 643 // Otherwise, we're going to create an instruction here. 644 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 645 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 646 if (SD->getKind() == SDDbgValue::SDNODE) { 647 SDNode *Node = SD->getSDNode(); 648 SDValue Op = SDValue(Node, SD->getResNo()); 649 // It's possible we replaced this SDNode with other(s) and therefore 650 // didn't generate code for it. It's better to catch these cases where 651 // they happen and transfer the debug info, but trying to guarantee that 652 // in all cases would be very fragile; this is a safeguard for any 653 // that were missed. 654 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 655 if (I==VRBaseMap.end()) 656 MIB.addReg(0U); // undef 657 else 658 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 659 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 660 } else if (SD->getKind() == SDDbgValue::CONST) { 661 const Value *V = SD->getConst(); 662 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 663 if (CI->getBitWidth() > 64) 664 MIB.addCImm(CI); 665 else 666 MIB.addImm(CI->getSExtValue()); 667 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 668 MIB.addFPImm(CF); 669 } else { 670 // Could be an Undef. In any case insert an Undef so we can see what we 671 // dropped. 672 MIB.addReg(0U); 673 } 674 } else { 675 // Insert an Undef so we can see what we dropped. 676 MIB.addReg(0U); 677 } 678 679 MIB.addImm(Offset).addMetadata(MDPtr); 680 return &*MIB; 681} 682 683/// EmitMachineNode - Generate machine code for a target-specific node and 684/// needed dependencies. 685/// 686void InstrEmitter:: 687EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 688 DenseMap<SDValue, unsigned> &VRBaseMap) { 689 unsigned Opc = Node->getMachineOpcode(); 690 691 // Handle subreg insert/extract specially 692 if (Opc == TargetOpcode::EXTRACT_SUBREG || 693 Opc == TargetOpcode::INSERT_SUBREG || 694 Opc == TargetOpcode::SUBREG_TO_REG) { 695 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 696 return; 697 } 698 699 // Handle COPY_TO_REGCLASS specially. 700 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 701 EmitCopyToRegClassNode(Node, VRBaseMap); 702 return; 703 } 704 705 // Handle REG_SEQUENCE specially. 706 if (Opc == TargetOpcode::REG_SEQUENCE) { 707 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 708 return; 709 } 710 711 if (Opc == TargetOpcode::IMPLICIT_DEF) 712 // We want a unique VR for each IMPLICIT_DEF use. 713 return; 714 715 const MCInstrDesc &II = TII->get(Opc); 716 unsigned NumResults = CountResults(Node); 717 unsigned NumImpUses = 0; 718 unsigned NodeOperands = countOperands(Node, NumImpUses); 719 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 720#ifndef NDEBUG 721 unsigned NumMIOperands = NodeOperands + NumResults; 722 if (II.isVariadic()) 723 assert(NumMIOperands >= II.getNumOperands() && 724 "Too few operands for a variadic node!"); 725 else 726 assert(NumMIOperands >= II.getNumOperands() && 727 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 728 NumImpUses && 729 "#operands for dag node doesn't match .td file!"); 730#endif 731 732 // Create the new machine instruction. 733 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 734 735 // Add result register values for things that are defined by this 736 // instruction. 737 if (NumResults) 738 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 739 740 // Emit all of the actual operands of this instruction, adding them to the 741 // instruction as appropriate. 742 bool HasOptPRefs = II.getNumDefs() > NumResults; 743 assert((!HasOptPRefs || !HasPhysRegOuts) && 744 "Unable to cope with optional defs and phys regs defs!"); 745 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 746 for (unsigned i = NumSkip; i != NodeOperands; ++i) 747 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 748 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 749 750 // Transfer all of the memory reference descriptions of this instruction. 751 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 752 cast<MachineSDNode>(Node)->memoperands_end()); 753 754 // Insert the instruction into position in the block. This needs to 755 // happen before any custom inserter hook is called so that the 756 // hook knows where in the block to insert the replacement code. 757 MBB->insert(InsertPos, MI); 758 759 // The MachineInstr may also define physregs instead of virtregs. These 760 // physreg values can reach other instructions in different ways: 761 // 762 // 1. When there is a use of a Node value beyond the explicitly defined 763 // virtual registers, we emit a CopyFromReg for one of the implicitly 764 // defined physregs. This only happens when HasPhysRegOuts is true. 765 // 766 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 767 // 768 // 3. A glued instruction may implicitly use a physreg. 769 // 770 // 4. A glued instruction may use a RegisterSDNode operand. 771 // 772 // Collect all the used physreg defs, and make sure that any unused physreg 773 // defs are marked as dead. 774 SmallVector<unsigned, 8> UsedRegs; 775 776 // Additional results must be physical register defs. 777 if (HasPhysRegOuts) { 778 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 779 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 780 if (!Node->hasAnyUseOfValue(i)) 781 continue; 782 // This implicitly defined physreg has a use. 783 UsedRegs.push_back(Reg); 784 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 785 } 786 } 787 788 // Scan the glue chain for any used physregs. 789 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 790 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 791 if (F->getOpcode() == ISD::CopyFromReg) { 792 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 793 continue; 794 } else if (F->getOpcode() == ISD::CopyToReg) { 795 // Skip CopyToReg nodes that are internal to the glue chain. 796 continue; 797 } 798 // Collect declared implicit uses. 799 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 800 UsedRegs.append(MCID.getImplicitUses(), 801 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 802 // In addition to declared implicit uses, we must also check for 803 // direct RegisterSDNode operands. 804 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 805 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 806 unsigned Reg = R->getReg(); 807 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 808 UsedRegs.push_back(Reg); 809 } 810 } 811 } 812 813 // Finally mark unused registers as dead. 814 if (!UsedRegs.empty() || II.getImplicitDefs()) 815 MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 816 817 // Run post-isel target hook to adjust this instruction if needed. 818#ifdef NDEBUG 819 if (II.hasPostISelHook()) 820#endif 821 TLI->AdjustInstrPostInstrSelection(MI, Node); 822} 823 824/// EmitSpecialNode - Generate machine code for a target-independent node and 825/// needed dependencies. 826void InstrEmitter:: 827EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 828 DenseMap<SDValue, unsigned> &VRBaseMap) { 829 switch (Node->getOpcode()) { 830 default: 831#ifndef NDEBUG 832 Node->dump(); 833#endif 834 llvm_unreachable("This target-independent node should have been selected!"); 835 case ISD::EntryToken: 836 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 837 case ISD::MERGE_VALUES: 838 case ISD::TokenFactor: // fall thru 839 break; 840 case ISD::CopyToReg: { 841 unsigned SrcReg; 842 SDValue SrcVal = Node->getOperand(2); 843 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 844 SrcReg = R->getReg(); 845 else 846 SrcReg = getVR(SrcVal, VRBaseMap); 847 848 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 849 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 850 break; 851 852 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 853 DestReg).addReg(SrcReg); 854 break; 855 } 856 case ISD::CopyFromReg: { 857 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 858 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 859 break; 860 } 861 case ISD::EH_LABEL: { 862 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 863 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 864 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 865 break; 866 } 867 868 case ISD::INLINEASM: { 869 unsigned NumOps = Node->getNumOperands(); 870 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 871 --NumOps; // Ignore the glue operand. 872 873 // Create the inline asm machine instruction. 874 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 875 TII->get(TargetOpcode::INLINEASM)); 876 877 // Add the asm string as an external symbol operand. 878 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 879 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 880 MI->addOperand(MachineOperand::CreateES(AsmStr)); 881 882 // Add the HasSideEffect and isAlignStack bits. 883 int64_t ExtraInfo = 884 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 885 getZExtValue(); 886 MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); 887 888 // Add all of the operand registers to the instruction. 889 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 890 unsigned Flags = 891 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 892 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 893 894 MI->addOperand(MachineOperand::CreateImm(Flags)); 895 ++i; // Skip the ID value. 896 897 switch (InlineAsm::getKind(Flags)) { 898 default: llvm_unreachable("Bad flags!"); 899 case InlineAsm::Kind_RegDef: 900 for (; NumVals; --NumVals, ++i) { 901 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 902 // FIXME: Add dead flags for physical and virtual registers defined. 903 // For now, mark physical register defs as implicit to help fast 904 // regalloc. This makes inline asm look a lot like calls. 905 MI->addOperand(MachineOperand::CreateReg(Reg, true, 906 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 907 } 908 break; 909 case InlineAsm::Kind_RegDefEarlyClobber: 910 case InlineAsm::Kind_Clobber: 911 for (; NumVals; --NumVals, ++i) { 912 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 913 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 914 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 915 /*isKill=*/ false, 916 /*isDead=*/ false, 917 /*isUndef=*/false, 918 /*isEarlyClobber=*/ true)); 919 } 920 break; 921 case InlineAsm::Kind_RegUse: // Use of register. 922 case InlineAsm::Kind_Imm: // Immediate. 923 case InlineAsm::Kind_Mem: // Addressing mode. 924 // The addressing mode has been selected, just add all of the 925 // operands to the machine instruction. 926 for (; NumVals; --NumVals, ++i) 927 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 928 /*IsDebug=*/false, IsClone, IsCloned); 929 break; 930 } 931 } 932 933 // Get the mdnode from the asm if it exists and add it to the instruction. 934 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 935 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 936 if (MD) 937 MI->addOperand(MachineOperand::CreateMetadata(MD)); 938 939 MBB->insert(InsertPos, MI); 940 break; 941 } 942 } 943} 944 945/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 946/// at the given position in the given block. 947InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 948 MachineBasicBlock::iterator insertpos) 949 : MF(mbb->getParent()), 950 MRI(&MF->getRegInfo()), 951 TM(&MF->getTarget()), 952 TII(TM->getInstrInfo()), 953 TRI(TM->getRegisterInfo()), 954 TLI(TM->getTargetLowering()), 955 MBB(mbb), InsertPos(insertpos) { 956} 957