/external/clang/test/PCH/ |
H A D | cxx-reference.h | 3 typedef char (&LR); typedef 10 LR &lrlr = c; 11 LR &&rrlr = c;
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/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | PointerArithChecker.cpp | 44 const MemRegion *LR = LV.getAsRegion(); local 46 if (!LR || !RV.isConstant()) 51 if (isa<VarRegion>(LR) || isa<CodeTextRegion>(LR) || 52 isa<CompoundLiteralRegion>(LR)) {
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H A D | PointerSubChecker.cpp | 47 const MemRegion *LR = LV.getAsRegion(); local 50 if (!(LR && RR)) 53 const MemRegion *BaseLR = LR->getBaseRegion();
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUFrameLowering.h | 27 std::pair<unsigned, int> LR[1]; member in class:llvm::SPUFrameLowering 69 //! Minimum frame size (enough to spill LR + SP)
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/external/valgrind/main/coregrind/m_dispatch/ |
H A D | dispatch-s390x-linux.S | 52 #undef LR 53 #define LR S390_REGNO_LINK_REGISTER define 135 cannot possibly modify the LR. How else would it be able to return 136 to the location in the LR otherwise? */ 137 basr LR,0 190 will return to the beginning of this loop start by issuing br LR. 204 bras LR,innermost_loop 296 br LR 341 basr LR,%r11
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/external/nist-sip/java/gov/nist/javax/sip/address/ |
H A D | NetObject.java | 57 protected static final String LR = "lr"; field in class:NetObject
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/external/llvm/lib/CodeGen/ |
H A D | ExecutionDepsFix.cpp | 578 const LiveReg &LR = LiveRegs[rx]; local 580 if (!LR.Value->getCommonDomains(available)) { 588 if (LR.Def < i->Def) { 590 Regs.insert(i, LR); 594 Regs.push_back(LR);
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H A D | RegAllocFast.cpp | 217 void RAFast::addKillFlag(const LiveReg &LR) { argument 218 if (!LR.LastUse) return; 219 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); 220 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { 221 if (MO.getReg() == LR.PhysReg) 224 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 261 LiveReg &LR local 483 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument [all...] |
H A D | LiveIntervalAnalysis.cpp | 241 LiveRange LR(defIndex, killIdx, ValNo); 242 interval.addRange(LR); 243 DEBUG(dbgs() << " +" << LR << "\n"); 270 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), 272 interval.addRange(LR); 273 DEBUG(dbgs() << " +" << LR); 291 LiveRange LR(Start, killIdx, ValNo); 292 interval.addRange(LR); 293 DEBUG(dbgs() << " +" << LR); 338 LiveRange LR(DefInde 1069 const LiveRange& LR = *LRI; local 1127 LiveRange* LR = LI->getLiveRangeContaining(OldIdx); local 1132 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot()); local 1149 LiveRange* LR = EI->second; local 1156 LiveRange* LR = II->second; local 1167 LiveRange* LR = EI->second; local 1213 LiveRange* LR = P.second; local 1225 LiveRange* LR = P.second; local 1273 LiveRange* LR = P.second; local 1291 LiveRange* LR = P.second; local 1329 LiveRange* LR = P.second; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 293 // Check if the link register (LR) must be saved. 453 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 493 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 538 // Check if the link register (LR) has been saved. 722 /// MustSaveLR - Return true if this function requires that we save the LR 725 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { argument 728 // We need a save/restore of LR if there is any def of LR (which is 730 // some use of the LR stack slot (e.g. for builtin_return_address). 731 // (LR come 743 unsigned LR = RegInfo->getRARegister(); local [all...] |
/external/llvm/lib/Analysis/ |
H A D | ValueTracking.cpp | 665 Value *LR = LU->getOperand(1); local 668 L = LR; 669 else if (LR == I)
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/external/llvm/include/llvm/ADT/ |
H A D | ImmutableSet.h | 504 TreeTy *LR = getRight(L); local 506 if (getHeight(LL) >= getHeight(LR)) 507 return createNode(LL, L, createNode(LR,V,R)); 509 assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1"); 511 TreeTy *LRL = getLeft(LR); 512 TreeTy *LRR = getRight(LR); 514 return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R));
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/external/opencv/ml/src/ |
H A D | mlboost.cpp | 579 // LR - ... primary split sends to the left and the surrogate split sends to the right 584 double LL = 0, RL = 0, LR, RR; local 599 LR = (sum_abs - sum)*0.5; 602 // LR of them are sent to the left by primary split, and RR - to the right. 603 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value. 612 LL += w; LR -= w; 622 if( RL + LR > best_val && sorted[i].val + epsilon < sorted[i+1].val ) 624 best_val = RL + LR; 644 // LR - ... primary split sends to the left and the surrogate split sends to the right
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H A D | mltree.cpp | 2055 // LR - ... primary split sends to the left and the surrogate split sends to the right 2063 int LL = 0, RL = 0, LR, RR; local 2075 LR = (sum_abs - sum) >> 1; 2078 // LR of them are sent to the left by primary split, and RR - to the right. 2079 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value. 2086 LL++; LR--; 2096 if( RL + LR > _best_val && sorted[i].val + epsilon < sorted[i+1].val ) 2098 best_val = RL + LR; 2107 double LL = 0, RL = 0, LR, RR; local 2124 LR [all...] |
/external/qemu/tcg/ppc/ |
H A D | tcg-target.c | 385 #define LR SPR(8, 0) macro 502 tcg_out32 (s, MTSPR | RS (arg) | LR); 924 tcg_out32 (s, MFSPR | RT (0) | LR); 954 tcg_out32 (s, MTSPR | RS (0) | LR);
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/external/qemu/tcg/ppc64/ |
H A D | tcg-target.c | 377 #define LR SPR(8, 0) macro 509 tcg_out32 (s, MTSPR | RS (arg) | LR); 873 + 8 /* LR */ 890 tcg_out32 (s, MFSPR | RT (0) | LR); 922 tcg_out32 (s, MTSPR | RS (0) | LR);
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/external/clang/lib/Serialization/ |
H A D | ASTReader.cpp | 141 StringRef LR = L[0], RR = R[0].Data; local 146 if (LR.size() == RR.size()) { 148 if (LR != RR) 159 LR = L[LI]; 161 } else if (LR.size() < RR.size()) { 163 if (!RR.startswith(LR)) 167 RR = RR.substr(LR.size()); 168 LR = L[LI]; 171 if (!LR.startswith(RR)) 175 LR [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 2408 SDValue LL, LR, RL, RR, CC0, CC1; local 2564 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2568 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2571 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2573 LR.getValueType(), LL, RL); 2575 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2578 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2580 LR.getValueType(), LL, RL); 2582 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op 3007 SDValue LL, LR, RL, RR, CC0, CC1; local [all...] |