/external/llvm/include/llvm/ |
H A D | Constant.h | 47 Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps) argument 48 : User(ty, vty, Ops, NumOps) {}
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H A D | User.h | 52 User(Type *ty, unsigned vty, Use *OpList, unsigned NumOps) argument 53 : Value(ty, vty), OperandList(OpList), NumOperands(NumOps) {}
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H A D | InlineAsm.h | 232 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) { argument 233 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!"); 235 return Kind | (NumOps << 3);
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H A D | Constants.h | 811 ConstantExpr(Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps) argument 812 : Constant(ty, ConstantExprVal, Ops, NumOps) {
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H A D | GlobalValue.h | 59 GlobalValue(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps, argument 61 : Constant(ty, vty, Ops, NumOps), Linkage(linkage),
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H A D | InstrTypes.h | 38 Use *Ops, unsigned NumOps, 40 : Instruction(Ty, iType, Ops, NumOps, InsertBefore) {} 43 Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd) 44 : Instruction(Ty, iType, Ops, NumOps, InsertAtEnd) {} 37 TerminatorInst(Type *Ty, Instruction::TermOps iType, Use *Ops, unsigned NumOps, Instruction *InsertBefore = 0) argument 42 TerminatorInst(Type *Ty, Instruction::TermOps iType, Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd) argument
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/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 120 unsigned NumOps = Outs.size(); local 121 for (unsigned i = 0; i != NumOps; ++i) { 139 unsigned NumOps = ArgVTs.size(); local 140 for (unsigned i = 0; i != NumOps; ++i) {
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H A D | MachineVerifier.cpp | 720 unsigned NumOps; local 721 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) { 726 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
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H A D | TwoAddressInstructionPass.cpp | 395 unsigned NumOps = MI.isInlineAsm() local 397 for (unsigned i = 0; i != NumOps; ++i) { 1205 unsigned NumOps = MI->getNumOperands(); local 1207 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 136 unsigned NumOps = Outs.size(); local 146 for (; i != NumOps; ++i) { 164 unsigned NumOps = ArgVTs.size(); local 165 for (unsigned i = 0; i != NumOps; ++i) {
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H A D | HexagonISelLowering.cpp | 672 unsigned NumOps = Node->getNumOperands(); local 673 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 674 --NumOps; // Ignore the flag operand. 676 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 209 unsigned NumOps = Node->getNumOperands(); local 210 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 211 Chain = Node->getOperand(NumOps-1).getNode();
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H A D | ScheduleDAGFast.cpp | 477 unsigned NumOps = Node->getNumOperands(); local 478 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 479 --NumOps; // Ignore the glue operand. 481 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
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H A D | LegalizeTypes.cpp | 415 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i) 1020 unsigned NumOps = N->getNumOperands(); local 1022 if (NumOps == 0) { 1024 } else if (NumOps == 1) { 1027 } else if (NumOps == 2) { 1031 SmallVector<SDValue, 8> Ops(NumOps); 1032 for (unsigned i = 0; i < NumOps; ++i) 1035 return MakeLibCall(LC, N->getValueType(0), &Ops[0], NumOps, isSigned, dl); 1041 const SDValue *Ops, unsigned NumOps, 1040 MakeLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl) argument [all...] |
H A D | ScheduleDAGRRList.cpp | 1251 unsigned NumOps = Node->getNumOperands(); local 1252 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 1253 --NumOps; // Ignore the glue operand. 1255 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 2660 unsigned NumOps = MCID.getNumOperands() - NumRes; 2661 for (unsigned i = 0; i != NumOps; ++i) { 2887 unsigned NumOps = MCID.getNumOperands() - NumRes; 2888 for (unsigned j = 0; j != NumOps; ++j) {
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H A D | SelectionDAGISel.cpp | 1952 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1972 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2742 unsigned NumOps = MatcherTable[MatcherIndex++]; 2744 for (unsigned i = 0; i != NumOps; ++i) { 1951 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) argument
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H A D | LegalizeVectorTypes.cpp | 1517 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); local 1518 if (NumOps != ConcatEnd ) { 1520 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1523 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 2497 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); local 2498 SmallVector<SDValue, 16> WidenOps(NumOps); 2504 for (; i != NumOps; ++i) 2507 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
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/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 169 unsigned NumOps = Desc.getNumOperands(); local 170 if (NumOps) { 171 bool isTwoAddr = NumOps > 1 && 176 for (unsigned e = NumOps; i != e; ++i) { 194 for (unsigned e = NumOps; i != e; ++i) { 206 for (; i != NumOps; ++i) { 223 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) 240 for (unsigned e = NumOps; i != e; ++i) { 936 unsigned NumOps = Desc->getNumOperands(); 938 if (NumOps > [all...] |
/external/llvm/lib/VMCore/ |
H A D | Instruction.cpp | 23 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, argument 25 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) { 37 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, argument 39 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
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/external/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.cpp | 71 unsigned NumOps = 1; local 92 NumOps = NumArgs; 117 OperandType, MIOperandNo, NumOps, 119 MIOperandNo += NumOps;
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H A D | DAGISelMatcherEmitter.cpp | 646 unsigned NumOps = P.getNumOperands(); local 649 ++NumOps; // Get the chained node too. 652 OS << " Result.resize(NextRes+" << NumOps << ");\n"; local 667 for (unsigned i = 0; i != NumOps; ++i)
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 658 unsigned NumOps = MCID.getNumOperands(); local 659 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 660 if (HasCC && MI->getOperand(NumOps-1).isDead()) 684 unsigned NumOps = MCID.getNumOperands(); local 686 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) 749 unsigned NumOps = MCID.getNumOperands(); local 750 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 751 if (HasCC && MI->getOperand(NumOps-1).isDead()) 775 unsigned NumOps = MCID.getNumOperands(); local 777 if (i < NumOps [all...] |
H A D | ARMConstantIslandPass.cpp | 1853 unsigned NumOps = MCID.getNumOperands(); local 1854 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2); 1979 unsigned NumOps = MCID.getNumOperands(); 1980 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2);
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 573 unsigned NumOps = Desc.getNumOperands(); local 575 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 577 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) { 578 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 735 unsigned NumOps = MI.getNumOperands(); local 737 bool isTwoAddr = NumOps > 1 && 742 for (; i != NumOps; ++i) { 760 for (; i != NumOps; ++i) { 772 for (; i != NumOps; ++i) { 789 if (NumOps > 978 unsigned NumOps = Desc.getNumOperands(); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 683 unsigned NumOps) 686 OperandList(NumOps ? new SDUse[NumOps] : 0), 688 NumOperands(NumOps), NumValues(VTs.NumVTs), 690 for (unsigned i = 0; i != NumOps; ++i) { 906 unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO); 1085 const SDValue *Ops, unsigned NumOps, 1087 : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) { 1565 unsigned NumOps, ISD::CvtCode Code) 1566 : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps), 1084 MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO) argument 1564 CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops, unsigned NumOps, ISD::CvtCode Code) argument [all...] |