/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 46 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { argument 50 DwarfLLVMRegPair Key = { RegNum, 0 }; 52 if (I == M+Size || I->FromReg != RegNum) 57 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { argument 61 DwarfLLVMRegPair Key = { RegNum, 0 }; 63 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 67 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { 68 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 69 if (I == L2SEHRegs.end()) return (int)RegNum; [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 305 getDwarfRegNum(unsigned RegNum, bool isEH) const { argument
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeAsmPrinter.cpp | 137 unsigned RegNum = getMBlazeRegisterNumbering(Reg); local 139 CPUBitmask |= (1 << RegNum);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 148 unsigned RegNum = getMipsRegisterNumbering(Reg); local 150 FPUBitmask |= (3 << RegNum); 156 FPUBitmask |= (1 << RegNum); 163 unsigned RegNum = getMipsRegisterNumbering(Reg); local 164 CPUBitmask |= (1 << RegNum);
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 88 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { argument 89 switch (getLLVMRegNum(RegNum, isEH)) {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 122 unsigned RegNum; member in union:__anon8898::CountValue::Values 124 Values(unsigned r) : RegNum(r) {} 141 return Contents.RegNum; 144 Contents.RegNum = Val;
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/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 96 unsigned RegNum; member in struct:__anon8910::MBlazeOperand::__anon8911::__anon8913 147 return Reg.RegNum; 234 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { argument 236 Op->Reg.RegNum = RegNum;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 135 unsigned RegNum; member in union:__anon8964::CountValue::Values 137 Values(unsigned r) : RegNum(r) {} 154 return Contents.RegNum; 157 Contents.RegNum = Val;
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H A D | PPCISelLowering.cpp | 1645 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local 1649 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1650 // need to skip a register if RegNum is odd. 1651 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1652 State.AllocateReg(ArgRegs[RegNum]); 1673 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local 1677 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1678 State.AllocateReg(ArgRegs[RegNum]); [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 1180 unsigned RegNum = GetX86RegNum(MO) << 4; local 1182 RegNum |= 1 << 7; 1190 RegNum |= Val; 1193 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 88 int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic); 142 unsigned RegNum; member in struct:__anon8937::MipsOperand::__anon8938::__anon8940 200 return Reg.RegNum; 227 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { argument 229 Op->Reg.RegNum = RegNum; 416 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum,StringRef Mnemonic) { argument 420 if (RegNum != 29) 425 if (RegNum > 31) 428 return getReg(Mips::CPURegsRegClassID,RegNum); 433 int RegNum = -1; local [all...] |
/external/clang/include/clang/Basic/ |
H A D | TargetInfo.h | 537 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1400 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); local 1402 RegNum < 16); 1403 Binary |= 0x1 << RegNum;
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H A D | ARMLoadStoreOptimizer.cpp | 485 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local 491 ((isNotVFP && RegNum > PRegNum) || 492 ((Count < Limit) && RegNum == PRegNum+1))) { 494 PRegNum = RegNum;
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1239 unsigned RegNum = Registers[i]->EnumValue; local 1240 if (AllocatableRegs.count(RegNum)) 1243 UberSetIDs.join(0, RegNum);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 346 unsigned RegNum; member in struct:__anon8852::ARMOperand::__anon8853::__anon8862 351 unsigned RegNum; member in struct:__anon8852::ARMOperand::__anon8853::__anon8863 380 unsigned RegNum; member in struct:__anon8852::ARMOperand::__anon8853::__anon8867 510 return Reg.RegNum; 1139 .contains(VectorList.RegNum)); 1155 .contains(VectorList.RegNum)); 1182 .contains(VectorList.RegNum)); 1409 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local 1410 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1746 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2109 CreateCCOut(unsigned RegNum, SMLoc S) argument 2126 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument 2211 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2222 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2234 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2286 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument 2471 unsigned RegNum = MatchRegisterName(lowerCase); local [all...] |