1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineModuleInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/MC/MCAsmInfo.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/STLExtras.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "X86GenRegisterInfo.inc"
44
45using namespace llvm;
46
47cl::opt<bool>
48ForceStackAlign("force-align-stack",
49                 cl::desc("Force align the stack to the minimum alignment"
50                           " needed for the function."),
51                 cl::init(false), cl::Hidden);
52
53cl::opt<bool>
54EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
58                                 const TargetInstrInfo &tii)
59  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
60                         ? X86::RIP : X86::EIP,
61                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
62                       X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
63                       TM(tm), TII(tii) {
64  X86_MC::InitLLVM2SEHRegisterMapping(this);
65
66  // Cache some information.
67  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68  Is64Bit = Subtarget->is64Bit();
69  IsWin64 = Subtarget->isTargetWin64();
70
71  if (Is64Bit) {
72    SlotSize = 8;
73    StackPtr = X86::RSP;
74    FramePtr = X86::RBP;
75  } else {
76    SlotSize = 4;
77    StackPtr = X86::ESP;
78    FramePtr = X86::EBP;
79  }
80  // Use a callee-saved register as the base pointer.  These registers must
81  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
82  // requires GOT in the EBX register before function calls via PLT GOT pointer.
83  BasePtr = Is64Bit ? X86::RBX : X86::ESI;
84}
85
86/// getCompactUnwindRegNum - This function maps the register to the number for
87/// compact unwind encoding. Return -1 if the register isn't valid.
88int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
89  switch (getLLVMRegNum(RegNum, isEH)) {
90  case X86::EBX: case X86::RBX: return 1;
91  case X86::ECX: case X86::R12: return 2;
92  case X86::EDX: case X86::R13: return 3;
93  case X86::EDI: case X86::R14: return 4;
94  case X86::ESI: case X86::R15: return 5;
95  case X86::EBP: case X86::RBP: return 6;
96  }
97
98  return -1;
99}
100
101bool
102X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
103  // Only enable when post-RA scheduling is enabled and this is needed.
104  return TM.getSubtargetImpl()->postRAScheduler();
105}
106
107int
108X86RegisterInfo::getSEHRegNum(unsigned i) const {
109  int reg = X86_MC::getX86RegNum(i);
110  switch (i) {
111  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
112  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
113  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
114  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
115  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
116  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
117  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119  case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
120  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
121  case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
122  case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
123    reg += 8;
124  }
125  return reg;
126}
127
128const TargetRegisterClass *
129X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
130                                       unsigned Idx) const {
131  // The sub_8bit sub-register index is more constrained in 32-bit mode.
132  // It behaves just like the sub_8bit_hi index.
133  if (!Is64Bit && Idx == X86::sub_8bit)
134    Idx = X86::sub_8bit_hi;
135
136  // Forward to TableGen's default version.
137  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
138}
139
140const TargetRegisterClass *
141X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
142                                          const TargetRegisterClass *B,
143                                          unsigned SubIdx) const {
144  // The sub_8bit sub-register index is more constrained in 32-bit mode.
145  if (!Is64Bit && SubIdx == X86::sub_8bit) {
146    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
147    if (!A)
148      return 0;
149  }
150  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
151}
152
153const TargetRegisterClass*
154X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
155  // Don't allow super-classes of GR8_NOREX.  This class is only used after
156  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
157  // to the full GR8 register class in 64-bit mode, so we cannot allow the
158  // reigster class inflation.
159  //
160  // The GR8_NOREX class is always used in a way that won't be constrained to a
161  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
162  // full GR8 class.
163  if (RC == &X86::GR8_NOREXRegClass)
164    return RC;
165
166  const TargetRegisterClass *Super = RC;
167  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
168  do {
169    switch (Super->getID()) {
170    case X86::GR8RegClassID:
171    case X86::GR16RegClassID:
172    case X86::GR32RegClassID:
173    case X86::GR64RegClassID:
174    case X86::FR32RegClassID:
175    case X86::FR64RegClassID:
176    case X86::RFP32RegClassID:
177    case X86::RFP64RegClassID:
178    case X86::RFP80RegClassID:
179    case X86::VR128RegClassID:
180    case X86::VR256RegClassID:
181      // Don't return a super-class that would shrink the spill size.
182      // That can happen with the vector and float classes.
183      if (Super->getSize() == RC->getSize())
184        return Super;
185    }
186    Super = *I++;
187  } while (Super);
188  return RC;
189}
190
191const TargetRegisterClass *
192X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
193                                                                         const {
194  switch (Kind) {
195  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
196  case 0: // Normal GPRs.
197    if (TM.getSubtarget<X86Subtarget>().is64Bit())
198      return &X86::GR64RegClass;
199    return &X86::GR32RegClass;
200  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
201    if (TM.getSubtarget<X86Subtarget>().is64Bit())
202      return &X86::GR64_NOSPRegClass;
203    return &X86::GR32_NOSPRegClass;
204  case 2: // Available for tailcall (not callee-saved GPRs).
205    if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
206      return &X86::GR64_TCW64RegClass;
207    if (TM.getSubtarget<X86Subtarget>().is64Bit())
208      return &X86::GR64_TCRegClass;
209    return &X86::GR32_TCRegClass;
210  }
211}
212
213const TargetRegisterClass *
214X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
215  if (RC == &X86::CCRRegClass) {
216    if (Is64Bit)
217      return &X86::GR64RegClass;
218    else
219      return &X86::GR32RegClass;
220  }
221  return RC;
222}
223
224unsigned
225X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
226                                     MachineFunction &MF) const {
227  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
228
229  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
230  switch (RC->getID()) {
231  default:
232    return 0;
233  case X86::GR32RegClassID:
234    return 4 - FPDiff;
235  case X86::GR64RegClassID:
236    return 12 - FPDiff;
237  case X86::VR128RegClassID:
238    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
239  case X86::VR64RegClassID:
240    return 4;
241  }
242}
243
244const uint16_t *
245X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
246  bool callsEHReturn = false;
247  bool ghcCall = false;
248
249  if (MF) {
250    callsEHReturn = MF->getMMI().callsEHReturn();
251    const Function *F = MF->getFunction();
252    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
253  }
254
255  if (ghcCall)
256    return CSR_NoRegs_SaveList;
257  if (Is64Bit) {
258    if (IsWin64)
259      return CSR_Win64_SaveList;
260    if (callsEHReturn)
261      return CSR_64EHRet_SaveList;
262    return CSR_64_SaveList;
263  }
264  if (callsEHReturn)
265    return CSR_32EHRet_SaveList;
266  return CSR_32_SaveList;
267}
268
269const uint32_t*
270X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
271  if (CC == CallingConv::GHC)
272    return CSR_NoRegs_RegMask;
273  if (!Is64Bit)
274    return CSR_32_RegMask;
275  if (IsWin64)
276    return CSR_Win64_RegMask;
277  return CSR_64_RegMask;
278}
279
280BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
281  BitVector Reserved(getNumRegs());
282  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
283
284  // Set the stack-pointer register and its aliases as reserved.
285  Reserved.set(X86::RSP);
286  for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
287    Reserved.set(*I);
288
289  // Set the instruction pointer register and its aliases as reserved.
290  Reserved.set(X86::RIP);
291  for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I)
292    Reserved.set(*I);
293
294  // Set the frame-pointer register and its aliases as reserved if needed.
295  if (TFI->hasFP(MF)) {
296    Reserved.set(X86::RBP);
297    for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I)
298      Reserved.set(*I);
299  }
300
301  // Set the base-pointer register and its aliases as reserved if needed.
302  if (hasBasePointer(MF)) {
303    CallingConv::ID CC = MF.getFunction()->getCallingConv();
304    const uint32_t* RegMask = getCallPreservedMask(CC);
305    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
306      report_fatal_error(
307        "Stack realignment in presence of dynamic allocas is not supported with"
308        "this calling convention.");
309
310    Reserved.set(getBaseRegister());
311    for (MCSubRegIterator I(getBaseRegister(), this); I.isValid(); ++I)
312      Reserved.set(*I);
313  }
314
315  // Mark the segment registers as reserved.
316  Reserved.set(X86::CS);
317  Reserved.set(X86::SS);
318  Reserved.set(X86::DS);
319  Reserved.set(X86::ES);
320  Reserved.set(X86::FS);
321  Reserved.set(X86::GS);
322
323  // Mark the floating point stack registers as reserved.
324  Reserved.set(X86::ST0);
325  Reserved.set(X86::ST1);
326  Reserved.set(X86::ST2);
327  Reserved.set(X86::ST3);
328  Reserved.set(X86::ST4);
329  Reserved.set(X86::ST5);
330  Reserved.set(X86::ST6);
331  Reserved.set(X86::ST7);
332
333  // Reserve the registers that only exist in 64-bit mode.
334  if (!Is64Bit) {
335    // These 8-bit registers are part of the x86-64 extension even though their
336    // super-registers are old 32-bits.
337    Reserved.set(X86::SIL);
338    Reserved.set(X86::DIL);
339    Reserved.set(X86::BPL);
340    Reserved.set(X86::SPL);
341
342    for (unsigned n = 0; n != 8; ++n) {
343      // R8, R9, ...
344      static const uint16_t GPR64[] = {
345        X86::R8,  X86::R9,  X86::R10, X86::R11,
346        X86::R12, X86::R13, X86::R14, X86::R15
347      };
348      for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI)
349        Reserved.set(*AI);
350
351      // XMM8, XMM9, ...
352      assert(X86::XMM15 == X86::XMM8+7);
353      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
354        Reserved.set(*AI);
355    }
356  }
357
358  return Reserved;
359}
360
361//===----------------------------------------------------------------------===//
362// Stack Frame Processing methods
363//===----------------------------------------------------------------------===//
364
365bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
366   const MachineFrameInfo *MFI = MF.getFrameInfo();
367
368   if (!EnableBasePointer)
369     return false;
370
371   // When we need stack realignment and there are dynamic allocas, we can't
372   // reference off of the stack pointer, so we reserve a base pointer.
373   if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
374     return true;
375
376   return false;
377}
378
379bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
380  const MachineFrameInfo *MFI = MF.getFrameInfo();
381  const MachineRegisterInfo *MRI = &MF.getRegInfo();
382  if (!MF.getTarget().Options.RealignStack)
383    return false;
384
385  // Stack realignment requires a frame pointer.  If we already started
386  // register allocation with frame pointer elimination, it is too late now.
387  if (!MRI->canReserveReg(FramePtr))
388    return false;
389
390  // If a base pointer is necessary.  Check that it isn't too late to reserve
391  // it.
392  if (MFI->hasVarSizedObjects())
393    return MRI->canReserveReg(BasePtr);
394  return true;
395}
396
397bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
398  const MachineFrameInfo *MFI = MF.getFrameInfo();
399  const Function *F = MF.getFunction();
400  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
401  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
402                               F->hasFnAttr(Attribute::StackAlignment));
403
404  // If we've requested that we force align the stack do so now.
405  if (ForceStackAlign)
406    return canRealignStack(MF);
407
408  return requiresRealignment && canRealignStack(MF);
409}
410
411bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
412                                           unsigned Reg, int &FrameIdx) const {
413  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
414
415  if (Reg == FramePtr && TFI->hasFP(MF)) {
416    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
417    return true;
418  }
419  return false;
420}
421
422static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
423  if (is64Bit) {
424    if (isInt<8>(Imm))
425      return X86::SUB64ri8;
426    return X86::SUB64ri32;
427  } else {
428    if (isInt<8>(Imm))
429      return X86::SUB32ri8;
430    return X86::SUB32ri;
431  }
432}
433
434static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
435  if (is64Bit) {
436    if (isInt<8>(Imm))
437      return X86::ADD64ri8;
438    return X86::ADD64ri32;
439  } else {
440    if (isInt<8>(Imm))
441      return X86::ADD32ri8;
442    return X86::ADD32ri;
443  }
444}
445
446void X86RegisterInfo::
447eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
448                              MachineBasicBlock::iterator I) const {
449  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
450  bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
451  int Opcode = I->getOpcode();
452  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
453  DebugLoc DL = I->getDebugLoc();
454  uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
455  uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
456  I = MBB.erase(I);
457
458  if (!reseveCallFrame) {
459    // If the stack pointer can be changed after prologue, turn the
460    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
461    // adjcallstackdown instruction into 'add ESP, <amt>'
462    // TODO: consider using push / pop instead of sub + store / add
463    if (Amount == 0)
464      return;
465
466    // We need to keep the stack aligned properly.  To do this, we round the
467    // amount of space needed for the outgoing arguments up to the next
468    // alignment boundary.
469    unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
470    Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
471
472    MachineInstr *New = 0;
473    if (Opcode == TII.getCallFrameSetupOpcode()) {
474      New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
475                    StackPtr)
476        .addReg(StackPtr)
477        .addImm(Amount);
478    } else {
479      assert(Opcode == TII.getCallFrameDestroyOpcode());
480
481      // Factor out the amount the callee already popped.
482      Amount -= CalleeAmt;
483
484      if (Amount) {
485        unsigned Opc = getADDriOpcode(Is64Bit, Amount);
486        New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
487          .addReg(StackPtr).addImm(Amount);
488      }
489    }
490
491    if (New) {
492      // The EFLAGS implicit def is dead.
493      New->getOperand(3).setIsDead();
494
495      // Replace the pseudo instruction with a new instruction.
496      MBB.insert(I, New);
497    }
498
499    return;
500  }
501
502  if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
503    // If we are performing frame pointer elimination and if the callee pops
504    // something off the stack pointer, add it back.  We do this until we have
505    // more advanced stack pointer tracking ability.
506    unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
507    MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
508      .addReg(StackPtr).addImm(CalleeAmt);
509
510    // The EFLAGS implicit def is dead.
511    New->getOperand(3).setIsDead();
512
513    // We are not tracking the stack pointer adjustment by the callee, so make
514    // sure we restore the stack pointer immediately after the call, there may
515    // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
516    MachineBasicBlock::iterator B = MBB.begin();
517    while (I != B && !llvm::prior(I)->isCall())
518      --I;
519    MBB.insert(I, New);
520  }
521}
522
523void
524X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
525                                     int SPAdj, RegScavenger *RS) const {
526  assert(SPAdj == 0 && "Unexpected");
527
528  unsigned i = 0;
529  MachineInstr &MI = *II;
530  MachineFunction &MF = *MI.getParent()->getParent();
531  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
532
533  while (!MI.getOperand(i).isFI()) {
534    ++i;
535    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
536  }
537
538  int FrameIndex = MI.getOperand(i).getIndex();
539  unsigned BasePtr;
540
541  unsigned Opc = MI.getOpcode();
542  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
543  if (hasBasePointer(MF))
544    BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
545  else if (needsStackRealignment(MF))
546    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
547  else if (AfterFPPop)
548    BasePtr = StackPtr;
549  else
550    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
551
552  // This must be part of a four operand memory reference.  Replace the
553  // FrameIndex with base register with EBP.  Add an offset to the offset.
554  MI.getOperand(i).ChangeToRegister(BasePtr, false);
555
556  // Now add the frame object offset to the offset from EBP.
557  int FIOffset;
558  if (AfterFPPop) {
559    // Tail call jmp happens after FP is popped.
560    const MachineFrameInfo *MFI = MF.getFrameInfo();
561    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
562  } else
563    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
564
565  if (MI.getOperand(i+3).isImm()) {
566    // Offset is a 32-bit integer.
567    int Imm = (int)(MI.getOperand(i + 3).getImm());
568    int Offset = FIOffset + Imm;
569    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
570           "Requesting 64-bit offset in 32-bit immediate!");
571    MI.getOperand(i + 3).ChangeToImmediate(Offset);
572  } else {
573    // Offset is symbolic. This is extremely rare.
574    uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
575    MI.getOperand(i+3).setOffset(Offset);
576  }
577}
578
579unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
580  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
581  return TFI->hasFP(MF) ? FramePtr : StackPtr;
582}
583
584unsigned X86RegisterInfo::getEHExceptionRegister() const {
585  llvm_unreachable("What is the exception register");
586}
587
588unsigned X86RegisterInfo::getEHHandlerRegister() const {
589  llvm_unreachable("What is the exception handler register");
590}
591
592namespace llvm {
593unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
594  switch (VT.getSimpleVT().SimpleTy) {
595  default: return Reg;
596  case MVT::i8:
597    if (High) {
598      switch (Reg) {
599      default: return getX86SubSuperRegister(Reg, MVT::i64, High);
600      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
601        return X86::AH;
602      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
603        return X86::DH;
604      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
605        return X86::CH;
606      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
607        return X86::BH;
608      }
609    } else {
610      switch (Reg) {
611      default: return 0;
612      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
613        return X86::AL;
614      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
615        return X86::DL;
616      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
617        return X86::CL;
618      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
619        return X86::BL;
620      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
621        return X86::SIL;
622      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
623        return X86::DIL;
624      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
625        return X86::BPL;
626      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
627        return X86::SPL;
628      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
629        return X86::R8B;
630      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
631        return X86::R9B;
632      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
633        return X86::R10B;
634      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
635        return X86::R11B;
636      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
637        return X86::R12B;
638      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
639        return X86::R13B;
640      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
641        return X86::R14B;
642      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
643        return X86::R15B;
644      }
645    }
646  case MVT::i16:
647    switch (Reg) {
648    default: return Reg;
649    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
650      return X86::AX;
651    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
652      return X86::DX;
653    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
654      return X86::CX;
655    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
656      return X86::BX;
657    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
658      return X86::SI;
659    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
660      return X86::DI;
661    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
662      return X86::BP;
663    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
664      return X86::SP;
665    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
666      return X86::R8W;
667    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
668      return X86::R9W;
669    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
670      return X86::R10W;
671    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
672      return X86::R11W;
673    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
674      return X86::R12W;
675    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
676      return X86::R13W;
677    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
678      return X86::R14W;
679    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
680      return X86::R15W;
681    }
682  case MVT::i32:
683    switch (Reg) {
684    default: return Reg;
685    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
686      return X86::EAX;
687    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
688      return X86::EDX;
689    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
690      return X86::ECX;
691    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
692      return X86::EBX;
693    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
694      return X86::ESI;
695    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
696      return X86::EDI;
697    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
698      return X86::EBP;
699    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
700      return X86::ESP;
701    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
702      return X86::R8D;
703    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
704      return X86::R9D;
705    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
706      return X86::R10D;
707    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
708      return X86::R11D;
709    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
710      return X86::R12D;
711    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
712      return X86::R13D;
713    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
714      return X86::R14D;
715    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
716      return X86::R15D;
717    }
718  case MVT::i64:
719    // For 64-bit mode if we've requested a "high" register and the
720    // Q or r constraints we want one of these high registers or
721    // just the register name otherwise.
722    if (High) {
723      switch (Reg) {
724      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
725        return X86::SI;
726      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
727        return X86::DI;
728      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
729        return X86::BP;
730      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
731        return X86::SP;
732      // Fallthrough.
733      }
734    }
735    switch (Reg) {
736    default: return Reg;
737    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
738      return X86::RAX;
739    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
740      return X86::RDX;
741    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
742      return X86::RCX;
743    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
744      return X86::RBX;
745    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
746      return X86::RSI;
747    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
748      return X86::RDI;
749    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
750      return X86::RBP;
751    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
752      return X86::RSP;
753    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
754      return X86::R8;
755    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
756      return X86::R9;
757    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
758      return X86::R10;
759    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
760      return X86::R11;
761    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
762      return X86::R12;
763    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
764      return X86::R13;
765    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
766      return X86::R14;
767    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
768      return X86::R15;
769    }
770  }
771}
772}
773
774namespace {
775  struct MSAH : public MachineFunctionPass {
776    static char ID;
777    MSAH() : MachineFunctionPass(ID) {}
778
779    virtual bool runOnMachineFunction(MachineFunction &MF) {
780      const X86TargetMachine *TM =
781        static_cast<const X86TargetMachine *>(&MF.getTarget());
782      const TargetFrameLowering *TFI = TM->getFrameLowering();
783      MachineRegisterInfo &RI = MF.getRegInfo();
784      X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
785      unsigned StackAlignment = TFI->getStackAlignment();
786
787      // Be over-conservative: scan over all vreg defs and find whether vector
788      // registers are used. If yes, there is a possibility that vector register
789      // will be spilled and thus require dynamic stack realignment.
790      for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
791        unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
792        if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
793          FuncInfo->setForceFramePointer(true);
794          return true;
795        }
796      }
797      // Nothing to do
798      return false;
799    }
800
801    virtual const char *getPassName() const {
802      return "X86 Maximal Stack Alignment Check";
803    }
804
805    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
806      AU.setPreservesCFG();
807      MachineFunctionPass::getAnalysisUsage(AU);
808    }
809  };
810
811  char MSAH::ID = 0;
812}
813
814FunctionPass*
815llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
816