Searched defs:VirtReg (Results 1 - 15 of 15) sorted by relevance

/external/llvm/lib/CodeGen/
H A DAllocationOrder.cpp25 AllocationOrder::AllocationOrder(unsigned VirtReg, argument
29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
31 VRM.getRegInfo().getRegAllocationHint(VirtReg);
H A DLiveRegMatrix.cpp72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
75 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
80 Matrix[*Units].unify(VirtReg);
86 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
90 VRM->clearVirt(VirtReg
99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
128 query(LiveInterval &VirtReg, unsigned RegUnit) argument
136 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
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H A DLiveIntervalUnion.cpp30 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { argument
31 if (VirtReg.empty())
36 LiveInterval::iterator RegPos = VirtReg.begin();
37 LiveInterval::iterator RegEnd = VirtReg.end();
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { argument
58 if (VirtReg.empty())
63 LiveInterval::iterator RegPos = VirtReg
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H A DRegisterCoalescer.h68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
H A DRegAllocBasic.cpp105 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
114 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
167 // that interfere with VirtReg. The newly spilled or split live intervals are
169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument
177 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
183 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
189 " interferences with " << VirtReg << "\n");
223 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, argument
229 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
232 switch (Matrix->checkInterference(VirtReg, PhysRe
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H A DVirtRegMap.h132 /// @brief returns true if VirtReg is assigned to its preferred physreg.
133 bool hasPreferredPhys(unsigned VirtReg) { argument
134 return getPhys(VirtReg) == getRegAllocPref(VirtReg);
147 /// getOriginal - Return the original virtual register that VirtReg descends
151 unsigned getOriginal(unsigned VirtReg) const {
152 unsigned Orig = getPreSplitReg(VirtReg);
153 return Orig ? Orig : VirtReg;
H A DLiveIntervalUnion.h88 void unify(LiveInterval &VirtReg);
91 void extract(LiveInterval &VirtReg);
108 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query
109 LiveInterval::iterator VirtRegI; // current position in VirtReg
118 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
121 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
127 VirtReg = NULL;
138 if (UserTag == UTag && VirtReg == VReg &&
145 VirtReg = VReg;
151 assert(VirtReg
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H A DPHIElimination.cpp174 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
176 static bool isImplicitlyDefined(unsigned VirtReg, argument
178 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
H A DVirtRegMap.cpp228 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); local
229 if (MRI->reg_nodbg_empty(VirtReg))
231 LiveInterval &LI = LIS->getInterval(VirtReg);
236 unsigned PhysReg = VRM->getPhys(VirtReg);
278 unsigned VirtReg = MO.getReg(); local
279 unsigned PhysReg = VRM->getPhys(VirtReg);
281 "Instruction uses unmapped VirtReg");
H A DPrologEpilogInserter.cpp821 unsigned VirtReg = 0; local
841 if (Reg != VirtReg) {
847 VirtReg = Reg;
H A DRegAllocFast.cpp72 unsigned VirtReg; // Virtual register number. member in struct:__anon8702::RAFast::LiveReg
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
163 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { argument
164 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
166 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
167 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
185 getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) argument
240 killVirtReg(unsigned VirtReg) argument
250 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument
492 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument
503 const unsigned VirtReg = LRI->VirtReg; local
572 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
605 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
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H A DRegAllocGreedy.cpp137 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
138 return ExtraRegInfo[VirtReg.reg].Stage;
141 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument
143 ExtraRegInfo[VirtReg.reg].Stage = Stage;
354 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { argument
355 if (VRM->hasPhys(VirtReg)) {
356 Matrix->unassign(LIS->getInterval(VirtReg));
364 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument
365 if (!VRM->hasPhys(VirtReg))
369 LiveInterval &LI = LIS->getInterval(VirtReg);
438 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs) argument
515 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument
586 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &NewVRegs) argument
627 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs, unsigned CostPerUseLimit) argument
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H A DInlineSpiller.cpp833 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
842 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
858 markValueUsed(&VirtReg, ParentVNI);
863 // If the instruction also writes VirtReg.reg, it had better not require the
867 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
869 markValueUsed(&VirtReg, ParentVNI);
896 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
H A DLiveDebugVariables.cpp303 /// lookupVirtReg - Find the EC leader for VirtReg or null.
304 UserValue *lookupVirtReg(unsigned VirtReg);
335 void mapVirtReg(unsigned VirtReg, UserValue *EC);
429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument
430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
431 UserValue *&Leader = virtRegToEqClass[VirtReg];
435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument
436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
903 unsigned VirtReg = Loc.getReg(); local
904 if (VRM.isAssignedReg(VirtReg)
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/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h101 unsigned VirtReg; member in struct:llvm::VReg2SUnit
104 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
107 return TargetRegisterInfo::virtReg2Index(VirtReg);

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