Searched refs:V1 (Results 76 - 100 of 103) sorted by relevance

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/external/llvm/lib/VMCore/
H A DConstants.cpp1725 Constant *ConstantExpr::getSelect(Constant *C, Constant *V1, Constant *V2) { argument
1726 assert(!SelectInst::areInvalidOperands(C, V1, V2)&&"Invalid select operands");
1728 if (Constant *SC = ConstantFoldSelectInstruction(C, V1, V2))
1732 argVec[1] = V1;
1737 return pImpl->ExprConstants.getOrCreate(V1->getType(), Key);
1853 Constant *ConstantExpr::getShuffleVector(Constant *V1, Constant *V2, argument
1855 assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) &&
1858 if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask))
1862 Type *EltTy = V1->getType()->getVectorElementType();
1866 std::vector<Constant*> ArgVec(1, V1);
[all...]
/external/libvpx/vp8/common/ppc/
H A Dfilter_bilinear_altivec.asm23 .macro load_vfilter V0, V1
27 lvx \V1, r6, r10
H A Dfilter_altivec.asm23 .macro load_hfilter V0, V1
27 lvx \V1, r5, r10
/external/llvm/include/llvm/CodeGen/
H A DLiveInterval.h259 /// are found to be equivalent. This eliminates V1, replacing all
260 /// LiveRanges with the V1 value number with the V2 value number. This can
261 /// cause merging of V1/V2 values numbers and compaction of the value space.
262 VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2);
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp1824 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1830 /// permute/shuffle the bytes from V1 and V2.
1834 /// element move from V2 into V1.
1839 SDValue V1 = Op.getOperand(0); local
1843 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1845 // If we have a single element being moved from V1 to V2, this can be handled
1849 EVT VecVT = V1.getValueType();
1931 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
1937 return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1
[all...]
/external/qemu/target-mips/
H A Dcpu.h33 uint_fast16_t V1:1; member in struct:r4k_tlb_t
H A Dhelper.c92 if (!(n ? tlb->V1 : tlb->V0))
799 if (tlb->V1) {
H A Dop_helper.c1544 if (tlb->V1) {
1583 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1628 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1703 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
/external/llvm/include/llvm/
H A DConstants.h998 static Constant *getSelect(Constant *C, Constant *V1, Constant *V2);
1057 static Constant *getShuffleVector(Constant *V1, Constant *V2, Constant *Mask);
H A DIRBuilder.h1229 Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask, argument
1231 if (Constant *V1C = dyn_cast<Constant>(V1))
1235 return Insert(new ShuffleVectorInst(V1, V2, Mask), Name);
H A DInstructions.h1660 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
1663 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
1668 static bool isValidOperands(const Value *V1, const Value *V2,
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4558 SDValue V1 = Op.getOperand(0); local
4568 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4572 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4578 SDValue V1 = Op.getOperand(0); local
4599 // Test if V1 is a SCALAR_TO_VECTOR.
4600 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4601 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4603 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4606 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4607 !isa<ConstantSDNode>(V1
[all...]
H A DARMCodeEmitter.cpp778 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); local
793 Binary |= getMachineSoImmOpValue(V1);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp3053 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); local
3057 s = V1.add(V2, APFloat::rmNearestTiesToEven);
3059 return getConstantFP(V1, VT);
3062 s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
3064 return getConstantFP(V1, VT);
3067 s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
3069 return getConstantFP(V1, VT);
3072 s = V1.divide(V2, APFloat::rmNearestTiesToEven);
3074 return getConstantFP(V1, VT);
3077 s = V1
[all...]
H A DLegalizeIntegerTypes.cpp2898 SDValue V1 = GetPromotedInteger(N->getOperand(1)); local
2901 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2990 SDValue V1 = N->getOperand(1); local
2992 V0->getValueType(0).getScalarType(), V0, V1);
/external/libvpx/vp8/encoder/ppc/
H A Dvariance_subpixel_altivec.asm24 .macro load_vfilter V0, V1
28 lvx \V1, r6, r10
/external/llvm/lib/Transforms/Scalar/
H A DCodeGenPrepare.cpp348 const Value *V1 = PN->getIncomingValueForBlock(Pred); local
357 if (V1 != V2) return false;
H A DReassociate.cpp953 Value *V1 = Ops.back();
956 return BinaryOperator::CreateAdd(V2, V1, "tmp", I);
H A DSCCP.cpp988 Constant *V1 = V1State.isConstant() ?
994 markConstant(&I, ConstantExpr::getShuffleVector(V1, V2, Mask));
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp322 .Case("v1", Mips::V1)
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4334 SDValue V1 = Op.getOperand(0); local
4424 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4427 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4429 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4433 EVT EltVT = V1.getValueType().getVectorElementType();
4447 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
H A DPPCFrameLowering.cpp42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
/external/llvm/bindings/ocaml/llvm/
H A Dllvm_ocaml.c1924 CAMLprim LLVMValueRef llvm_build_shufflevector(LLVMValueRef V1, LLVMValueRef V2, argument
1927 return LLVMBuildShuffleVector(Builder_val(B), V1, V2, Mask, String_val(Name));
/external/llvm/include/llvm-c/
H A DCore.h2476 LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef, LLVMValueRef V1,
/external/clang/lib/CodeGen/
H A DCGExprScalar.cpp773 Value* V1 = CGF.EmitScalarExpr(E->getExpr(0)); local
777 llvm::VectorType *VTy = cast<llvm::VectorType>(V1->getType());
787 return Builder.CreateShuffleVector(V1, V2, SV, "shuffle");

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