Searched refs:V2 (Results 51 - 75 of 100) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp128 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
140 V2 = RegInfo.createVirtualRegister(RC);
164 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
166 .addReg(V1).addReg(V2);
/external/llvm/unittests/Analysis/
H A DScalarEvolutionTest.cpp50 Value *V2 = new GlobalVariable(M, Ty, false, GlobalValue::ExternalLinkage, Init, "V2"); local
58 const SCEV *S2 = SE.getSCEV(V2);
78 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V2);
81 V2->replaceAllUsesWith(V1);
/external/mesa3d/src/mesa/main/
H A Dmacros.h343 #define ASSIGN_4V( V, V0, V1, V2, V3 ) \
347 V[2] = V2; \
473 #define ASSIGN_3V( V, V0, V1, V2 ) \
477 V[2] = V2; \
/external/llvm/include/llvm/Support/
H A DConstantFolder.h220 Constant *CreateShuffleVector(Constant *V1, Constant *V2, argument
222 return ConstantExpr::getShuffleVector(V1, V2, Mask);
H A DTargetFolder.h237 Constant *CreateShuffleVector(Constant *V1, Constant *V2, argument
239 return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
H A DNoFolder.h280 Instruction *CreateShuffleVector(Constant *V1, Constant *V2, argument
282 return new ShuffleVectorInst(V1, V2, Mask);
/external/llvm/lib/Analysis/
H A DAliasAnalysisEvaluator.cpp90 const Value *V2, const Module *M) {
96 WriteAsOperand(os2, V2, true, M);
89 PrintResults(const char *Msg, bool P, const Value *V1, const Value *V2, const Module *M) argument
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1804 Value *V1 = 0, *V2 = 0; local
1813 match(A, m_Add(m_Value(V1), m_Value(V2)))) {
1815 if (V1 == B && MaskedValueIsZero(V2, C2->getValue()))
1817 if (V2 == B && MaskedValueIsZero(V1, C2->getValue()))
1822 match(B, m_Add(m_Value(V1), m_Value(V2)))) {
1824 if (V1 == A && MaskedValueIsZero(V2, C1->getValue()))
1826 if (V2 == A && MaskedValueIsZero(V1, C1->getValue()))
1834 if (match(A, m_Or(m_Value(V1), m_Value(V2))) &&
1835 ((V1 == B && MaskedValueIsZero(V2, ~C1->getValue())) || // (V|N)
1836 (V2
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H A DInstCombineLoadStoreAlloca.cpp426 // load (select (Cond, &V1, &V2)) --> select(Cond, load &V1, load &V2).
432 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(2), local
435 V2->setAlignment(Align);
436 return SelectInst::Create(SI->getCondition(), V1, V2);
H A DInstCombineShifts.cpp406 Value *V1, *V2; local
465 m_And(m_Shr(m_Value(V1), m_Value(V2)),
466 m_ConstantInt(CC))) && V2 == Op1 &&
/external/clang/lib/include/
H A Davx2intrin.h157 #define _mm256_blend_epi16(V1, V2, M) __extension__ ({ \
159 __m256i __V2 = (V2); \
758 #define _mm_blend_epi32(V1, V2, M) __extension__ ({ \
760 __m128i __V2 = (V2); \
763 #define _mm256_blend_epi32(V1, V2, M) __extension__ ({ \
765 __m256i __V2 = (V2); \
841 #define _mm256_permute2x128_si256(V1, V2, M) __extension__ ({ \
843 __m256i __V2 = (V2); \
850 #define _mm256_inserti128_si256(V1, V2, O) __extension__ ({ \
852 __m128i __V2 = (V2); \
[all...]
/external/clang/lib/Headers/
H A Davx2intrin.h157 #define _mm256_blend_epi16(V1, V2, M) __extension__ ({ \
159 __m256i __V2 = (V2); \
758 #define _mm_blend_epi32(V1, V2, M) __extension__ ({ \
760 __m128i __V2 = (V2); \
763 #define _mm256_blend_epi32(V1, V2, M) __extension__ ({ \
765 __m256i __V2 = (V2); \
841 #define _mm256_permute2x128_si256(V1, V2, M) __extension__ ({ \
843 __m256i __V2 = (V2); \
850 #define _mm256_inserti128_si256(V1, V2, O) __extension__ ({ \
852 __m128i __V2 = (V2); \
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/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp59 SDValue V2);
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, argument
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
2968 SDValue V1, SDValue V2, unsigned TargetMask,
2975 return DAG.getNode(Opc, dl, VT, V1, V2,
2981 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2993 return DAG.getNode(Opc, dl, VT, V1, V2);
3726 /// the second half of V2.
4152 /// half of V2 (and in order).
4207 /// half of V2 (an
2967 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) argument
2980 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument
4209 ShouldXformToMOVLP(SDNode *V1, SDNode *V2, ArrayRef<int> Mask, EVT VT) argument
4252 SDValue V2 = N->getOperand(1); local
4350 getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4361 getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4373 getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4475 getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
5438 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, local
5568 SDValue V2 = Op.getOperand(1); local
5588 SDValue V2 = SVOp->getOperand(1); local
5661 SDValue V2 = SVOp->getOperand(1); local
5911 SDValue V2 = SVOp->getOperand(1); local
6035 SDValue V2 = SVOp->getOperand(1); local
6111 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); local
6269 SDValue V2 = SVOp->getOperand(1); local
10878 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); local
13393 SDValue V2 = SVOp->getOperand(1); local
14759 SDValue V2 = N->getOperand(1); local
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/external/llvm/lib/CodeGen/
H A DMachineModuleInfo.cpp50 virtual void allUsesReplacedWith(Value *V2);
247 void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) { argument
248 Map->UpdateForRAUWBlock(cast<BasicBlock>(getValPtr()), cast<BasicBlock>(V2));
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp62 case HexagonSubtarget::V2:
109 case HexagonSubtarget::V2:
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp30 unsigned V2, unsigned V3) {
31 return (V0 << (3*4)) | (V1 << (2*4)) | (V2 << (1*4)) | (V3 << (0*4));
29 MakeMask(unsigned V0, unsigned V1, unsigned V2, unsigned V3) argument
/external/opencv/cvaux/src/
H A Dcveigenobjects.cpp87 float *A2 = A + n * (p + 1), *V2 = V + n * (p + 1); local
89 for( q = p + 1; q < n; q++, A2 += n, V2 += n )
119 Vqi = V2[i];
123 V2[i] = (float) (Vqi * c + Vpi * s);
130 Vqi = V2[i];
134 V2[i] = (float) (Vqi * c + Vpi * s);
141 Vqi = V2[i];
145 V2[i] = (float) (Vqi * c + Vpi * s);
/external/webkit/PerformanceTests/SunSpider/tests/sunspider-0.9/
H A D3d-cube.js78 function CalcNormal(V0, V1, V2) {
82 B[i] = V2[i] - V1[i];
/external/webkit/PerformanceTests/SunSpider/tests/sunspider-0.9.1/
H A D3d-cube.js78 function CalcNormal(V0, V1, V2) {
82 B[i] = V2[i] - V1[i];
/external/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp849 DefinedSVal V2 = cast<DefinedSVal>(V2_untested); local
866 SVal Result = evalBinOp(state, Op, V2, RHS, U->getType());
879 svalBuilder.evalEQ(state, V2,svalBuilder.makeZeroVal(U->getType()));
899 state = state->BindExpr(U, LCtx, U->isPostfix() ? V2 : Result);
/external/llvm/include/llvm/ADT/
H A DAPInt.h1589 inline bool operator==(uint64_t V1, const APInt& V2) {
1590 return V2 == V1;
1593 inline bool operator!=(uint64_t V1, const APInt& V2) {
1594 return V2 != V1;
/external/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp955 Value *V2 = EmitAddTreeOfValues(I, Ops); local
956 return BinaryOperator::CreateAdd(V2, V1, "tmp", I);
1251 Instruction *V2 = BinaryOperator::CreateMul(V, MaxOccVal, "tmp", I);
1255 RedoInsts.insert(V2);
1260 return V2;
1265 Ops.insert(Ops.begin(), ValueEntry(getRank(V2), V2));
H A DCodeGenPrepare.cpp349 const Value *V2 = PN->getIncomingValueForBlock(BB); local
351 // If V2 is a phi node in BB, look up what the mapped value will be.
352 if (const PHINode *V2PN = dyn_cast<PHINode>(V2))
354 V2 = V2PN->getIncomingValueForBlock(Pred);
357 if (V1 != V2) return false;
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1480 SDValue V2, SDValue V3) {
1489 V2, SubReg2, V3, SubReg3 };
1496 SDValue V2, SDValue V3) {
1504 V2, SubReg2, V3, SubReg3 };
1511 SDValue V2, SDValue V3) {
1519 V2, SubReg2, V3, SubReg3 };
1785 SDValue V2 local
1479 QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1495 QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1510 QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1835 SDValue V2 = N->getOperand(Vec0Idx + 2); local
1953 SDValue V2 = N->getOperand(Vec0Idx + 2); local
2088 SDValue V2 = N->getOperand(FirstTblReg + 2); local
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/external/llvm/lib/VMCore/
H A DVerifier.cpp325 const Value *V1 = 0, const Value *V2 = 0,
329 WriteValue(V2);
366 #define Assert2(C, M, V1, V2) \
367 do { if (!(C)) { CheckFailed(M, V1, V2); return; } } while (0)
368 #define Assert3(C, M, V1, V2, V3) \
369 do { if (!(C)) { CheckFailed(M, V1, V2, V3); return; } } while (0)
370 #define Assert4(C, M, V1, V2, V3, V4) \
371 do { if (!(C)) { CheckFailed(M, V1, V2, V3, V4); return; } } while (0)

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