Searched refs:ADC (Results 1 - 18 of 18) sorted by relevance

/external/aac/libSBRdec/src/arm/
H A Denv_calc_arm.cpp119 ADC r3, r3, #0
/external/clang/lib/StaticAnalyzer/Core/
H A DExprEngineCallAndReturn.cpp390 const AnalysisDeclContext *ADC = CallerSFC->getAnalysisDeclContext(); local
391 assert(ADC->getCFGBuildOptions().AddInitializers && "No CFG initializers");
392 (void)ADC;
416 const AnalysisDeclContext *ADC = CallerSFC->getAnalysisDeclContext(); local
417 assert(ADC->getCFGBuildOptions().AddImplicitDtors && "No CFG destructors");
418 (void)ADC;
H A DPathDiagnostic.cpp437 AnalysisDeclContext *ADC; local
439 ADC = LAC.get<const LocationContext*>()->getAnalysisDeclContext();
441 ADC = LAC.get<AnalysisDeclContext*>();
443 ParentMap &PM = ADC->getParentMap();
454 const Stmt *Body = ADC->getBody();
458 L = ADC->getDecl()->getLocEnd();
/external/clang/lib/StaticAnalyzer/Checkers/
H A DMallocSizeofChecker.cpp176 AnalysisDeclContext *ADC = mgr.getAnalysisDeclContext(D); local
236 BR.getSourceManager(), ADC);
/external/tremolo/Tremolo/
H A Ddpen.s99 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
124 ADC r8, r6, r7 @ r8 = t+chase+bit
141 ADC r12,r8, r6 @ r12= chase+bit+1+t
156 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
181 ADC r8, r7, #0 @ r8 = chase+bit
200 ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000)
201 ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1
214 ADC r2, r7, r7 @ r8 = chase*2+C
H A Dfloor1ARM.s60 ADC r5, r6, r5, LSL #17 @ r5 = MULT31_SHIFT15
/external/qemu/distrib/sdl-1.2.15/src/audio/mint/
H A DSDL_mintaudio_xbios.c221 if (src==ADC) {
/external/v8/src/arm/
H A Dconstants-arm.h196 ADC = 5 << 21, // Add with Carry. enumerator in enum:v8::internal::Opcode
H A Dassembler-arm.cc1106 addrmod1(cond | ADC | s, src1, dst, src2);
H A Dsimulator-arm.cc2333 case ADC: {
/external/webkit/Source/JavaScriptCore/assembler/
H A DARMAssembler.h130 ADC = (0x5 << 21), enumerator in enum:JSC::ARMAssembler::__anon14303
333 emitInst(static_cast<ARMWord>(cc) | ADC, rd, rn, op2);
338 emitInst(static_cast<ARMWord>(cc) | ADC | SET_CC, rd, rn, op2);
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h252 ADD, SUB, ADC, SBB, SMUL, enumerator in enum:llvm::X86ISD::NodeType
H A DX86ISelLowering.cpp8897 Opc == X86ISD::ADC ||
11250 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11612 case X86ISD::ADC: return "X86ISD::ADC";
13281 case X86ISD::ADC:
15966 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15969 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
16023 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
16026 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
16092 case X86ISD::ADC
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/external/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s23 @ ADC (register)
H A Dbasic-arm-instructions.s15 @ ADC (immediate)
45 @ ADC (register)
46 @ ADC (shifted register)
H A Dbasic-thumb2-instructions.s18 @ ADC (immediate)
41 @ ADC (register)
/external/valgrind/main/none/tests/arm/
H A Dv6intARM.stdout.exp34 ADC
773 ADC
H A Dv6intThumb.stdout.exp1409 (T3) ADC{S}.W Rd, Rn, #constT [allegedly]
5891 ADC{S}.W Rd, Rn, Rm, {shift}
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