Searched refs:CSR0 (Results 1 - 5 of 5) sorted by relevance

/external/grub/netboot/
H A Dsk_g16.c253 * CSR0 - Status and Control flags
262 #define CSR0 0x00 macro
517 PRINTF2(("## %s: At beginning of SK_poll(). CSR0: %#hX\n",
518 SK_NAME, SK_read_reg(CSR0)));
521 csr0 = SK_read_reg(CSR0); /* store register for checking */
528 SK_write_reg(CSR0, csr0 & CSR0_CLRALL);
611 SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */
631 PRINTF2(("## %s: At beginning of SK_transmit(). CSR0: %#hX\n",
632 SK_NAME, SK_read_reg(CSR0)));
664 SK_write_reg(CSR0, CSR0_TDM
[all...]
H A Dotulip.c57 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets
162 outl(0x00000001, ioaddr + CSR0);
165 outl(0x01A08000, ioaddr + CSR0);
H A Ddepca.c251 #define CSR0 0 macro
272 ** Control and Status Register 0 (CSR0) bit definitions
471 outw(CSR0, DEPCA_ADDR);\
509 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */
518 outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */
H A Ddavicom.c64 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
506 outl(0x00000001, ioaddr + CSR0);
511 outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
63 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:davicom_offsets
H A Dtulip.c291 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
414 unsigned int csr0, csr6; /* Current CSR0, CSR6 settings. */
969 outl(0x00000001, ioaddr + CSR0);
973 outl(tp->csr0, ioaddr + CSR0);
290 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets

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