1/* Etherboot: depca.h merged, comments from Linux driver retained */ 2/* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux. 3 4 Written 1994, 1995 by David C. Davies. 5 6 7 Copyright 1994 David C. Davies 8 and 9 United States Government 10 (as represented by the Director, National Security Agency). 11 12 Copyright 1995 Digital Equipment Corporation. 13 14 15 This software may be used and distributed according to the terms of 16 the GNU Public License, incorporated herein by reference. 17 18 This driver is written for the Digital Equipment Corporation series 19 of DEPCA and EtherWORKS ethernet cards: 20 21 DEPCA (the original) 22 DE100 23 DE101 24 DE200 Turbo 25 DE201 Turbo 26 DE202 Turbo (TP BNC) 27 DE210 28 DE422 (EISA) 29 30 The driver has been tested on DE100, DE200 and DE202 cards in a 31 relatively busy network. The DE422 has been tested a little. 32 33 This driver will NOT work for the DE203, DE204 and DE205 series of 34 cards, since they have a new custom ASIC in place of the AMD LANCE 35 chip. See the 'ewrk3.c' driver in the Linux source tree for running 36 those cards. 37 38 I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from) 39 a DECstation 5000/200. 40 41 The author may be reached at davies@maniac.ultranet.com 42 43 ========================================================================= 44 45 The driver was originally based on the 'lance.c' driver from Donald 46 Becker which is included with the standard driver distribution for 47 linux. V0.4 is a complete re-write with only the kernel interface 48 remaining from the original code. 49 50 1) Lance.c code in /linux/drivers/net/ 51 2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook", 52 AMD, 1992 [(800) 222-9323]. 53 3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)", 54 AMD, Pub. #17881, May 1993. 55 4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA", 56 AMD, Pub. #16907, May 1992 57 5) "DEC EtherWORKS LC Ethernet Controller Owners Manual", 58 Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003 59 6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual", 60 Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003 61 7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR 62 Digital Equipment Corporation, 1989 63 8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual", 64 Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001 65 66 67 Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this 68 driver. 69 70 The original DEPCA card requires that the ethernet ROM address counter 71 be enabled to count and has an 8 bit NICSR. The ROM counter enabling is 72 only done when a 0x08 is read as the first address octet (to minimise 73 the chances of writing over some other hardware's I/O register). The 74 NICSR accesses have been changed to byte accesses for all the cards 75 supported by this driver, since there is only one useful bit in the MSB 76 (remote boot timeout) and it is not used. Also, there is a maximum of 77 only 48kB network RAM for this card. My thanks to Torbjorn Lindh for 78 help debugging all this (and holding my feet to the fire until I got it 79 right). 80 81 The DE200 series boards have on-board 64kB RAM for use as a shared 82 memory network buffer. Only the DE100 cards make use of a 2kB buffer 83 mode which has not been implemented in this driver (only the 32kB and 84 64kB modes are supported [16kB/48kB for the original DEPCA]). 85 86 At the most only 2 DEPCA cards can be supported on the ISA bus because 87 there is only provision for two I/O base addresses on each card (0x300 88 and 0x200). The I/O address is detected by searching for a byte sequence 89 in the Ethernet station address PROM at the expected I/O address for the 90 Ethernet PROM. The shared memory base address is 'autoprobed' by 91 looking for the self test PROM and detecting the card name. When a 92 second DEPCA is detected, information is placed in the base_addr 93 variable of the next device structure (which is created if necessary), 94 thus enabling ethif_probe initialization for the device. More than 2 95 EISA cards can be supported, but care will be needed assigning the 96 shared memory to ensure that each slot has the correct IRQ, I/O address 97 and shared memory address assigned. 98 99 ************************************************************************ 100 101 NOTE: If you are using two ISA DEPCAs, it is important that you assign 102 the base memory addresses correctly. The driver autoprobes I/O 0x300 103 then 0x200. The base memory address for the first device must be less 104 than that of the second so that the auto probe will correctly assign the 105 I/O and memory addresses on the same card. I can't think of a way to do 106 this unambiguously at the moment, since there is nothing on the cards to 107 tie I/O and memory information together. 108 109 I am unable to test 2 cards together for now, so this code is 110 unchecked. All reports, good or bad, are welcome. 111 112 ************************************************************************ 113 114 The board IRQ setting must be at an unused IRQ which is auto-probed 115 using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are 116 {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is 117 really IRQ9 in machines with 16 IRQ lines. 118 119 No 16MB memory limitation should exist with this driver as DMA is not 120 used and the common memory area is in low memory on the network card (my 121 current system has 20MB and I've not had problems yet). 122 123 The ability to load this driver as a loadable module has been added. To 124 utilise this ability, you have to do <8 things: 125 126 0) have a copy of the loadable modules code installed on your system. 127 1) copy depca.c from the /linux/drivers/net directory to your favourite 128 temporary directory. 129 2) if you wish, edit the source code near line 1530 to reflect the I/O 130 address and IRQ you're using (see also 5). 131 3) compile depca.c, but include -DMODULE in the command line to ensure 132 that the correct bits are compiled (see end of source code). 133 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a 134 kernel with the depca configuration turned off and reboot. 135 5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100] 136 [Alan Cox: Changed the code to allow command line irq/io assignments] 137 [Dave Davies: Changed the code to allow command line mem/name 138 assignments] 139 6) run the net startup bits for your eth?? interface manually 140 (usually /etc/rc.inet[12] at boot time). 141 7) enjoy! 142 143 Note that autoprobing is not allowed in loadable modules - the system is 144 already up and running and you're messing with interrupts. 145 146 To unload a module, turn off the associated interface 147 'ifconfig eth?? down' then 'rmmod depca'. 148 149 To assign a base memory address for the shared memory when running as a 150 loadable module, see 5 above. To include the adapter name (if you have 151 no PROM but know the card name) also see 5 above. Note that this last 152 option will not work with kernel built-in depca's. 153 154 The shared memory assignment for a loadable module makes sense to avoid 155 the 'memory autoprobe' picking the wrong shared memory (for the case of 156 2 depca's in a PC). 157 158 ************************************************************************ 159 Support for MCA EtherWORKS cards added 11-3-98. 160 Verified to work with up to 2 DE212 cards in a system (although not 161 fully stress-tested). 162 163 Currently known bugs/limitations: 164 165 Note: with the MCA stuff as a module, it trusts the MCA configuration, 166 not the command line for IRQ and memory address. You can 167 specify them if you want, but it will throw your values out. 168 You still have to pass the IO address it was configured as 169 though. 170 171 ************************************************************************ 172 TO DO: 173 ------ 174 175 176 Revision History 177 ---------------- 178 179 Version Date Description 180 181 0.1 25-jan-94 Initial writing. 182 0.2 27-jan-94 Added LANCE TX hardware buffer chaining. 183 0.3 1-feb-94 Added multiple DEPCA support. 184 0.31 4-feb-94 Added DE202 recognition. 185 0.32 19-feb-94 Tidy up. Improve multi-DEPCA support. 186 0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable. 187 Add jabber packet fix from murf@perftech.com 188 and becker@super.org 189 0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access. 190 0.35 8-mar-94 Added DE201 recognition. Tidied up. 191 0.351 30-apr-94 Added EISA support. Added DE422 recognition. 192 0.36 16-may-94 DE422 fix released. 193 0.37 22-jul-94 Added MODULE support 194 0.38 15-aug-94 Added DBR ROM switch in depca_close(). 195 Multi DEPCA bug fix. 196 0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0. 197 0.381 12-dec-94 Added DE101 recognition, fix multicast bug. 198 0.382 9-feb-95 Fix recognition bug reported by <bkm@star.rl.ac.uk>. 199 0.383 22-feb-95 Fix for conflict with VESA SCSI reported by 200 <stromain@alf.dec.com> 201 0.384 17-mar-95 Fix a ring full bug reported by <bkm@star.rl.ac.uk> 202 0.385 3-apr-95 Fix a recognition bug reported by 203 <ryan.niemi@lastfrontier.com> 204 0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility 205 0.40 25-May-95 Rewrite for portability & updated. 206 ALPHA support from <jestabro@amt.tay1.dec.com> 207 0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from 208 suggestion by <heiko@colossus.escape.de> 209 0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable 210 modules. 211 Add 'adapter_name' for loadable modules when no PROM. 212 Both above from a suggestion by 213 <pchen@woodruffs121.residence.gatech.edu>. 214 Add new multicasting code. 215 0.421 22-Apr-96 Fix alloc_device() bug <jari@markkus2.fimr.fi> 216 0.422 29-Apr-96 Fix depca_hw_init() bug <jari@markkus2.fimr.fi> 217 0.423 7-Jun-96 Fix module load bug <kmg@barco.be> 218 0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c 219 0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug 220 reported by <mmogilvi@elbert.uccs.edu> 221 0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards 222 by <tymm@computer.org> 223 0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <tymm@computer.org> 224 0.5 14-Nov-98 Re-spin for 2.1.x kernels. 225 0.51 27-Jun-99 Correct received packet length for CRC from 226 report by <worm@dkik.dk> 227 228 ========================================================================= 229*/ 230 231#include "etherboot.h" 232#include "nic.h" 233#include "cards.h" 234 235/* 236** I/O addresses. Note that the 2k buffer option is not supported in 237** this driver. 238*/ 239#define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */ 240#define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */ 241#define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */ 242#define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */ 243#define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */ 244#define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */ 245#define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */ 246#define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */ 247 248/* 249** These are LANCE registers addressable through DEPCA_ADDR 250*/ 251#define CSR0 0 252#define CSR1 1 253#define CSR2 2 254#define CSR3 3 255 256/* 257** NETWORK INTERFACE CSR (NI_CSR) bit definitions 258*/ 259 260#define TO 0x0100 /* Time Out for remote boot */ 261#define SHE 0x0080 /* SHadow memory Enable */ 262#define BS 0x0040 /* Bank Select */ 263#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */ 264#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */ 265#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */ 266#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */ 267#define IM 0x0004 /* Interrupt Mask (1->mask) */ 268#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */ 269#define LED 0x0001 /* LED control */ 270 271/* 272** Control and Status Register 0 (CSR0) bit definitions 273*/ 274 275#define ERR 0x8000 /* Error summary */ 276#define BABL 0x4000 /* Babble transmitter timeout error */ 277#define CERR 0x2000 /* Collision Error */ 278#define MISS 0x1000 /* Missed packet */ 279#define MERR 0x0800 /* Memory Error */ 280#define RINT 0x0400 /* Receiver Interrupt */ 281#define TINT 0x0200 /* Transmit Interrupt */ 282#define IDON 0x0100 /* Initialization Done */ 283#define INTR 0x0080 /* Interrupt Flag */ 284#define INEA 0x0040 /* Interrupt Enable */ 285#define RXON 0x0020 /* Receiver on */ 286#define TXON 0x0010 /* Transmitter on */ 287#define TDMD 0x0008 /* Transmit Demand */ 288#define STOP 0x0004 /* Stop */ 289#define STRT 0x0002 /* Start */ 290#define INIT 0x0001 /* Initialize */ 291#define INTM 0xff00 /* Interrupt Mask */ 292#define INTE 0xfff0 /* Interrupt Enable */ 293 294/* 295** CONTROL AND STATUS REGISTER 3 (CSR3) 296*/ 297 298#define BSWP 0x0004 /* Byte SWaP */ 299#define ACON 0x0002 /* ALE control */ 300#define BCON 0x0001 /* Byte CONtrol */ 301 302/* 303** Initialization Block Mode Register 304*/ 305 306#define PROM 0x8000 /* Promiscuous Mode */ 307#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */ 308#define INTL 0x0040 /* Internal Loopback */ 309#define DRTY 0x0020 /* Disable Retry */ 310#define COLL 0x0010 /* Force Collision */ 311#define DTCR 0x0008 /* Disable Transmit CRC */ 312#define LOOP 0x0004 /* Loopback */ 313#define DTX 0x0002 /* Disable the Transmitter */ 314#define DRX 0x0001 /* Disable the Receiver */ 315 316/* 317** Receive Message Descriptor 1 (RMD1) bit definitions. 318*/ 319 320#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ 321#define R_ERR 0x4000 /* Error Summary */ 322#define R_FRAM 0x2000 /* Framing Error */ 323#define R_OFLO 0x1000 /* Overflow Error */ 324#define R_CRC 0x0800 /* CRC Error */ 325#define R_BUFF 0x0400 /* Buffer Error */ 326#define R_STP 0x0200 /* Start of Packet */ 327#define R_ENP 0x0100 /* End of Packet */ 328 329/* 330** Transmit Message Descriptor 1 (TMD1) bit definitions. 331*/ 332 333#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ 334#define T_ERR 0x4000 /* Error Summary */ 335#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */ 336#define T_MORE 0x1000 /* >1 retry to transmit packet */ 337#define T_ONE 0x0800 /* 1 try needed to transmit the packet */ 338#define T_DEF 0x0400 /* Deferred */ 339#define T_STP 0x02000000 /* Start of Packet */ 340#define T_ENP 0x01000000 /* End of Packet */ 341#define T_FLAGS 0xff000000 /* TX Flags Field */ 342 343/* 344** Transmit Message Descriptor 3 (TMD3) bit definitions. 345*/ 346 347#define TMD3_BUFF 0x8000 /* BUFFer error */ 348#define TMD3_UFLO 0x4000 /* UnderFLOw error */ 349#define TMD3_RES 0x2000 /* REServed */ 350#define TMD3_LCOL 0x1000 /* Late COLlision */ 351#define TMD3_LCAR 0x0800 /* Loss of CARrier */ 352#define TMD3_RTRY 0x0400 /* ReTRY error */ 353 354/* 355** Ethernet PROM defines 356*/ 357#define PROBE_LENGTH 32 358 359/* 360** Set the number of Tx and Rx buffers. Ensure that the memory requested 361** here is <= to the amount of shared memory set up by the board switches. 362** The number of descriptors MUST BE A POWER OF 2. 363** 364** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ) 365*/ 366#define NUM_RX_DESC 2 /* Number of RX descriptors */ 367#define NUM_TX_DESC 2 /* Number of TX descriptors */ 368#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */ 369#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */ 370 371/* 372** ISA Bus defines 373*/ 374#define DEPCA_IO_PORTS {0x300, 0x200, 0} 375 376#ifndef DEPCA_MODEL 377#define DEPCA_MODEL DEPCA 378#endif 379 380static enum { 381 DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown 382} adapter = DEPCA_MODEL; 383 384/* 385** Name <-> Adapter mapping 386*/ 387 388static char *adapter_name[] = { 389 "DEPCA", 390 "DE100","DE101", 391 "DE200","DE201","DE202", 392 "DE210","DE212", 393 "DE422", 394 "" 395}; 396 397#ifndef DEPCA_RAM_BASE 398#define DEPCA_RAM_BASE 0xd0000 399#endif 400 401/* 402** Memory Alignment. Each descriptor is 4 longwords long. To force a 403** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and 404** DESC_ALIGN. ALIGN aligns the start address of the private memory area 405** and hence the RX descriptor ring's first entry. 406*/ 407#define ALIGN4 ((u32)4 - 1) /* 1 longword align */ 408#define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */ 409#define ALIGN ALIGN8 /* Keep the LANCE happy... */ 410 411typedef long s32; 412typedef unsigned long u32; 413typedef short s16; 414typedef unsigned short u16; 415typedef char s8; 416typedef unsigned char u8; 417 418/* 419** The DEPCA Rx and Tx ring descriptors. 420*/ 421struct depca_rx_desc { 422 volatile s32 base; 423 s16 buf_length; /* This length is negative 2's complement! */ 424 s16 msg_length; /* This length is "normal". */ 425}; 426 427struct depca_tx_desc { 428 volatile s32 base; 429 s16 length; /* This length is negative 2's complement! */ 430 s16 misc; /* Errors and TDR info */ 431}; 432 433#define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM 434 to LANCE memory address space */ 435 436/* 437** The Lance initialization block, described in databook, in common memory. 438*/ 439struct depca_init { 440 u16 mode; /* Mode register */ 441 u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */ 442 u8 mcast_table[8]; /* Multicast Hash Table. */ 443 u32 rx_ring; /* Rx ring base pointer & ring length */ 444 u32 tx_ring; /* Tx ring base pointer & ring length */ 445}; 446 447struct depca_private { 448 struct depca_rx_desc *rx_ring; 449 struct depca_tx_desc *tx_ring; 450 struct depca_init init_block; /* Shadow init block */ 451 char *rx_memcpy[NUM_RX_DESC]; 452 char *tx_memcpy[NUM_TX_DESC]; 453 u32 bus_offset; /* ISA bus address offset */ 454 u32 sh_mem; /* address of shared mem */ 455 u32 dma_buffs; /* Rx & Tx buffer start */ 456 int rx_cur, tx_cur; /* Next free ring entry */ 457 int txRingMask, rxRingMask; 458 s32 rx_rlen, tx_rlen; 459 /* log2([rt]xRingMask+1) for the descriptors */ 460}; 461 462static Address mem_start = DEPCA_RAM_BASE; 463static Address mem_len, offset; 464static unsigned short ioaddr = 0; 465static struct depca_private lp; 466 467/* 468** Miscellaneous defines... 469*/ 470#define STOP_DEPCA \ 471 outw(CSR0, DEPCA_ADDR);\ 472 outw(STOP, DEPCA_DATA) 473 474/* Initialize the lance Rx and Tx descriptor rings. */ 475static void depca_init_ring(struct nic *nic) 476{ 477 int i; 478 u32 p; 479 480 lp.rx_cur = lp.tx_cur = 0; 481 /* Initialize the base addresses and length of each buffer in the ring */ 482 for (i = 0; i <= lp.rxRingMask; i++) { 483 writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base); 484 writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length); 485 lp.rx_memcpy[i] = (char *) (p + lp.bus_offset); 486 } 487 for (i = 0; i <= lp.txRingMask; i++) { 488 writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base); 489 lp.tx_memcpy[i] = (char *) (p + lp.bus_offset); 490 } 491 492 /* Set up the initialization block */ 493 lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen; 494 lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen; 495 for (i = 0; i < ETH_ALEN; i++) 496 lp.init_block.phys_addr[i] = nic->node_addr[i]; 497 lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */ 498 memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table)); 499} 500 501static void LoadCSRs(void) 502{ 503 outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */ 504 outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA); 505 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */ 506 outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA); 507 outw(CSR3, DEPCA_ADDR); /* ALE control */ 508 outw(ACON, DEPCA_DATA); 509 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */ 510} 511 512static int InitRestartDepca(void) 513{ 514 int i; 515 516 /* Copy the shadow init_block to shared memory */ 517 memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init)); 518 outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */ 519 outw(INIT, DEPCA_DATA); /* initialise DEPCA */ 520 521 for (i = 0; i < 100 && !(inw(DEPCA_DATA) & IDON); i++) 522 ; 523 if (i < 100) { 524 /* clear IDON by writing a 1, and start LANCE */ 525 outw(IDON | STRT, DEPCA_DATA); 526 } else { 527 printf("DEPCA not initialised\n"); 528 return (1); 529 } 530 return (0); 531} 532 533/************************************************************************** 534RESET - Reset adapter 535***************************************************************************/ 536static void depca_reset(struct nic *nic) 537{ 538 s16 nicsr; 539 int i, j; 540 541 STOP_DEPCA; 542 nicsr = inb(DEPCA_NICSR); 543 nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM); 544 outb(nicsr, DEPCA_NICSR); 545 if (inw(DEPCA_DATA) != STOP) 546 { 547 printf("depca: Cannot stop NIC\n"); 548 return; 549 } 550 551 /* Initialisation block */ 552 lp.sh_mem = mem_start; 553 mem_start += sizeof(struct depca_init); 554 /* Tx & Rx descriptors (aligned to a quadword boundary) */ 555 mem_start = (mem_start + ALIGN) & ~ALIGN; 556 lp.rx_ring = (struct depca_rx_desc *) mem_start; 557 mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC); 558 lp.tx_ring = (struct depca_tx_desc *) mem_start; 559 mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC); 560 561 lp.bus_offset = mem_start & 0x00ff0000; 562 /* LANCE re-mapped start address */ 563 lp.dma_buffs = mem_start & LA_MASK; 564 565 /* Finish initialising the ring information. */ 566 lp.rxRingMask = NUM_RX_DESC - 1; 567 lp.txRingMask = NUM_TX_DESC - 1; 568 569 /* Calculate Tx/Rx RLEN size for the descriptors. */ 570 for (i = 0, j = lp.rxRingMask; j > 0; i++) { 571 j >>= 1; 572 } 573 lp.rx_rlen = (s32) (i << 29); 574 for (i = 0, j = lp.txRingMask; j > 0; i++) { 575 j >>= 1; 576 } 577 lp.tx_rlen = (s32) (i << 29); 578 579 /* Load the initialisation block */ 580 depca_init_ring(nic); 581 LoadCSRs(); 582 InitRestartDepca(); 583} 584 585/************************************************************************** 586POLL - Wait for a frame 587***************************************************************************/ 588static int depca_poll(struct nic *nic) 589{ 590 int entry; 591 u32 status; 592 593 entry = lp.rx_cur; 594 if ((status = readl(&lp.rx_ring[entry].base) & R_OWN)) 595 return (0); 596 memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length); 597 lp.rx_ring[entry].base |= R_OWN; 598 lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask; 599 return (1); 600} 601 602/************************************************************************** 603TRANSMIT - Transmit a frame 604***************************************************************************/ 605static void depca_transmit( 606 struct nic *nic, 607 const char *d, /* Destination */ 608 unsigned int t, /* Type */ 609 unsigned int s, /* size */ 610 const char *p) /* Packet */ 611{ 612 int entry, len; 613 char *mem; 614 615 /* send the packet to destination */ 616 /* 617 ** Caution: the right order is important here... dont 618 ** setup the ownership rights until all the other 619 ** information is in place 620 */ 621 mem = lp.tx_memcpy[entry = lp.tx_cur]; 622 memcpy_toio(mem, d, ETH_ALEN); 623 memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN); 624 mem[ETH_ALEN * 2] = t >> 8; 625 mem[ETH_ALEN * 2 + 1] = t; 626 memcpy_toio(mem + ETH_HLEN, p, s); 627 s += ETH_HLEN; 628 len = (s < ETH_ZLEN ? ETH_ZLEN : s); 629 /* clean out flags */ 630 writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base); 631 /* clears other error flags */ 632 writew(0x0000, &lp.tx_ring[entry].misc); 633 /* packet length in buffer */ 634 writew(-len, &lp.tx_ring[entry].length); 635 /* start and end of packet, ownership */ 636 writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base); 637 /* update current pointers */ 638 lp.tx_cur = (++lp.tx_cur) & lp.txRingMask; 639} 640 641/************************************************************************** 642DISABLE - Turn off ethernet interface 643***************************************************************************/ 644static void depca_disable(struct nic *nic) 645{ 646 STOP_DEPCA; 647} 648 649/* 650** Look for a special sequence in the Ethernet station address PROM that 651** is common across all DEPCA products. Note that the original DEPCA needs 652** its ROM address counter to be initialized and enabled. Only enable 653** if the first address octet is a 0x08 - this minimises the chances of 654** messing around with some other hardware, but it assumes that this DEPCA 655** card initialized itself correctly. 656** 657** Search the Ethernet address ROM for the signature. Since the ROM address 658** counter can start at an arbitrary point, the search must include the entire 659** probe sequence length plus the (length_of_the_signature - 1). 660** Stop the search IMMEDIATELY after the signature is found so that the 661** PROM address counter is correctly positioned at the start of the 662** ethernet address for later read out. 663*/ 664static int depca_probe1(struct nic *nic) 665{ 666 u8 data, nicsr; 667 /* This is only correct for little endian machines, but then 668 Etherboot doesn't work on anything but a PC */ 669 u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA }; 670 int i, j; 671 long sum, chksum; 672 673 data = inb(DEPCA_PROM); /* clear counter on DEPCA */ 674 data = inb(DEPCA_PROM); /* read data */ 675 if (data == 0x8) { 676 nicsr = inb(DEPCA_NICSR); 677 nicsr |= AAC; 678 outb(nicsr, DEPCA_NICSR); 679 } 680 for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) { 681 data = inb(DEPCA_PROM); 682 if (data == sig[j]) /* track signature */ 683 ++j; 684 else 685 j = (data == sig[0]) ? 1 : 0; 686 } 687 if (j != sizeof(sig)) 688 return (0); 689 /* put the card in its initial state */ 690 STOP_DEPCA; 691 nicsr = ((inb(DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM); 692 outb(nicsr, DEPCA_NICSR); 693 if (inw(DEPCA_DATA) != STOP) 694 return (0); 695 memcpy((char *)mem_start, sig, sizeof(sig)); 696 if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0) 697 return (0); 698 for (i = 0, j = 0, sum = 0; j < 3; j++) { 699 sum <<= 1; 700 if (sum > 0xFFFF) 701 sum -= 0xFFFF; 702 sum += (u8)(nic->node_addr[i++] = inb(DEPCA_PROM)); 703 sum += (u16)((nic->node_addr[i++] = inb(DEPCA_PROM)) << 8); 704 if (sum > 0xFFFF) 705 sum -= 0xFFFF; 706 } 707 if (sum == 0xFFFF) 708 sum = 0; 709 chksum = (u8)inb(DEPCA_PROM); 710 chksum |= (u16)(inb(DEPCA_PROM) << 8); 711 mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10); 712 offset = 0; 713 if (nicsr & BUF) { 714 offset = 0x8000; 715 nicsr &= ~BS; 716 mem_len -= (32 << 10); 717 } 718 if (adapter != DEPCA) /* enable shadow RAM */ 719 outb(nicsr |= SHE, DEPCA_NICSR); 720 printf("%s base %#hX, memory [%#hX-%#hX], addr %!", 721 adapter_name[adapter], ioaddr, mem_start, mem_start + mem_len, 722 nic->node_addr); 723 if (sum != chksum) 724 printf(" (bad checksum)"); 725 putchar('\n'); 726 return (1); 727} 728 729/************************************************************************** 730PROBE - Look for an adapter, this routine's visible to the outside 731***************************************************************************/ 732struct nic *depca_probe(struct nic *nic, unsigned short *probe_addrs) 733{ 734 static unsigned short base[] = DEPCA_IO_PORTS; 735 int i; 736 737 if (probe_addrs == 0 || probe_addrs[0] == 0) 738 probe_addrs = base; /* Use defaults */ 739 for (i = 0; (ioaddr = base[i]) != 0; ++i) { 740 if (depca_probe1(nic)) 741 break; 742 } 743 if (ioaddr == 0) 744 return (0); 745 depca_reset(nic); 746 /* point to NIC specific routines */ 747 nic->reset = depca_reset; 748 nic->poll = depca_poll; 749 nic->transmit = depca_transmit; 750 nic->disable = depca_disable; 751 return (nic); 752} 753