/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.h | 160 SDValue JoinIntegers(SDValue Lo, SDValue Hi); 172 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 174 SDValue &Lo, SDValue &Hi); 298 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi. 300 /// method returns the two i32's, with Lo being equal to the lower 32 bits of 302 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 303 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi); 308 SDValue &Lo, SDValue &Hi); 309 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); 310 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValu 692 GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument 725 GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part 30 // These routines assume that the Lo/Hi part is stored first in memory on 31 // little/big-endian machines, followed by the Hi/Lo part. This means that 32 // they cannot be used as is on vectors, for which Lo is always stored first. 34 SDValue &Lo, SDValue &Hi) { 36 GetExpandedOp(Op, Lo, Hi); 39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { argument 53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); local 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 33 ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 148 ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 155 ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 167 ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 211 ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, SDValue &Hi) argument 253 ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 324 SDValue Lo, Hi; local 342 SDValue Lo, Hi; local 366 SDValue Lo, Hi; local 413 SDValue Lo, Hi; local 443 SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 449 SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 473 SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 486 SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeFloatTypes.cpp | 822 SDValue Lo, Hi; local 823 Lo = Hi = SDValue(); 837 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 838 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 839 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 841 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 842 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 843 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 844 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 845 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, H 880 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); local 883 ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 895 ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 909 ExpandFloatRes_FADD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 918 ExpandFloatRes_FCEIL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 927 ExpandFloatRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 938 ExpandFloatRes_FCOS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 947 ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 960 ExpandFloatRes_FEXP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 969 ExpandFloatRes_FEXP2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 978 ExpandFloatRes_FFLOOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 987 ExpandFloatRes_FLOG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 996 ExpandFloatRes_FLOG2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1005 ExpandFloatRes_FLOG10(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1014 ExpandFloatRes_FMA(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1027 ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1040 ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1051 ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1059 ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1066 ExpandFloatRes_FPOW(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1075 ExpandFloatRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1084 ExpandFloatRes_FRINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1093 ExpandFloatRes_FSIN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1102 ExpandFloatRes_FSQRT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1111 ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1124 ExpandFloatRes_FTRUNC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1133 ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1165 ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1344 SDValue Lo, Hi; local 1456 SDValue Lo, Hi; local [all...] |
H A D | LegalizeIntegerTypes.cpp | 237 SDValue Lo, Hi; local 238 GetSplitVector(N->getOperand(0), Lo, Hi); 239 Lo = BitConvertToInteger(Lo); 243 std::swap(Lo, Hi); 248 JoinIntegers(Lo, Hi)); 886 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); local 888 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 893 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 1072 SDValue Lo, H local 1110 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; local 1166 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); local 1257 ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) argument 1349 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1437 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1511 ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1573 ExpandIntRes_ADDSUBC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1599 ExpandIntRes_ADDSUBE(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1619 ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 1625 ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1648 ExpandIntRes_AssertSext(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1669 ExpandIntRes_AssertZext(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1689 ExpandIntRes_BSWAP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1697 ExpandIntRes_Constant(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1706 ExpandIntRes_CTLZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1725 ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1736 ExpandIntRes_CTTZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1755 ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1762 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); local 1765 ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1772 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); local 1775 ExpandIntRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi) argument 1890 ExpandIntRes_Logical(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1900 ExpandIntRes_MUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1987 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); local 1990 ExpandIntRes_SADDSUBO(SDNode *Node, SDValue &Lo, SDValue &Hi) argument 2032 ExpandIntRes_SDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2049 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); local 2052 ExpandIntRes_Shift(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2133 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); local 2141 ExpandIntRes_SIGN_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2173 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2199 ExpandIntRes_SREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2216 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); local 2219 ExpandIntRes_TRUNCATE(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2230 ExpandIntRes_UADDSUBO(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2253 ExpandIntRes_XMULO(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2336 ExpandIntRes_UDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2353 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); local 2356 ExpandIntRes_UREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2373 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); local 2376 ExpandIntRes_ZERO_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2404 ExpandIntRes_ATOMIC_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2640 SDValue Lo, Hi; local 2649 SDValue Lo, Hi; local 2678 SDValue Lo, Hi; local 2802 SDValue Lo, Hi; local [all...] |
H A D | LegalizeVectorTypes.cpp | 459 SDValue Lo, Hi; local 475 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 477 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 478 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 479 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 480 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 481 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 482 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 483 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 484 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, H 490 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); local 496 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); local 561 SetSplitVector(SDValue(N, ResNo), Lo, Hi); local 564 SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 576 SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 592 SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) argument 640 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); local 648 SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 661 SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 682 SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 697 SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument 705 SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 720 SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 770 SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 779 SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi) argument 820 SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 848 SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 890 SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, SDValue &Hi) argument 1070 SDValue Lo, Hi; local 1088 SDValue Lo, Hi; local 1105 SDValue Lo, Hi; local 1167 SDValue Lo, Hi; local 1245 SDValue Lo, Hi; local [all...] |
H A D | LegalizeTypes.cpp | 765 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo, argument 771 Lo = Entry.first; 775 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo, argument 777 assert(Lo.getValueType() == 779 Hi.getValueType() == Lo.getValueType() && 781 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant. 782 AnalyzeNewValue(Lo); 788 Entry.first = Lo; 792 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo, argument 798 Lo 802 SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi) argument 819 GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi) argument 829 SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi) argument 973 GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi) argument 1001 JoinIntegers(SDValue Lo, SDValue Hi) argument 1114 SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) argument 1128 SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeDAG.cpp | 396 SDValue Lo = Val; local 401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 528 SDValue Lo, Hi; local 530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); local 678 if (TLI.isBigEndian()) std::swap(Lo, H [all...] |
/external/llvm/include/llvm/Support/ |
H A D | SwapByteOrder.h | 34 uint16_t Lo = value >> 8; 35 return Hi | Lo; 66 uint32_t Lo = SwapByteOrder_32(uint32_t(value >> 32)); 67 return (Hi << 32) | Lo;
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H A D | GCOV.h | 138 uint64_t Lo = readInt(); local 140 uint64_t Result = Lo | (Hi << 32);
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H A D | MathExtras.h | 227 uint32_t Lo = Lo_32(Value); local 229 Count = CountLeadingZeros_32(Lo)+32;
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/external/llvm/include/llvm/ |
H A D | MDBuilder.h | 80 /// \brief Return metadata describing the range [Lo, Hi). 81 MDNode *createRange(const APInt &Lo, const APInt &Hi) { argument 82 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!"); 84 if (Hi == Lo) 87 // Return the range [Lo, Hi). 88 Type *Ty = IntegerType::get(Context, Lo.getBitWidth()); 89 Value *Range[2] = { ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi) };
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/external/llvm/lib/Target/Mips/ |
H A D | MipsJITInfo.cpp | 179 int Lo = (int)(NewVal & 0xffff); local 182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo; 219 int Lo = (int)(EmittedAddr & 0xffff); local 226 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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H A D | MipsISelLowering.cpp | 62 case MipsISD::Lo: return "MipsISD::Lo"; 330 // multHi/Lo: product of multiplication 331 // Lo0: initial value of Lo register 403 // multHi/Lo: product of multiplication 404 // Lo0: initial value of Lo register 747 SDValue Lo = Add.getOperand(1); 749 if ((Lo.getOpcode() != MipsISD::Lo) || 750 (Lo 1590 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); local 1611 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); local 1626 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); local 1639 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); local 1693 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); local 1716 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); local 1749 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); local 1778 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); local 1792 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); local 2026 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local 2057 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local 2695 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, local 2794 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); local [all...] |
H A D | MipsISelDAGToDAG.cpp | 340 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || 369 SDNode *Lo = 0, *Hi = 0; local 375 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, 377 InFlag = SDValue(Lo, 1); 383 return std::make_pair(Lo, Hi);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 124 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 125 Addr.getOperand(1).getOpcode() == SPISD::Lo)
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H A D | SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::SPISD::__anon8976
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H A D | SparcISelLowering.cpp | 479 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, local 487 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 494 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 510 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 826 case SPISD::Lo: return "SPISD::Lo"; 892 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); local 895 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 899 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, H 914 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); local [all...] |
/external/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 1042 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1048 /// \param Lo - The classification for the parts of the type 1054 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1059 /// \param Lo - The classification for the parts of the type 1070 /// be passed in Memory then at least the classification of \arg Lo 1073 /// The \arg Lo class will be NoClass iff the argument is ignored. 1075 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1077 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const; 1232 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, argument 1256 Lo 1305 classify(QualType Ty, uint64_t OffsetBase, Class &Lo, Class &Hi) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | AsmPrinter.h | 340 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size 341 /// in bytes of the directive is specified by Size and Hi/Lo specify the 343 void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, 346 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo" 347 /// where the size in bytes of the directive is specified by Size and Hi/Lo 350 const MCSymbol *Lo, unsigned Size) const;
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/external/skia/src/core/ |
H A D | SkMath.cpp | 182 uint32_t Lo = C + (B << 16); local 183 uint32_t Hi = A + (B >>16) + (Lo < C); 187 int32_t R = (Hi << 2) + (Lo >> 30);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 573 SDValue Lo(Hi.getNode(), 1); 574 SDValue Ops[] = { Lo, Hi }; 590 SDValue Lo(Hi.getNode(), 1); 591 SDValue Ops[] = { Lo, Hi }; 687 SDValue Lo(Hi.getNode(), 1); 688 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 695 SDValue Lo(Hi.getNode(), 1); 696 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 706 SDValue Lo(Hi.getNode(), 1); 711 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, H 1438 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); local [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 32 Lo, ///< Low address component (lower 16) enumerator in enum:llvm::SPUISD::NodeType
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 42 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::HexagonISD::__anon8900
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DIE.h | 304 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) argument 305 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 114 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo || 127 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo || 789 unsigned Lo = Imm & 0xFFFF; local 794 // Just the Lo bits. 795 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 796 } else if (Lo) { 800 // And Lo bits. 802 SDValue(Result, 0), getI32Imm(Lo)); 824 if ((Lo = Remainder & 0xFFFF)) { 826 SDValue(Result, 0), getI32Imm(Lo)); [all...] |