| /external/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 74 RCInfo &RCI = RegClass[RC->getID()]; local
79 if (!RCI.Order)
80 RCI.Order.reset(new unsigned[NumRegs]);
97 RCI.Order[N++] = PhysReg;
99 RCI.NumRegs = N + CSRAlias.size();
100 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
103 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
106 if (StressRA && RCI.NumRegs > StressRA)
107 RCI.NumRegs = StressRA;
111 if (Super != RC && getNumAllocatableRegs(Super) > RCI
[all...] |
| H A D | AllocationOrder.cpp | 28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
55 if (!RCI.isReserved(Order[i]))
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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| H A D | AllocationOrder.h | 29 const RegisterClassInfo &RCI; member in class:llvm::AllocationOrder
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| H A D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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| H A D | RegisterPressure.cpp | 174 RCI = rci;
340 const RegisterClassInfo *RCI) {
348 else if (RCI->isAllocatable(MO.getReg()))
454 collectOperands(CurrPos, PhysRegOpers, VirtRegOpers, TRI, RCI);
527 collectOperands(CurrPos, PhysRegOpers, VirtRegOpers, TRI, RCI);
669 collectOperands(MI, PhysRegOpers, VirtRegOpers, TRI, RCI);
755 collectOperands(MI, PhysRegOpers, VirtRegOpers, TRI, RCI);
336 collectOperands(const MachineInstr *MI, PhysRegOperands &PhysRegOpers, VirtRegOperands &VirtRegOpers, const TargetRegisterInfo *TRI, const RegisterClassInfo *RCI) argument
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| H A D | PostRASchedulerList.cpp | 198 AliasAnalysis *AA, const RegisterClassInfo &RCI,
214 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
216 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
196 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
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| H A D | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : argument
35 RegClassInfo(RCI),
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| H A D | AggressiveAntiDepBreaker.cpp | 118 const RegisterClassInfo &RCI,
124 RegClassInfo(RCI),
117 AggressiveAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector& CriticalPathRCs) argument
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 65 const RCInfo &RCI = RegClass[RC->getID()]; local
66 if (Tag != RCI.Tag)
68 return RCI;
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| H A D | RegisterPressure.h | 138 const RegisterClassInfo *RCI; member in class:llvm::RegPressureTracker
165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}
168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
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| /external/llvm/lib/Target/ |
| H A D | TargetRegisterInfo.cpp | 178 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
179 if (RCI.getSubReg() == Idx)
182 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 717 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
718 SuperRegRC.setBitsInMask(RCI.getMask());
2830 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2831 E = RI->regclass_end(); RCI != E; ++RCI) {
2832 const TargetRegisterClass *RC = *RCI;
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