| /external/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| H A D | ARMInstrInfo.h | 28 explicit ARMInstrInfo(const ARMSubtarget &STI);
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| H A D | ARMHazardRecognizer.h | 33 const ARMSubtarget &STI; member in class:llvm::ARMHazardRecognizer
45 TRI(tri), STI(sti), LastMI(0) {}
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| H A D | Thumb2RegisterInfo.h | 28 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| H A D | ARMInstrInfo.cpp | 27 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) argument
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
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| H A D | ARMFrameLowering.h | 26 const ARMSubtarget &STI; member in class:llvm::ARMFrameLowering
31 STI(sti) {
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| H A D | Thumb1InstrInfo.cpp | 24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) argument
25 : ARMBaseInstrInfo(STI), RI(*this, STI) {
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| H A D | MBlazeDisassembler.h | 33 MBlazeDisassembler(const MCSubtargetInfo &STI) : argument
34 MCDisassembler(STI) {
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| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI; member in class:llvm::MBlazeFrameLowering
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.h | 22 explicit Mips16FrameLowering(const MipsSubtarget &STI) argument
23 : MipsFrameLowering(STI) {}
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| H A D | MipsFrameLowering.h | 26 const MipsSubtarget &STI; member in class:llvm::MipsFrameLowering
31 sti.hasMips64() ? 16 : 8), STI(sti) {}
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| H A D | MipsSEFrameLowering.h | 23 explicit MipsSEFrameLowering(const MipsSubtarget &STI) argument
24 : MipsFrameLowering(STI) {}
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| H A D | MipsSEFrameLowering.cpp | 40 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
41 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
42 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
43 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
93 if (!STI.isLittle())
129 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
130 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
131 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
132 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
200 unsigned FP = STI
[all...] |
| /external/llvm/include/llvm/MC/ |
| H A D | MCDisassembler.h | 58 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0), argument
60 STI(STI), CommentStream(0) {}
110 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 21 const HexagonSubtarget &STI; member in class:llvm::HexagonFrameLowering
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.h | 26 const MSP430Subtarget &STI; member in class:llvm::MSP430FrameLowering
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 39 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, argument
41 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
61 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, argument
63 MipsDisassemblerBase(STI, Info, bigEndian) {}
80 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, argument
82 MipsDisassemblerBase(STI, Info, bigEndian) {}
193 const MCSubtargetInfo &STI) {
194 return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
199 const MCSubtargetInfo &STI) {
200 return new MipsDisassembler(STI,
191 createMipsDisassembler( const Target &T, const MCSubtargetInfo &STI) argument
197 createMipselDisassembler( const Target &T, const MCSubtargetInfo &STI) argument
203 createMips64Disassembler( const Target &T, const MCSubtargetInfo &STI) argument
209 createMips64elDisassembler( const Target &T, const MCSubtargetInfo &STI) argument
[all...] |
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| H A D | MBlazeMCTargetDesc.h | 35 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.h | 36 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.h | 26 XCoreFrameLowering(const XCoreSubtarget &STI);
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| /external/llvm/tools/llvm-mc/ |
| H A D | Disassembler.h | 33 MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCTargetDesc.h | 38 const MCSubtargetInfo &STI,
42 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.h | 27 const X86Subtarget &STI; member in class:llvm::X86FrameLowering
33 TM(tm), STI(sti) {
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| /external/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 72 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(TripleName, CPU, local
74 assert(STI && "Unable to create subtarget info!");
81 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
88 *MAI, *MII, *MRI, *STI);
94 STI, MII, Ctx, DisAsm, IP);
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| /external/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 158 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
166 Context->getRegisterInfo(), STI);
172 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
173 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI,
193 STI, *Context);
266 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
268 STI, *Ctx);
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