/external/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 31 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) 39 if (MF->getTarget().getRegisterInfo() != TRI) { 40 TRI = MF->getTarget().getRegisterInfo(); 41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 46 const uint16_t *CSR = TRI->getCalleeSavedRegs(MF); 51 CSRNum.resize(TRI->getNumRegs(), 0); 53 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 60 BitVector RR = TRI->getReservedRegs(*MF); 110 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) 117 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); [all...] |
H A D | LiveRegMatrix.cpp | 50 TRI = MF.getTarget().getRegisterInfo(); 55 unsigned NumRegUnits = TRI->getNumRegUnits(); 73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); 88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); [all...] |
H A D | RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | RegisterScavenging.cpp | 40 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 45 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 77 TRI = TM.getRegisterInfo(); 80 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 90 NumPhysRegs = TRI->getNumRegs(); 96 ReservedRegs = TRI->getReservedRegs(MF); 100 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF); 114 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 195 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 212 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MR [all...] |
H A D | MachineCopyPropagation.cpp | 34 const TargetRegisterInfo *TRI; member in class:__anon8677::MachineCopyPropagation 65 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 74 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) 111 const TargetRegisterInfo *TRI) { 115 if (TRI->isSubRegister(SrcSrc, Def)) { 117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); 120 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); 151 isNopCopy(CopyMI, Def, Src, TRI)) { 169 I->clearRegisterKills(Def, TRI); 179 for (MCRegAliasIterator AI(Src, TRI, tru 110 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument [all...] |
H A D | RegisterPressure.cpp | 30 const TargetRegisterInfo *TRI) { 31 unsigned Weight = TRI->getRegClassWeight(RC).RegWeight; 32 for (const int *PSet = TRI->getRegClassPressureSets(RC); 45 const TargetRegisterInfo *TRI) { 46 unsigned Weight = TRI->getRegClassWeight(RC).RegWeight; 47 for (const int *PSet = TRI->getRegClassPressureSets(RC); 56 const TargetRegisterInfo *TRI) { 57 increaseSetPressure(MaxSetPressure, MaxSetPressure, RC, TRI); 62 const TargetRegisterInfo *TRI) { 63 decreaseSetPressure(MaxSetPressure, RC, TRI); 27 increaseSetPressure(std::vector<unsigned> &CurrSetPressure, std::vector<unsigned> &MaxSetPressure, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) argument 43 decreaseSetPressure(std::vector<unsigned> &CurrSetPressure, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) argument 55 increase(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) argument 61 decrease(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) argument 67 dump(const TargetRegisterInfo *TRI) argument 273 hasRegAlias(unsigned Reg, SparseSet<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 285 findRegAlias(unsigned Reg, SmallVectorImpl<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 299 findReg(unsigned Reg, bool isVReg, SmallVectorImpl<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 315 collect(const MachineOperand &MO, const TargetRegisterInfo *TRI) argument 336 collectOperands(const MachineInstr *MI, PhysRegOperands &PhysRegOpers, VirtRegOperands &VirtRegOpers, const TargetRegisterInfo *TRI, const RegisterClassInfo *RCI) argument 585 computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec, ArrayRef<unsigned> NewPressureVec, RegPressureDelta &Delta, const TargetRegisterInfo *TRI) argument [all...] |
H A D | MachineRegisterInfo.cpp | 20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) argument 21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 UsedPhysRegMask.resize(TRI.getNumRegs()); 28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 271 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument [all...] |
H A D | RegAllocBase.h | 61 const TargetRegisterInfo *TRI; member in class:llvm::RegAllocBase 68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
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H A D | AllocationOrder.cpp | 42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); local 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 60 Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
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H A D | InterferenceCache.h | 25 const TargetRegisterInfo *TRI; member in class:llvm::InterferenceCache 112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI); 120 const TargetRegisterInfo *TRI, 150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
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H A D | AggressiveAntiDepBreaker.cpp | 123 TRI(MF.getTarget().getRegisterInfo()), 129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); 139 dbgs() << " " << TRI->getName(r)); 149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 160 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 176 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 189 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 192 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 229 dbgs() << " " << TRI [all...] |
H A D | VirtRegMap.cpp | 54 TRI = mf.getTarget().getRegisterInfo(); 87 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF); 113 OS << '[' << PrintReg(Reg, TRI) << " -> " 114 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " 122 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] 148 const TargetRegisterInfo *TRI; member in class:__anon8745::VirtRegRewriter 193 TRI = TM->getRegisterInfo(); 257 BitVector Reserved = TRI->getReservedRegs(*MF); 307 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); 319 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, tru [all...] |
H A D | CriticalAntiDepBreaker.cpp | 34 TRI(MF.getTarget().getRegisterInfo()), 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), 37 KillIndices(TRI->getNumRegs(), 0), 38 DefIndices(TRI->getNumRegs(), 0), 39 KeepRegs(TRI->getNumRegs(), false) {} 46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 81 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 94 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 96 for (MCRegAliasIterator AI(*I, TRI, tru [all...] |
/external/llvm/lib/Target/ |
H A D | TargetInstrInfo.cpp | 35 const TargetRegisterInfo *TRI, 42 return TRI->getPointerRegClass(MF, RegClass); 49 return TRI->getRegClass(RegClass); 34 getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const argument
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H A D | TargetRegisterInfo.cpp | 37 else if (TRI && Reg < TRI->getNumRegs()) 38 OS << '%' << TRI->getName(Reg); 42 if (TRI) 43 OS << ':' << TRI->getSubRegIndexName(SubIdx); 50 // Generic printout when TRI is missing. 51 if (!TRI) { 57 if (Unit >= TRI->getNumRegUnits()) { 63 MCRegUnitRootIterator Roots(Unit, TRI); 65 OS << TRI 147 firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.h | 41 const TargetRegisterInfo *TRI) const; 45 const TargetRegisterInfo *TRI) const;
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H A D | ARMHazardRecognizer.h | 32 const ARMBaseRegisterInfo &TRI; member in class:llvm::ARMHazardRecognizer 45 TRI(tri), STI(sti), LastMI(0) {}
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H A D | Thumb1InstrInfo.h | 50 const TargetRegisterInfo *TRI) const; 56 const TargetRegisterInfo *TRI) const;
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H A D | Thumb2InstrInfo.h | 52 const TargetRegisterInfo *TRI) const; 58 const TargetRegisterInfo *TRI) const;
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H A D | ARMHazardRecognizer.cpp | 20 const TargetRegisterInfo &TRI) { 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 61 hasRAWHazard(DefMI, MI, TRI))) { 19 hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI) argument
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 36 const TargetRegisterInfo *TRI) const; 40 const TargetRegisterInfo *TRI) const;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 37 const TargetRegisterInfo *TRI) const; 42 const TargetRegisterInfo *TRI) const;
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H A D | HexagonFrameLowering.cpp | 213 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument 214 MCSuperRegIterator SRI(Reg, TRI); 227 const TargetRegisterInfo *TRI) const { 248 unsigned SuperReg = uniqueSuperReg(Reg, TRI); 253 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); 254 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 261 CSI[i+1].getFrameIdx(), SuperRegClass, TRI); 267 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 269 TRI); 281 const TargetRegisterInfo *TRI) cons [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 41 const TargetRegisterInfo *TRI) const; 45 const TargetRegisterInfo *TRI) const;
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterPressure.h | 40 void increase(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI); 44 void decrease(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI); 46 void dump(const TargetRegisterInfo *TRI); 137 const TargetRegisterInfo *TRI; member in class:llvm::RegPressureTracker 165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {} 168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
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