/external/webkit/Tools/Scripts/webkitpy/layout_tests/layout_package/ |
H A D | printing_unittest.py | 150 rs = result_summary.ResultSummary(expectations, test_paths) 151 return test_paths, rs, expectations 340 paths, rs, exp = self.get_result_summary(tests, expectations) 342 printer.print_progress(rs, False, paths) 346 printer.print_progress(rs, True, paths) 353 printer.print_progress(rs, False, paths) 359 printer.print_progress(rs, True, paths) 372 paths, rs, exp = self.get_result_summary(tests, expectations) 373 printer.print_progress(rs, False, paths) 380 paths, rs, ex [all...] |
/external/webkit/Source/JavaScriptCore/assembler/ |
H A D | MIPSAssembler.h | 242 void move(RegisterID rd, RegisterID rs) argument 245 emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS)); 268 void addiu(RegisterID rt, RegisterID rs, int imm) argument 270 emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) 274 void addu(RegisterID rd, RegisterID rs, RegisterID rt) argument 276 emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS) 280 void subu(RegisterID rd, RegisterID rs, RegisterID rt) argument 282 emitInst(0x00000023 | (rd << OP_SH_RD) | (rs << OP_SH_RS) 286 void mult(RegisterID rs, RegisterID rt) argument 288 emitInst(0x00000018 | (rs << OP_SH_R 291 div(RegisterID rs, RegisterID rt) argument 306 mul(RegisterID rd, RegisterID rs, RegisterID rt) argument 317 andInsn(RegisterID rd, RegisterID rs, RegisterID rt) argument 323 andi(RegisterID rt, RegisterID rs, int imm) argument 329 nor(RegisterID rd, RegisterID rs, RegisterID rt) argument 335 orInsn(RegisterID rd, RegisterID rs, RegisterID rt) argument 341 ori(RegisterID rt, RegisterID rs, int imm) argument 347 xorInsn(RegisterID rd, RegisterID rs, RegisterID rt) argument 353 xori(RegisterID rt, RegisterID rs, int imm) argument 359 slt(RegisterID rd, RegisterID rs, RegisterID rt) argument 365 sltu(RegisterID rd, RegisterID rs, RegisterID rt) argument 371 sltiu(RegisterID rt, RegisterID rs, int imm) argument 383 sllv(RegisterID rd, RegisterID rt, int rs) argument 395 srav(RegisterID rd, RegisterID rt, RegisterID rs) argument 407 srlv(RegisterID rd, RegisterID rt, RegisterID rs) argument 413 lbu(RegisterID rt, RegisterID rs, int offset) argument 420 lw(RegisterID rt, RegisterID rs, int offset) argument 427 lwl(RegisterID rt, RegisterID rs, int offset) argument 434 lwr(RegisterID rt, RegisterID rs, int offset) argument 441 lhu(RegisterID rt, RegisterID rs, int offset) argument 448 sw(RegisterID rt, RegisterID rs, int offset) argument 454 jr(RegisterID rs) argument 459 jalr(RegisterID rs) argument 475 bgez(RegisterID rs, int imm) argument 480 bltz(RegisterID rs, int imm) argument 485 beq(RegisterID rs, RegisterID rt, int imm) argument 490 bne(RegisterID rs, RegisterID rt, int imm) argument 539 lwc1(FPRegisterID ft, RegisterID rs, int offset) argument 546 ldc1(FPRegisterID ft, RegisterID rs, int offset) argument 552 swc1(FPRegisterID ft, RegisterID rs, int offset) argument 558 sdc1(FPRegisterID ft, RegisterID rs, int offset) argument [all...] |
H A D | MacroAssemblerMIPS.h | 1701 Jump branchEqual(RegisterID rs, RegisterID rt) argument 1704 m_assembler.beq(rs, rt, 0); 1710 Jump branchNotEqual(RegisterID rs, RegisterID rt) argument 1713 m_assembler.bne(rs, rt, 0);
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/external/valgrind/main/none/tests/arm/ |
H A D | v6intARM.stdout.exp | 376 add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000 377 add r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 378 add r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 379 add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000 380 add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000 381 add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000 382 add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000 383 add r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 384 add r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 385 add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs [all...] |
H A D | v6intThumb.stdout.exp | [all...] |
H A D | v6media.stdout.exp | 9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 13 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 14 mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 16 mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 17 mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 18 mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 19 mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs [all...] |
/external/webkit/LayoutTests/storage/ |
H A D | sql-data-types.js | 34 var rs = result.rows.item(0); 36 i = "timestamp"; shouldBeSameTypeAndValue(i, testValues[i], rs[i]); 37 i = "id"; shouldBeSameTypeAndValue(i, testValues[i], rs[i]); 38 i = "real"; shouldBeSameTypeAndValue(i, testValues[i], rs[i]); 39 i = "text"; shouldBeSameTypeAndValue(i, testValues[i], rs[i]); 40 i = "blob"; shouldBeSameTypeAndValue(i, testValues[i], rs[i]);
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/external/webkit/PerformanceTests/SunSpider/tests/parse-only/ |
H A D | concat-jquery-mootools-prototype.js | 7500 var rs = obj.CallFunction('<invoke name="' + fn + '" returntype="javascript">' + __flash__argumentsToXML(arguments, 2) + '</invoke>'); 7501 return eval(rs);
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/external/v8/src/arm/ |
H A D | assembler-arm.cc | 199 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { argument 204 rs_ = rs;
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H A D | assembler-arm.h | 416 // rm <shift_op> rs 417 explicit Operand(Register rm, ShiftOp shift_op, Register rs); 436 Register rs() const { return rs_; } function in class:v8::internal::BASE_EMBEDDED
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H A D | disasm-arm.cc | 236 int rs = instr->RsValue(); local 239 PrintRegister(rs); 332 } else if (format[1] == 's') { // 'rs: Rs register 693 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 708 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
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H A D | macro-assembler-arm.cc | 374 ASSERT(src.rs().is(no_reg));
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H A D | simulator-arm.cc | 1482 int rs = instr->RsValue(); local 1483 shift_amount = get_register(rs) &0xff; 2015 int rs = instr->RsValue(); local 2016 int32_t rs_val = get_register(rs); 2023 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 2035 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 2047 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
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/external/v8/src/mips/ |
H A D | assembler-mips.cc | 371 Register rs; local 372 rs.code_ = (instr & kRsFieldMask) >> kRsShift; 373 return rs; 583 uint32_t rs = GetRs(instr); 592 rs == static_cast<uint32_t>(ToNumber(zero_reg)) && 854 Register rs, 859 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); 860 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) 867 Register rs, 872 ASSERT(rs 853 GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, uint16_t sa, SecondaryField func) argument 866 GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, uint16_t lsb, SecondaryField func) argument 922 GenInstrImmediate(Opcode opcode, Register rs, Register rt, int32_t j) argument 933 GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, int32_t j) argument 943 GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, int32_t j) argument 1070 beq(Register rs, Register rt, int16_t offset) argument 1077 bgez(Register rs, int16_t offset) argument 1084 bgezal(Register rs, int16_t offset) argument 1092 bgtz(Register rs, int16_t offset) argument 1099 blez(Register rs, int16_t offset) argument 1106 bltz(Register rs, int16_t offset) argument 1113 bltzal(Register rs, int16_t offset) argument 1121 bne(Register rs, Register rt, int16_t offset) argument 1139 jr(Register rs) argument 1161 jalr(Register rs, Register rd) argument 1169 j_or_jr(int32_t target, Register rs) argument 1182 jal_or_jalr(int32_t target, Register rs) argument 1199 addu(Register rd, Register rs, Register rt) argument 1204 addiu(Register rd, Register rs, int32_t j) argument 1209 subu(Register rd, Register rs, Register rt) argument 1214 mul(Register rd, Register rs, Register rt) argument 1219 mult(Register rs, Register rt) argument 1224 multu(Register rs, Register rt) argument 1229 div(Register rs, Register rt) argument 1234 divu(Register rs, Register rt) argument 1241 and_(Register rd, Register rs, Register rt) argument 1246 andi(Register rt, Register rs, int32_t j) argument 1252 or_(Register rd, Register rs, Register rt) argument 1257 ori(Register rt, Register rs, int32_t j) argument 1263 xor_(Register rd, Register rs, Register rt) argument 1268 xori(Register rt, Register rs, int32_t j) argument 1274 nor(Register rd, Register rs, Register rt) argument 1293 sllv(Register rd, Register rt, Register rs) argument 1303 srlv(Register rd, Register rt, Register rs) argument 1313 srav(Register rd, Register rt, Register rs) argument 1328 rotrv(Register rd, Register rt, Register rs) argument 1349 lb(Register rd, const MemOperand& rs) argument 1359 lbu(Register rd, const MemOperand& rs) argument 1369 lh(Register rd, const MemOperand& rs) argument 1379 lhu(Register rd, const MemOperand& rs) argument 1389 lw(Register rd, const MemOperand& rs) argument 1399 lwl(Register rd, const MemOperand& rs) argument 1404 lwr(Register rd, const MemOperand& rs) argument 1409 sb(Register rd, const MemOperand& rs) argument 1419 sh(Register rd, const MemOperand& rs) argument 1429 sw(Register rd, const MemOperand& rs) argument 1439 swl(Register rd, const MemOperand& rs) argument 1444 swr(Register rd, const MemOperand& rs) argument 1489 tge(Register rs, Register rt, uint16_t code) argument 1497 tgeu(Register rs, Register rt, uint16_t code) argument 1505 tlt(Register rs, Register rt, uint16_t code) argument 1513 tltu(Register rs, Register rt, uint16_t code) argument 1522 teq(Register rs, Register rt, uint16_t code) argument 1530 tne(Register rs, Register rt, uint16_t code) argument 1551 slt(Register rd, Register rs, Register rt) argument 1556 sltu(Register rd, Register rs, Register rt) argument 1561 slti(Register rt, Register rs, int32_t j) argument 1566 sltiu(Register rt, Register rs, int32_t j) argument 1572 movz(Register rd, Register rs, Register rt) argument 1577 movn(Register rd, Register rs, Register rt) argument 1582 movt(Register rd, Register rs, uint16_t cc) argument 1589 movf(Register rd, Register rs, uint16_t cc) argument 1597 clz(Register rd, Register rs) argument 1603 ins_(Register rt, Register rs, uint16_t pos, uint16_t size) argument 1611 ext_(Register rt, Register rs, uint16_t pos, uint16_t size) argument [all...] |
H A D | assembler-mips.h | 677 void beq(Register rs, Register rt, int16_t offset); 678 void beq(Register rs, Register rt, Label* L) { argument 679 beq(rs, rt, branch_offset(L, false) >> 2); 681 void bgez(Register rs, int16_t offset); 682 void bgezal(Register rs, int16_t offset); 683 void bgtz(Register rs, int16_t offset); 684 void blez(Register rs, int16_t offset); 685 void bltz(Register rs, int16_t offset); 686 void bltzal(Register rs, int16_t offset); 687 void bne(Register rs, Registe 688 bne(Register rs, Register rt, Label* L) argument [all...] |
H A D | disasm-mips.cc | 319 if (format[1] == 's') { // 'rs: Rs register. 624 Format(instr, "jr 'rs"); 627 Format(instr, "jalr 'rs"); 650 Format(instr, "sllv 'rd, 'rt, 'rs"); 654 Format(instr, "srlv 'rd, 'rt, 'rs"); 657 Format(instr, "rotrv 'rd, 'rt, 'rs"); 664 Format(instr, "srav 'rd, 'rt, 'rs"); 673 Format(instr, "mult 'rs, 'rt"); 676 Format(instr, "multu 'rs, 'rt"); 679 Format(instr, "div 'rs, 'r [all...] |
H A D | macro-assembler-mips.cc | 543 void MacroAssembler::Addu(Register rd, Register rs, const Operand& rt) { argument 545 addu(rd, rs, rt.rm()); 548 addiu(rd, rs, rt.imm32_); 551 ASSERT(!rs.is(at)); 553 addu(rd, rs, at); 559 void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) { argument 561 subu(rd, rs, rt.rm()); 564 addiu(rd, rs, -rt.imm32_); // No subiu instr, use addiu(x, y, -imm). 567 ASSERT(!rs.is(at)); 569 subu(rd, rs, a 575 Mul(Register rd, Register rs, const Operand& rt) argument 597 Mult(Register rs, const Operand& rt) argument 609 Multu(Register rs, const Operand& rt) argument 621 Div(Register rs, const Operand& rt) argument 633 Divu(Register rs, const Operand& rt) argument 645 And(Register rd, Register rs, const Operand& rt) argument 661 Or(Register rd, Register rs, const Operand& rt) argument 677 Xor(Register rd, Register rs, const Operand& rt) argument 693 Nor(Register rd, Register rs, const Operand& rt) argument 705 Neg(Register rs, const Operand& rt) argument 714 Slt(Register rd, Register rs, const Operand& rt) argument 730 Sltu(Register rd, Register rs, const Operand& rt) argument 746 Ror(Register rd, Register rs, const Operand& rt) argument 927 Ext(Register rt, Register rs, uint16_t pos, uint16_t size) argument 4326 Assert(Condition cc, const char* msg, Register rs, Operand rt) argument 4361 Check(Condition cc, const char* msg, Register rs, Operand rt) argument [all...] |
H A D | macro-assembler-mips.h | 172 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \ 193 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) { 194 Ret(cond, rs, rt, bd); 199 Register rs, 251 void Movz(Register rd, Register rs, Register rt); 252 void Movn(Register rd, Register rs, Register rt); 253 void Movt(Register rd, Register rs, uint16_t cc = 0); 254 void Movf(Register rd, Register rs, uint16_t cc = 0); 256 void Clz(Register rd, Register rs); 452 uint32_t rs local [all...] |
H A D | regexp-macro-assembler-mips.cc | 1147 Register rs, 1158 __ Branch(&backtrack_label_, condition, rs, rt); 1161 __ Branch(to, condition, rs, rt); 1165 void RegExpMacroAssemblerMIPS::SafeCall(Label* to, Condition cond, Register rs, 1167 __ BranchAndLink(to, cond, rs, rt);
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H A D | regexp-macro-assembler-mips.h | 201 Register rs, 208 Register rs,
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H A D | simulator-mips.cc | 1693 const int32_t rs = get_register(rs_reg); local 1694 const uint32_t rs_u = static_cast<uint32_t>(rs); 1763 alu_out = rt << rs; 1769 alu_out = rt_u >> rs; 1778 alu_out = rt >> rs; 1787 i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt); 1793 if (HaveSameSign(rs, rt)) { 1794 if (rs > 0) { 1795 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt); 1796 } else if (rs < 1920 const int32_t rs = get_register(rs_reg); local 2298 int32_t rs = get_register(instr->RsValue()); local [all...] |
/external/srtp/crypto/include/ |
H A D | stat.h | 64 stat_test_rand_source(rand_source_func_t rs);
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/external/quake/quake/src/QW/dxsdk/sdk/inc/ |
H A D | d3drm.h | 92 STDMETHOD(LoadTextureFromResource) (THIS_ HRSRC rs, LPDIRECT3DRMTEXTURE *) PURE;
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/external/quake/quake/src/WinQuake/dxsdk/SDK/INC/ |
H A D | D3DRM.H | 92 STDMETHOD(LoadTextureFromResource) (THIS_ HRSRC rs, LPDIRECT3DRMTEXTURE *) PURE;
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/external/skia/src/utils/ |
H A D | SkDumpCanvas.cpp | 298 SkString bs, rs; local 300 toString(dst, &rs); 307 rs.prependf("%s ", ss.c_str()); 311 bs.c_str(), rs.c_str());
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