1/************************************************************************** 2ETHERBOOT - BOOTP/TFTP Bootstrap Program 3 4Author: Martin Renters 5 Date: Jun/94 6 7**************************************************************************/ 8 9#define VENDOR_NONE 0 10#define VENDOR_WD 1 11#define VENDOR_NOVELL 2 12#define VENDOR_3COM 3 13 14#define FLAG_PIO 0x01 15#define FLAG_16BIT 0x02 16#define FLAG_790 0x04 17 18#define MEM_8192 32 19#define MEM_16384 64 20#define MEM_32768 128 21 22#define ISA_MAX_ADDR 0x400 23 24/************************************************************************** 25Western Digital/SMC Board Definitions 26**************************************************************************/ 27#define WD_LOW_BASE 0x200 28#define WD_HIGH_BASE 0x3e0 29#ifndef WD_DEFAULT_MEM 30#define WD_DEFAULT_MEM 0xD0000 31#endif 32#define WD_NIC_ADDR 0x10 33 34/************************************************************************** 35Western Digital/SMC ASIC Addresses 36**************************************************************************/ 37#define WD_MSR 0x00 38#define WD_ICR 0x01 39#define WD_IAR 0x02 40#define WD_BIO 0x03 41#define WD_IRR 0x04 42#define WD_LAAR 0x05 43#define WD_IJR 0x06 44#define WD_GP2 0x07 45#define WD_LAR 0x08 46#define WD_BID 0x0E 47 48#define WD_ICR_16BIT 0x01 49 50#define WD_MSR_MENB 0x40 51 52#define WD_LAAR_L16EN 0x40 53#define WD_LAAR_M16EN 0x80 54 55#define WD_SOFTCONFIG 0x20 56 57/************************************************************************** 58Western Digital/SMC Board Types 59**************************************************************************/ 60#define TYPE_WD8003S 0x02 61#define TYPE_WD8003E 0x03 62#define TYPE_WD8013EBT 0x05 63#define TYPE_WD8003W 0x24 64#define TYPE_WD8003EB 0x25 65#define TYPE_WD8013W 0x26 66#define TYPE_WD8013EP 0x27 67#define TYPE_WD8013WC 0x28 68#define TYPE_WD8013EPC 0x29 69#define TYPE_SMC8216T 0x2a 70#define TYPE_SMC8216C 0x2b 71#define TYPE_SMC8416T 0x00 /* Bogus entries: the 8416 generates the */ 72#define TYPE_SMC8416C 0x00 /* the same codes as the 8216. */ 73#define TYPE_SMC8013EBP 0x2c 74 75/************************************************************************** 763com 3c503 definitions 77**************************************************************************/ 78 79#ifndef _3COM_BASE 80#define _3COM_BASE 0x300 81#endif 82 83#define _3COM_TX_PAGE_OFFSET_8BIT 0x20 84#define _3COM_TX_PAGE_OFFSET_16BIT 0x0 85#define _3COM_RX_PAGE_OFFSET_16BIT 0x20 86 87#define _3COM_ASIC_OFFSET 0x400 88#define _3COM_NIC_OFFSET 0x0 89 90#define _3COM_PSTR 0 91#define _3COM_PSPR 1 92 93#define _3COM_BCFR 3 94#define _3COM_BCFR_2E0 0x01 95#define _3COM_BCFR_2A0 0x02 96#define _3COM_BCFR_280 0x04 97#define _3COM_BCFR_250 0x08 98#define _3COM_BCFR_350 0x10 99#define _3COM_BCFR_330 0x20 100#define _3COM_BCFR_310 0x40 101#define _3COM_BCFR_300 0x80 102#define _3COM_PCFR 4 103#define _3COM_PCFR_PIO 0 104#define _3COM_PCFR_C8000 0x10 105#define _3COM_PCFR_CC000 0x20 106#define _3COM_PCFR_D8000 0x40 107#define _3COM_PCFR_DC000 0x80 108#define _3COM_CR 6 109#define _3COM_CR_RST 0x01 /* Reset GA and NIC */ 110#define _3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 111#define _3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 112#define _3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 113#define _3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 114#define _3COM_CR_DBSEL 0x20 /* Double buffer select */ 115#define _3COM_CR_DDIR 0x40 /* DMA direction select */ 116#define _3COM_CR_START 0x80 /* Start DMA controller */ 117#define _3COM_GACFR 5 118#define _3COM_GACFR_MBS0 0x01 119#define _3COM_GACFR_MBS1 0x02 120#define _3COM_GACFR_MBS2 0x04 121#define _3COM_GACFR_RSEL 0x08 /* enable shared memory */ 122#define _3COM_GACFR_TEST 0x10 /* for GA testing */ 123#define _3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 124#define _3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 125#define _3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 126#define _3COM_STREG 7 127#define _3COM_STREG_REV 0x07 /* GA revision */ 128#define _3COM_STREG_DIP 0x08 /* DMA in progress */ 129#define _3COM_STREG_DTC 0x10 /* DMA terminal count */ 130#define _3COM_STREG_OFLW 0x20 /* Overflow */ 131#define _3COM_STREG_UFLW 0x40 /* Underflow */ 132#define _3COM_STREG_DPRDY 0x80 /* Data port ready */ 133#define _3COM_IDCFR 8 134#define _3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 135#define _3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 136#define _3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 137#define _3COM_IDCFR_UNUSED 0x08 /* not used */ 138#define _3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 139#define _3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 140#define _3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 141#define _3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 142#define _3COM_IRQ2 2 143#define _3COM_IRQ3 3 144#define _3COM_IRQ4 4 145#define _3COM_IRQ5 5 146#define _3COM_DAMSB 9 147#define _3COM_DALSB 0x0a 148#define _3COM_VPTR2 0x0b 149#define _3COM_VPTR1 0x0c 150#define _3COM_VPTR0 0x0d 151#define _3COM_RFMSB 0x0e 152#define _3COM_RFLSB 0x0f 153 154/************************************************************************** 155NE1000/2000 definitions 156**************************************************************************/ 157#define NE_ASIC_OFFSET 0x10 158#define NE_RESET 0x0F /* Used to reset card */ 159#define NE_DATA 0x00 /* Used to read/write NIC mem */ 160 161#define COMPEX_RL2000_TRIES 200 162 163/************************************************************************** 1648390 Register Definitions 165**************************************************************************/ 166#define D8390_P0_COMMAND 0x00 167#define D8390_P0_PSTART 0x01 168#define D8390_P0_PSTOP 0x02 169#define D8390_P0_BOUND 0x03 170#define D8390_P0_TSR 0x04 171#define D8390_P0_TPSR 0x04 172#define D8390_P0_TBCR0 0x05 173#define D8390_P0_TBCR1 0x06 174#define D8390_P0_ISR 0x07 175#define D8390_P0_RSAR0 0x08 176#define D8390_P0_RSAR1 0x09 177#define D8390_P0_RBCR0 0x0A 178#define D8390_P0_RBCR1 0x0B 179#define D8390_P0_RSR 0x0C 180#define D8390_P0_RCR 0x0C 181#define D8390_P0_TCR 0x0D 182#define D8390_P0_DCR 0x0E 183#define D8390_P0_IMR 0x0F 184#define D8390_P1_COMMAND 0x00 185#define D8390_P1_PAR0 0x01 186#define D8390_P1_PAR1 0x02 187#define D8390_P1_PAR2 0x03 188#define D8390_P1_PAR3 0x04 189#define D8390_P1_PAR4 0x05 190#define D8390_P1_PAR5 0x06 191#define D8390_P1_CURR 0x07 192#define D8390_P1_MAR0 0x08 193 194#define D8390_COMMAND_PS0 0x0 /* Page 0 select */ 195#define D8390_COMMAND_PS1 0x40 /* Page 1 select */ 196#define D8390_COMMAND_PS2 0x80 /* Page 2 select */ 197#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */ 198#define D8390_COMMAND_RD1 0x10 199#define D8390_COMMAND_RD0 0x08 200#define D8390_COMMAND_TXP 0x04 /* transmit packet */ 201#define D8390_COMMAND_STA 0x02 /* start */ 202#define D8390_COMMAND_STP 0x01 /* stop */ 203 204#define D8390_RCR_MON 0x20 /* monitor mode */ 205 206#define D8390_DCR_FT1 0x40 207#define D8390_DCR_LS 0x08 /* Loopback select */ 208#define D8390_DCR_WTS 0x01 /* Word transfer select */ 209 210#define D8390_ISR_PRX 0x01 /* successful recv */ 211#define D8390_ISR_PTX 0x02 /* successful xmit */ 212#define D8390_ISR_RXE 0x04 /* receive error */ 213#define D8390_ISR_TXE 0x08 /* transmit error */ 214#define D8390_ISR_OVW 0x10 /* Overflow */ 215#define D8390_ISR_CNT 0x20 /* Counter overflow */ 216#define D8390_ISR_RDC 0x40 /* Remote DMA complete */ 217#define D8390_ISR_RST 0x80 /* reset */ 218 219#define D8390_RSTAT_PRX 0x01 /* successful recv */ 220#define D8390_RSTAT_CRC 0x02 /* CRC error */ 221#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */ 222#define D8390_RSTAT_OVER 0x08 /* FIFO overrun */ 223 224#define D8390_TXBUF_SIZE 6 225#define D8390_RXBUF_END 32 226#define D8390_PAGE_SIZE 256 227 228struct ringbuffer { 229 unsigned char status; 230 unsigned char next; 231 unsigned short len; 232}; 233/* 234 * Local variables: 235 * c-basic-offset: 8 236 * End: 237 */ 238 239