1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29 30 /* 31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp 32 */ 33 34#ifndef _AU1000_H_ 35#define _AU1000_H_ 36 37 38#ifndef _LANGUAGE_ASSEMBLY 39 40#include <linux/delay.h> 41#include <linux/types.h> 42 43#include <linux/io.h> 44#include <linux/irq.h> 45 46/* cpu pipeline flush */ 47void static inline au_sync(void) 48{ 49 __asm__ volatile ("sync"); 50} 51 52void static inline au_sync_udelay(int us) 53{ 54 __asm__ volatile ("sync"); 55 udelay(us); 56} 57 58void static inline au_sync_delay(int ms) 59{ 60 __asm__ volatile ("sync"); 61 mdelay(ms); 62} 63 64void static inline au_writeb(u8 val, unsigned long reg) 65{ 66 *(volatile u8 *)reg = val; 67} 68 69void static inline au_writew(u16 val, unsigned long reg) 70{ 71 *(volatile u16 *)reg = val; 72} 73 74void static inline au_writel(u32 val, unsigned long reg) 75{ 76 *(volatile u32 *)reg = val; 77} 78 79static inline u8 au_readb(unsigned long reg) 80{ 81 return *(volatile u8 *)reg; 82} 83 84static inline u16 au_readw(unsigned long reg) 85{ 86 return *(volatile u16 *)reg; 87} 88 89static inline u32 au_readl(unsigned long reg) 90{ 91 return *(volatile u32 *)reg; 92} 93 94 95/* arch/mips/au1000/common/clocks.c */ 96extern void set_au1x00_speed(unsigned int new_freq); 97extern unsigned int get_au1x00_speed(void); 98extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 99extern unsigned long get_au1x00_uart_baud_base(void); 100extern void set_au1x00_lcd_clock(void); 101extern unsigned int get_au1x00_lcd_clock(void); 102 103/* 104 * Every board describes its IRQ mapping with this table. 105 */ 106struct au1xxx_irqmap { 107 int im_irq; 108 int im_type; 109 int im_request; 110}; 111 112/* 113 * init_IRQ looks for a table with this name. 114 */ 115extern struct au1xxx_irqmap au1xxx_irq_map[]; 116 117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 118 119/* 120 * SDRAM register offsets 121 */ 122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ 123 defined(CONFIG_SOC_AU1100) 124#define MEM_SDMODE0 0x0000 125#define MEM_SDMODE1 0x0004 126#define MEM_SDMODE2 0x0008 127#define MEM_SDADDR0 0x000C 128#define MEM_SDADDR1 0x0010 129#define MEM_SDADDR2 0x0014 130#define MEM_SDREFCFG 0x0018 131#define MEM_SDPRECMD 0x001C 132#define MEM_SDAUTOREF 0x0020 133#define MEM_SDWRMD0 0x0024 134#define MEM_SDWRMD1 0x0028 135#define MEM_SDWRMD2 0x002C 136#define MEM_SDSLEEP 0x0030 137#define MEM_SDSMCKE 0x0034 138 139/* 140 * MEM_SDMODE register content definitions 141 */ 142#define MEM_SDMODE_F (1 << 22) 143#define MEM_SDMODE_SR (1 << 21) 144#define MEM_SDMODE_BS (1 << 20) 145#define MEM_SDMODE_RS (3 << 18) 146#define MEM_SDMODE_CS (7 << 15) 147#define MEM_SDMODE_TRAS (15 << 11) 148#define MEM_SDMODE_TMRD (3 << 9) 149#define MEM_SDMODE_TWR (3 << 7) 150#define MEM_SDMODE_TRP (3 << 5) 151#define MEM_SDMODE_TRCD (3 << 3) 152#define MEM_SDMODE_TCL (7 << 0) 153 154#define MEM_SDMODE_BS_2Bank (0 << 20) 155#define MEM_SDMODE_BS_4Bank (1 << 20) 156#define MEM_SDMODE_RS_11Row (0 << 18) 157#define MEM_SDMODE_RS_12Row (1 << 18) 158#define MEM_SDMODE_RS_13Row (2 << 18) 159#define MEM_SDMODE_RS_N(N) ((N) << 18) 160#define MEM_SDMODE_CS_7Col (0 << 15) 161#define MEM_SDMODE_CS_8Col (1 << 15) 162#define MEM_SDMODE_CS_9Col (2 << 15) 163#define MEM_SDMODE_CS_10Col (3 << 15) 164#define MEM_SDMODE_CS_11Col (4 << 15) 165#define MEM_SDMODE_CS_N(N) ((N) << 15) 166#define MEM_SDMODE_TRAS_N(N) ((N) << 11) 167#define MEM_SDMODE_TMRD_N(N) ((N) << 9) 168#define MEM_SDMODE_TWR_N(N) ((N) << 7) 169#define MEM_SDMODE_TRP_N(N) ((N) << 5) 170#define MEM_SDMODE_TRCD_N(N) ((N) << 3) 171#define MEM_SDMODE_TCL_N(N) ((N) << 0) 172 173/* 174 * MEM_SDADDR register contents definitions 175 */ 176#define MEM_SDADDR_E (1 << 20) 177#define MEM_SDADDR_CSBA (0x03FF << 10) 178#define MEM_SDADDR_CSMASK (0x03FF << 0) 179#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) 180#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) 181 182/* 183 * MEM_SDREFCFG register content definitions 184 */ 185#define MEM_SDREFCFG_TRC (15 << 28) 186#define MEM_SDREFCFG_TRPM (3 << 26) 187#define MEM_SDREFCFG_E (1 << 25) 188#define MEM_SDREFCFG_RE (0x1ffffff << 0) 189#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) 190#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) 191#define MEM_SDREFCFG_REF_N(N) (N) 192#endif 193 194/***********************************************************************/ 195 196/* 197 * Au1550 SDRAM Register Offsets 198 */ 199 200/***********************************************************************/ 201 202#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 203#define MEM_SDMODE0 0x0800 204#define MEM_SDMODE1 0x0808 205#define MEM_SDMODE2 0x0810 206#define MEM_SDADDR0 0x0820 207#define MEM_SDADDR1 0x0828 208#define MEM_SDADDR2 0x0830 209#define MEM_SDCONFIGA 0x0840 210#define MEM_SDCONFIGB 0x0848 211#define MEM_SDSTAT 0x0850 212#define MEM_SDERRADDR 0x0858 213#define MEM_SDSTRIDE0 0x0860 214#define MEM_SDSTRIDE1 0x0868 215#define MEM_SDSTRIDE2 0x0870 216#define MEM_SDWRMD0 0x0880 217#define MEM_SDWRMD1 0x0888 218#define MEM_SDWRMD2 0x0890 219#define MEM_SDPRECMD 0x08C0 220#define MEM_SDAUTOREF 0x08C8 221#define MEM_SDSREF 0x08D0 222#define MEM_SDSLEEP MEM_SDSREF 223 224#endif 225 226/* 227 * Physical base addresses for integrated peripherals 228 */ 229 230#ifdef CONFIG_SOC_AU1000 231#define MEM_PHYS_ADDR 0x14000000 232#define STATIC_MEM_PHYS_ADDR 0x14001000 233#define DMA0_PHYS_ADDR 0x14002000 234#define DMA1_PHYS_ADDR 0x14002100 235#define DMA2_PHYS_ADDR 0x14002200 236#define DMA3_PHYS_ADDR 0x14002300 237#define DMA4_PHYS_ADDR 0x14002400 238#define DMA5_PHYS_ADDR 0x14002500 239#define DMA6_PHYS_ADDR 0x14002600 240#define DMA7_PHYS_ADDR 0x14002700 241#define IC0_PHYS_ADDR 0x10400000 242#define IC1_PHYS_ADDR 0x11800000 243#define AC97_PHYS_ADDR 0x10000000 244#define USBH_PHYS_ADDR 0x10100000 245#define USBD_PHYS_ADDR 0x10200000 246#define IRDA_PHYS_ADDR 0x10300000 247#define MAC0_PHYS_ADDR 0x10500000 248#define MAC1_PHYS_ADDR 0x10510000 249#define MACEN_PHYS_ADDR 0x10520000 250#define MACDMA0_PHYS_ADDR 0x14004000 251#define MACDMA1_PHYS_ADDR 0x14004200 252#define I2S_PHYS_ADDR 0x11000000 253#define UART0_PHYS_ADDR 0x11100000 254#define UART1_PHYS_ADDR 0x11200000 255#define UART2_PHYS_ADDR 0x11300000 256#define UART3_PHYS_ADDR 0x11400000 257#define SSI0_PHYS_ADDR 0x11600000 258#define SSI1_PHYS_ADDR 0x11680000 259#define SYS_PHYS_ADDR 0x11900000 260#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 261#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 262#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 263#endif 264 265/********************************************************************/ 266 267#ifdef CONFIG_SOC_AU1500 268#define MEM_PHYS_ADDR 0x14000000 269#define STATIC_MEM_PHYS_ADDR 0x14001000 270#define DMA0_PHYS_ADDR 0x14002000 271#define DMA1_PHYS_ADDR 0x14002100 272#define DMA2_PHYS_ADDR 0x14002200 273#define DMA3_PHYS_ADDR 0x14002300 274#define DMA4_PHYS_ADDR 0x14002400 275#define DMA5_PHYS_ADDR 0x14002500 276#define DMA6_PHYS_ADDR 0x14002600 277#define DMA7_PHYS_ADDR 0x14002700 278#define IC0_PHYS_ADDR 0x10400000 279#define IC1_PHYS_ADDR 0x11800000 280#define AC97_PHYS_ADDR 0x10000000 281#define USBH_PHYS_ADDR 0x10100000 282#define USBD_PHYS_ADDR 0x10200000 283#define PCI_PHYS_ADDR 0x14005000 284#define MAC0_PHYS_ADDR 0x11500000 285#define MAC1_PHYS_ADDR 0x11510000 286#define MACEN_PHYS_ADDR 0x11520000 287#define MACDMA0_PHYS_ADDR 0x14004000 288#define MACDMA1_PHYS_ADDR 0x14004200 289#define I2S_PHYS_ADDR 0x11000000 290#define UART0_PHYS_ADDR 0x11100000 291#define UART3_PHYS_ADDR 0x11400000 292#define GPIO2_PHYS_ADDR 0x11700000 293#define SYS_PHYS_ADDR 0x11900000 294#define PCI_MEM_PHYS_ADDR 0x400000000ULL 295#define PCI_IO_PHYS_ADDR 0x500000000ULL 296#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 297#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 298#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 299#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 300#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 301#endif 302 303/********************************************************************/ 304 305#ifdef CONFIG_SOC_AU1100 306#define MEM_PHYS_ADDR 0x14000000 307#define STATIC_MEM_PHYS_ADDR 0x14001000 308#define DMA0_PHYS_ADDR 0x14002000 309#define DMA1_PHYS_ADDR 0x14002100 310#define DMA2_PHYS_ADDR 0x14002200 311#define DMA3_PHYS_ADDR 0x14002300 312#define DMA4_PHYS_ADDR 0x14002400 313#define DMA5_PHYS_ADDR 0x14002500 314#define DMA6_PHYS_ADDR 0x14002600 315#define DMA7_PHYS_ADDR 0x14002700 316#define IC0_PHYS_ADDR 0x10400000 317#define SD0_PHYS_ADDR 0x10600000 318#define SD1_PHYS_ADDR 0x10680000 319#define IC1_PHYS_ADDR 0x11800000 320#define AC97_PHYS_ADDR 0x10000000 321#define USBH_PHYS_ADDR 0x10100000 322#define USBD_PHYS_ADDR 0x10200000 323#define IRDA_PHYS_ADDR 0x10300000 324#define MAC0_PHYS_ADDR 0x10500000 325#define MACEN_PHYS_ADDR 0x10520000 326#define MACDMA0_PHYS_ADDR 0x14004000 327#define MACDMA1_PHYS_ADDR 0x14004200 328#define I2S_PHYS_ADDR 0x11000000 329#define UART0_PHYS_ADDR 0x11100000 330#define UART1_PHYS_ADDR 0x11200000 331#define UART3_PHYS_ADDR 0x11400000 332#define SSI0_PHYS_ADDR 0x11600000 333#define SSI1_PHYS_ADDR 0x11680000 334#define GPIO2_PHYS_ADDR 0x11700000 335#define SYS_PHYS_ADDR 0x11900000 336#define LCD_PHYS_ADDR 0x15000000 337#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 338#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 339#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 340#endif 341 342/***********************************************************************/ 343 344#ifdef CONFIG_SOC_AU1550 345#define MEM_PHYS_ADDR 0x14000000 346#define STATIC_MEM_PHYS_ADDR 0x14001000 347#define IC0_PHYS_ADDR 0x10400000 348#define IC1_PHYS_ADDR 0x11800000 349#define USBH_PHYS_ADDR 0x14020000 350#define USBD_PHYS_ADDR 0x10200000 351#define PCI_PHYS_ADDR 0x14005000 352#define MAC0_PHYS_ADDR 0x10500000 353#define MAC1_PHYS_ADDR 0x10510000 354#define MACEN_PHYS_ADDR 0x10520000 355#define MACDMA0_PHYS_ADDR 0x14004000 356#define MACDMA1_PHYS_ADDR 0x14004200 357#define UART0_PHYS_ADDR 0x11100000 358#define UART1_PHYS_ADDR 0x11200000 359#define UART3_PHYS_ADDR 0x11400000 360#define GPIO2_PHYS_ADDR 0x11700000 361#define SYS_PHYS_ADDR 0x11900000 362#define DDMA_PHYS_ADDR 0x14002000 363#define PE_PHYS_ADDR 0x14008000 364#define PSC0_PHYS_ADDR 0x11A00000 365#define PSC1_PHYS_ADDR 0x11B00000 366#define PSC2_PHYS_ADDR 0x10A00000 367#define PSC3_PHYS_ADDR 0x10B00000 368#define PCI_MEM_PHYS_ADDR 0x400000000ULL 369#define PCI_IO_PHYS_ADDR 0x500000000ULL 370#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 371#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 372#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 373#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 374#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 375#endif 376 377/***********************************************************************/ 378 379#ifdef CONFIG_SOC_AU1200 380#define MEM_PHYS_ADDR 0x14000000 381#define STATIC_MEM_PHYS_ADDR 0x14001000 382#define AES_PHYS_ADDR 0x10300000 383#define CIM_PHYS_ADDR 0x14004000 384#define IC0_PHYS_ADDR 0x10400000 385#define IC1_PHYS_ADDR 0x11800000 386#define USBM_PHYS_ADDR 0x14020000 387#define USBH_PHYS_ADDR 0x14020100 388#define UART0_PHYS_ADDR 0x11100000 389#define UART1_PHYS_ADDR 0x11200000 390#define GPIO2_PHYS_ADDR 0x11700000 391#define SYS_PHYS_ADDR 0x11900000 392#define DDMA_PHYS_ADDR 0x14002000 393#define PSC0_PHYS_ADDR 0x11A00000 394#define PSC1_PHYS_ADDR 0x11B00000 395#define SD0_PHYS_ADDR 0x10600000 396#define SD1_PHYS_ADDR 0x10680000 397#define LCD_PHYS_ADDR 0x15000000 398#define SWCNT_PHYS_ADDR 0x1110010C 399#define MAEFE_PHYS_ADDR 0x14012000 400#define MAEBE_PHYS_ADDR 0x14010000 401#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 402#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 403#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 404#endif 405 406/* Static Bus Controller */ 407#define MEM_STCFG0 0xB4001000 408#define MEM_STTIME0 0xB4001004 409#define MEM_STADDR0 0xB4001008 410 411#define MEM_STCFG1 0xB4001010 412#define MEM_STTIME1 0xB4001014 413#define MEM_STADDR1 0xB4001018 414 415#define MEM_STCFG2 0xB4001020 416#define MEM_STTIME2 0xB4001024 417#define MEM_STADDR2 0xB4001028 418 419#define MEM_STCFG3 0xB4001030 420#define MEM_STTIME3 0xB4001034 421#define MEM_STADDR3 0xB4001038 422 423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 424#define MEM_STNDCTL 0xB4001100 425#define MEM_STSTAT 0xB4001104 426 427#define MEM_STNAND_CMD 0x0 428#define MEM_STNAND_ADDR 0x4 429#define MEM_STNAND_DATA 0x20 430#endif 431 432/* Interrupt Controller 0 */ 433#define IC0_CFG0RD 0xB0400040 434#define IC0_CFG0SET 0xB0400040 435#define IC0_CFG0CLR 0xB0400044 436 437#define IC0_CFG1RD 0xB0400048 438#define IC0_CFG1SET 0xB0400048 439#define IC0_CFG1CLR 0xB040004C 440 441#define IC0_CFG2RD 0xB0400050 442#define IC0_CFG2SET 0xB0400050 443#define IC0_CFG2CLR 0xB0400054 444 445#define IC0_REQ0INT 0xB0400054 446#define IC0_SRCRD 0xB0400058 447#define IC0_SRCSET 0xB0400058 448#define IC0_SRCCLR 0xB040005C 449#define IC0_REQ1INT 0xB040005C 450 451#define IC0_ASSIGNRD 0xB0400060 452#define IC0_ASSIGNSET 0xB0400060 453#define IC0_ASSIGNCLR 0xB0400064 454 455#define IC0_WAKERD 0xB0400068 456#define IC0_WAKESET 0xB0400068 457#define IC0_WAKECLR 0xB040006C 458 459#define IC0_MASKRD 0xB0400070 460#define IC0_MASKSET 0xB0400070 461#define IC0_MASKCLR 0xB0400074 462 463#define IC0_RISINGRD 0xB0400078 464#define IC0_RISINGCLR 0xB0400078 465#define IC0_FALLINGRD 0xB040007C 466#define IC0_FALLINGCLR 0xB040007C 467 468#define IC0_TESTBIT 0xB0400080 469 470/* Interrupt Controller 1 */ 471#define IC1_CFG0RD 0xB1800040 472#define IC1_CFG0SET 0xB1800040 473#define IC1_CFG0CLR 0xB1800044 474 475#define IC1_CFG1RD 0xB1800048 476#define IC1_CFG1SET 0xB1800048 477#define IC1_CFG1CLR 0xB180004C 478 479#define IC1_CFG2RD 0xB1800050 480#define IC1_CFG2SET 0xB1800050 481#define IC1_CFG2CLR 0xB1800054 482 483#define IC1_REQ0INT 0xB1800054 484#define IC1_SRCRD 0xB1800058 485#define IC1_SRCSET 0xB1800058 486#define IC1_SRCCLR 0xB180005C 487#define IC1_REQ1INT 0xB180005C 488 489#define IC1_ASSIGNRD 0xB1800060 490#define IC1_ASSIGNSET 0xB1800060 491#define IC1_ASSIGNCLR 0xB1800064 492 493#define IC1_WAKERD 0xB1800068 494#define IC1_WAKESET 0xB1800068 495#define IC1_WAKECLR 0xB180006C 496 497#define IC1_MASKRD 0xB1800070 498#define IC1_MASKSET 0xB1800070 499#define IC1_MASKCLR 0xB1800074 500 501#define IC1_RISINGRD 0xB1800078 502#define IC1_RISINGCLR 0xB1800078 503#define IC1_FALLINGRD 0xB180007C 504#define IC1_FALLINGCLR 0xB180007C 505 506#define IC1_TESTBIT 0xB1800080 507 508/* Interrupt Configuration Modes */ 509#define INTC_INT_DISABLED 0x0 510#define INTC_INT_RISE_EDGE 0x1 511#define INTC_INT_FALL_EDGE 0x2 512#define INTC_INT_RISE_AND_FALL_EDGE 0x3 513#define INTC_INT_HIGH_LEVEL 0x5 514#define INTC_INT_LOW_LEVEL 0x6 515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 516 517/* Interrupt Numbers */ 518/* Au1000 */ 519#ifdef CONFIG_SOC_AU1000 520enum soc_au1000_ints { 521 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 522 AU1000_UART0_INT = AU1000_FIRST_INT, 523 AU1000_UART1_INT, /* au1000 */ 524 AU1000_UART2_INT, /* au1000 */ 525 AU1000_UART3_INT, 526 AU1000_SSI0_INT, /* au1000 */ 527 AU1000_SSI1_INT, /* au1000 */ 528 AU1000_DMA_INT_BASE, 529 530 AU1000_TOY_INT = AU1000_FIRST_INT + 14, 531 AU1000_TOY_MATCH0_INT, 532 AU1000_TOY_MATCH1_INT, 533 AU1000_TOY_MATCH2_INT, 534 AU1000_RTC_INT, 535 AU1000_RTC_MATCH0_INT, 536 AU1000_RTC_MATCH1_INT, 537 AU1000_RTC_MATCH2_INT, 538 AU1000_IRDA_TX_INT, /* au1000 */ 539 AU1000_IRDA_RX_INT, /* au1000 */ 540 AU1000_USB_DEV_REQ_INT, 541 AU1000_USB_DEV_SUS_INT, 542 AU1000_USB_HOST_INT, 543 AU1000_ACSYNC_INT, 544 AU1000_MAC0_DMA_INT, 545 AU1000_MAC1_DMA_INT, 546 AU1000_I2S_UO_INT, /* au1000 */ 547 AU1000_AC97C_INT, 548 AU1000_GPIO_0, 549 AU1000_GPIO_1, 550 AU1000_GPIO_2, 551 AU1000_GPIO_3, 552 AU1000_GPIO_4, 553 AU1000_GPIO_5, 554 AU1000_GPIO_6, 555 AU1000_GPIO_7, 556 AU1000_GPIO_8, 557 AU1000_GPIO_9, 558 AU1000_GPIO_10, 559 AU1000_GPIO_11, 560 AU1000_GPIO_12, 561 AU1000_GPIO_13, 562 AU1000_GPIO_14, 563 AU1000_GPIO_15, 564 AU1000_GPIO_16, 565 AU1000_GPIO_17, 566 AU1000_GPIO_18, 567 AU1000_GPIO_19, 568 AU1000_GPIO_20, 569 AU1000_GPIO_21, 570 AU1000_GPIO_22, 571 AU1000_GPIO_23, 572 AU1000_GPIO_24, 573 AU1000_GPIO_25, 574 AU1000_GPIO_26, 575 AU1000_GPIO_27, 576 AU1000_GPIO_28, 577 AU1000_GPIO_29, 578 AU1000_GPIO_30, 579 AU1000_GPIO_31, 580}; 581 582#define UART0_ADDR 0xB1100000 583#define UART1_ADDR 0xB1200000 584#define UART2_ADDR 0xB1300000 585#define UART3_ADDR 0xB1400000 586 587#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 588#define USB_HOST_CONFIG 0xB017FFFC 589 590#define AU1000_ETH0_BASE 0xB0500000 591#define AU1000_ETH1_BASE 0xB0510000 592#define AU1000_MAC0_ENABLE 0xB0520000 593#define AU1000_MAC1_ENABLE 0xB0520004 594#define NUM_ETH_INTERFACES 2 595#endif /* CONFIG_SOC_AU1000 */ 596 597/* Au1500 */ 598#ifdef CONFIG_SOC_AU1500 599enum soc_au1500_ints { 600 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 601 AU1500_UART0_INT = AU1500_FIRST_INT, 602 AU1000_PCI_INTA, /* au1500 */ 603 AU1000_PCI_INTB, /* au1500 */ 604 AU1500_UART3_INT, 605 AU1000_PCI_INTC, /* au1500 */ 606 AU1000_PCI_INTD, /* au1500 */ 607 AU1000_DMA_INT_BASE, 608 609 AU1000_TOY_INT = AU1500_FIRST_INT + 14, 610 AU1000_TOY_MATCH0_INT, 611 AU1000_TOY_MATCH1_INT, 612 AU1000_TOY_MATCH2_INT, 613 AU1000_RTC_INT, 614 AU1000_RTC_MATCH0_INT, 615 AU1000_RTC_MATCH1_INT, 616 AU1000_RTC_MATCH2_INT, 617 AU1500_PCI_ERR_INT, 618 AU1500_RESERVED_INT, 619 AU1000_USB_DEV_REQ_INT, 620 AU1000_USB_DEV_SUS_INT, 621 AU1000_USB_HOST_INT, 622 AU1000_ACSYNC_INT, 623 AU1500_MAC0_DMA_INT, 624 AU1500_MAC1_DMA_INT, 625 AU1000_AC97C_INT = AU1500_FIRST_INT + 31, 626 AU1000_GPIO_0, 627 AU1000_GPIO_1, 628 AU1000_GPIO_2, 629 AU1000_GPIO_3, 630 AU1000_GPIO_4, 631 AU1000_GPIO_5, 632 AU1000_GPIO_6, 633 AU1000_GPIO_7, 634 AU1000_GPIO_8, 635 AU1000_GPIO_9, 636 AU1000_GPIO_10, 637 AU1000_GPIO_11, 638 AU1000_GPIO_12, 639 AU1000_GPIO_13, 640 AU1000_GPIO_14, 641 AU1000_GPIO_15, 642 AU1500_GPIO_200, 643 AU1500_GPIO_201, 644 AU1500_GPIO_202, 645 AU1500_GPIO_203, 646 AU1500_GPIO_20, 647 AU1500_GPIO_204, 648 AU1500_GPIO_205, 649 AU1500_GPIO_23, 650 AU1500_GPIO_24, 651 AU1500_GPIO_25, 652 AU1500_GPIO_26, 653 AU1500_GPIO_27, 654 AU1500_GPIO_28, 655 AU1500_GPIO_206, 656 AU1500_GPIO_207, 657 AU1500_GPIO_208_215, 658}; 659 660/* shortcuts */ 661#define INTA AU1000_PCI_INTA 662#define INTB AU1000_PCI_INTB 663#define INTC AU1000_PCI_INTC 664#define INTD AU1000_PCI_INTD 665 666#define UART0_ADDR 0xB1100000 667#define UART3_ADDR 0xB1400000 668 669#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 670#define USB_HOST_CONFIG 0xB017fffc 671 672#define AU1500_ETH0_BASE 0xB1500000 673#define AU1500_ETH1_BASE 0xB1510000 674#define AU1500_MAC0_ENABLE 0xB1520000 675#define AU1500_MAC1_ENABLE 0xB1520004 676#define NUM_ETH_INTERFACES 2 677#endif /* CONFIG_SOC_AU1500 */ 678 679/* Au1100 */ 680#ifdef CONFIG_SOC_AU1100 681enum soc_au1100_ints { 682 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 683 AU1100_UART0_INT, 684 AU1100_UART1_INT, 685 AU1100_SD_INT, 686 AU1100_UART3_INT, 687 AU1000_SSI0_INT, 688 AU1000_SSI1_INT, 689 AU1000_DMA_INT_BASE, 690 691 AU1000_TOY_INT = AU1100_FIRST_INT + 14, 692 AU1000_TOY_MATCH0_INT, 693 AU1000_TOY_MATCH1_INT, 694 AU1000_TOY_MATCH2_INT, 695 AU1000_RTC_INT, 696 AU1000_RTC_MATCH0_INT, 697 AU1000_RTC_MATCH1_INT, 698 AU1000_RTC_MATCH2_INT, 699 AU1000_IRDA_TX_INT, 700 AU1000_IRDA_RX_INT, 701 AU1000_USB_DEV_REQ_INT, 702 AU1000_USB_DEV_SUS_INT, 703 AU1000_USB_HOST_INT, 704 AU1000_ACSYNC_INT, 705 AU1100_MAC0_DMA_INT, 706 AU1100_GPIO_208_215, 707 AU1100_LCD_INT, 708 AU1000_AC97C_INT, 709 AU1000_GPIO_0, 710 AU1000_GPIO_1, 711 AU1000_GPIO_2, 712 AU1000_GPIO_3, 713 AU1000_GPIO_4, 714 AU1000_GPIO_5, 715 AU1000_GPIO_6, 716 AU1000_GPIO_7, 717 AU1000_GPIO_8, 718 AU1000_GPIO_9, 719 AU1000_GPIO_10, 720 AU1000_GPIO_11, 721 AU1000_GPIO_12, 722 AU1000_GPIO_13, 723 AU1000_GPIO_14, 724 AU1000_GPIO_15, 725 AU1000_GPIO_16, 726 AU1000_GPIO_17, 727 AU1000_GPIO_18, 728 AU1000_GPIO_19, 729 AU1000_GPIO_20, 730 AU1000_GPIO_21, 731 AU1000_GPIO_22, 732 AU1000_GPIO_23, 733 AU1000_GPIO_24, 734 AU1000_GPIO_25, 735 AU1000_GPIO_26, 736 AU1000_GPIO_27, 737 AU1000_GPIO_28, 738 AU1000_GPIO_29, 739 AU1000_GPIO_30, 740 AU1000_GPIO_31, 741}; 742 743#define UART0_ADDR 0xB1100000 744#define UART1_ADDR 0xB1200000 745#define UART3_ADDR 0xB1400000 746 747#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 748#define USB_HOST_CONFIG 0xB017FFFC 749 750#define AU1100_ETH0_BASE 0xB0500000 751#define AU1100_MAC0_ENABLE 0xB0520000 752#define NUM_ETH_INTERFACES 1 753#endif /* CONFIG_SOC_AU1100 */ 754 755#ifdef CONFIG_SOC_AU1550 756enum soc_au1550_ints { 757 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 758 AU1550_UART0_INT = AU1550_FIRST_INT, 759 AU1550_PCI_INTA, 760 AU1550_PCI_INTB, 761 AU1550_DDMA_INT, 762 AU1550_CRYPTO_INT, 763 AU1550_PCI_INTC, 764 AU1550_PCI_INTD, 765 AU1550_PCI_RST_INT, 766 AU1550_UART1_INT, 767 AU1550_UART3_INT, 768 AU1550_PSC0_INT, 769 AU1550_PSC1_INT, 770 AU1550_PSC2_INT, 771 AU1550_PSC3_INT, 772 AU1000_TOY_INT, 773 AU1000_TOY_MATCH0_INT, 774 AU1000_TOY_MATCH1_INT, 775 AU1000_TOY_MATCH2_INT, 776 AU1000_RTC_INT, 777 AU1000_RTC_MATCH0_INT, 778 AU1000_RTC_MATCH1_INT, 779 AU1000_RTC_MATCH2_INT, 780 781 AU1550_NAND_INT = AU1550_FIRST_INT + 23, 782 AU1550_USB_DEV_REQ_INT, 783 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, 784 AU1550_USB_DEV_SUS_INT, 785 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, 786 AU1550_USB_HOST_INT, 787 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, 788 AU1550_MAC0_DMA_INT, 789 AU1550_MAC1_DMA_INT, 790 AU1000_GPIO_0 = AU1550_FIRST_INT + 32, 791 AU1000_GPIO_1, 792 AU1000_GPIO_2, 793 AU1000_GPIO_3, 794 AU1000_GPIO_4, 795 AU1000_GPIO_5, 796 AU1000_GPIO_6, 797 AU1000_GPIO_7, 798 AU1000_GPIO_8, 799 AU1000_GPIO_9, 800 AU1000_GPIO_10, 801 AU1000_GPIO_11, 802 AU1000_GPIO_12, 803 AU1000_GPIO_13, 804 AU1000_GPIO_14, 805 AU1000_GPIO_15, 806 AU1550_GPIO_200, 807 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ 808 AU1500_GPIO_16, 809 AU1500_GPIO_17, 810 AU1500_GPIO_20, 811 AU1500_GPIO_21, 812 AU1500_GPIO_22, 813 AU1500_GPIO_23, 814 AU1500_GPIO_24, 815 AU1500_GPIO_25, 816 AU1500_GPIO_26, 817 AU1500_GPIO_27, 818 AU1500_GPIO_28, 819 AU1500_GPIO_206, 820 AU1500_GPIO_207, 821 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ 822}; 823 824/* shortcuts */ 825#define INTA AU1550_PCI_INTA 826#define INTB AU1550_PCI_INTB 827#define INTC AU1550_PCI_INTC 828#define INTD AU1550_PCI_INTD 829 830#define UART0_ADDR 0xB1100000 831#define UART1_ADDR 0xB1200000 832#define UART3_ADDR 0xB1400000 833 834#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 835#define USB_OHCI_LEN 0x00060000 836#define USB_HOST_CONFIG 0xB4027ffc 837 838#define AU1550_ETH0_BASE 0xB0500000 839#define AU1550_ETH1_BASE 0xB0510000 840#define AU1550_MAC0_ENABLE 0xB0520000 841#define AU1550_MAC1_ENABLE 0xB0520004 842#define NUM_ETH_INTERFACES 2 843#endif /* CONFIG_SOC_AU1550 */ 844 845#ifdef CONFIG_SOC_AU1200 846enum soc_au1200_ints { 847 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 848 AU1200_UART0_INT = AU1200_FIRST_INT, 849 AU1200_SWT_INT, 850 AU1200_SD_INT, 851 AU1200_DDMA_INT, 852 AU1200_MAE_BE_INT, 853 AU1200_GPIO_200, 854 AU1200_GPIO_201, 855 AU1200_GPIO_202, 856 AU1200_UART1_INT, 857 AU1200_MAE_FE_INT, 858 AU1200_PSC0_INT, 859 AU1200_PSC1_INT, 860 AU1200_AES_INT, 861 AU1200_CAMERA_INT, 862 AU1000_TOY_INT, 863 AU1000_TOY_MATCH0_INT, 864 AU1000_TOY_MATCH1_INT, 865 AU1000_TOY_MATCH2_INT, 866 AU1000_RTC_INT, 867 AU1000_RTC_MATCH0_INT, 868 AU1000_RTC_MATCH1_INT, 869 AU1000_RTC_MATCH2_INT, 870 871 AU1200_NAND_INT = AU1200_FIRST_INT + 23, 872 AU1200_GPIO_204, 873 AU1200_GPIO_205, 874 AU1200_GPIO_206, 875 AU1200_GPIO_207, 876 AU1200_GPIO_208_215, /* Logical OR of 208:215 */ 877 AU1200_USB_INT, 878 AU1000_USB_HOST_INT = AU1200_USB_INT, 879 AU1200_LCD_INT, 880 AU1200_MAE_BOTH_INT, 881 AU1000_GPIO_0, 882 AU1000_GPIO_1, 883 AU1000_GPIO_2, 884 AU1000_GPIO_3, 885 AU1000_GPIO_4, 886 AU1000_GPIO_5, 887 AU1000_GPIO_6, 888 AU1000_GPIO_7, 889 AU1000_GPIO_8, 890 AU1000_GPIO_9, 891 AU1000_GPIO_10, 892 AU1000_GPIO_11, 893 AU1000_GPIO_12, 894 AU1000_GPIO_13, 895 AU1000_GPIO_14, 896 AU1000_GPIO_15, 897 AU1000_GPIO_16, 898 AU1000_GPIO_17, 899 AU1000_GPIO_18, 900 AU1000_GPIO_19, 901 AU1000_GPIO_20, 902 AU1000_GPIO_21, 903 AU1000_GPIO_22, 904 AU1000_GPIO_23, 905 AU1000_GPIO_24, 906 AU1000_GPIO_25, 907 AU1000_GPIO_26, 908 AU1000_GPIO_27, 909 AU1000_GPIO_28, 910 AU1000_GPIO_29, 911 AU1000_GPIO_30, 912 AU1000_GPIO_31, 913}; 914 915#define UART0_ADDR 0xB1100000 916#define UART1_ADDR 0xB1200000 917 918#define USB_UOC_BASE 0x14020020 919#define USB_UOC_LEN 0x20 920#define USB_OHCI_BASE 0x14020100 921#define USB_OHCI_LEN 0x100 922#define USB_EHCI_BASE 0x14020200 923#define USB_EHCI_LEN 0x100 924#define USB_UDC_BASE 0x14022000 925#define USB_UDC_LEN 0x2000 926#define USB_MSR_BASE 0xB4020000 927#define USB_MSR_MCFG 4 928#define USBMSRMCFG_OMEMEN 0 929#define USBMSRMCFG_OBMEN 1 930#define USBMSRMCFG_EMEMEN 2 931#define USBMSRMCFG_EBMEN 3 932#define USBMSRMCFG_DMEMEN 4 933#define USBMSRMCFG_DBMEN 5 934#define USBMSRMCFG_GMEMEN 6 935#define USBMSRMCFG_OHCCLKEN 16 936#define USBMSRMCFG_EHCCLKEN 17 937#define USBMSRMCFG_UDCCLKEN 18 938#define USBMSRMCFG_PHYPLLEN 19 939#define USBMSRMCFG_RDCOMB 30 940#define USBMSRMCFG_PFEN 31 941 942#endif /* CONFIG_SOC_AU1200 */ 943 944#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 945#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 946#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) 947#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 948 949#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 950#define INTX 0xFF /* not valid */ 951 952/* Programmable Counters 0 and 1 */ 953#define SYS_BASE 0xB1900000 954#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 955# define SYS_CNTRL_E1S (1 << 23) 956# define SYS_CNTRL_T1S (1 << 20) 957# define SYS_CNTRL_M21 (1 << 19) 958# define SYS_CNTRL_M11 (1 << 18) 959# define SYS_CNTRL_M01 (1 << 17) 960# define SYS_CNTRL_C1S (1 << 16) 961# define SYS_CNTRL_BP (1 << 14) 962# define SYS_CNTRL_EN1 (1 << 13) 963# define SYS_CNTRL_BT1 (1 << 12) 964# define SYS_CNTRL_EN0 (1 << 11) 965# define SYS_CNTRL_BT0 (1 << 10) 966# define SYS_CNTRL_E0 (1 << 8) 967# define SYS_CNTRL_E0S (1 << 7) 968# define SYS_CNTRL_32S (1 << 5) 969# define SYS_CNTRL_T0S (1 << 4) 970# define SYS_CNTRL_M20 (1 << 3) 971# define SYS_CNTRL_M10 (1 << 2) 972# define SYS_CNTRL_M00 (1 << 1) 973# define SYS_CNTRL_C0S (1 << 0) 974 975/* Programmable Counter 0 Registers */ 976#define SYS_TOYTRIM (SYS_BASE + 0) 977#define SYS_TOYWRITE (SYS_BASE + 4) 978#define SYS_TOYMATCH0 (SYS_BASE + 8) 979#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 980#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 981#define SYS_TOYREAD (SYS_BASE + 0x40) 982 983/* Programmable Counter 1 Registers */ 984#define SYS_RTCTRIM (SYS_BASE + 0x44) 985#define SYS_RTCWRITE (SYS_BASE + 0x48) 986#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 987#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 988#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 989#define SYS_RTCREAD (SYS_BASE + 0x58) 990 991/* I2S Controller */ 992#define I2S_DATA 0xB1000000 993# define I2S_DATA_MASK 0xffffff 994#define I2S_CONFIG 0xB1000004 995# define I2S_CONFIG_XU (1 << 25) 996# define I2S_CONFIG_XO (1 << 24) 997# define I2S_CONFIG_RU (1 << 23) 998# define I2S_CONFIG_RO (1 << 22) 999# define I2S_CONFIG_TR (1 << 21) 1000# define I2S_CONFIG_TE (1 << 20) 1001# define I2S_CONFIG_TF (1 << 19) 1002# define I2S_CONFIG_RR (1 << 18) 1003# define I2S_CONFIG_RE (1 << 17) 1004# define I2S_CONFIG_RF (1 << 16) 1005# define I2S_CONFIG_PD (1 << 11) 1006# define I2S_CONFIG_LB (1 << 10) 1007# define I2S_CONFIG_IC (1 << 9) 1008# define I2S_CONFIG_FM_BIT 7 1009# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1012# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1013# define I2S_CONFIG_TN (1 << 6) 1014# define I2S_CONFIG_RN (1 << 5) 1015# define I2S_CONFIG_SZ_BIT 0 1016# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1017 1018#define I2S_CONTROL 0xB1000008 1019# define I2S_CONTROL_D (1 << 1) 1020# define I2S_CONTROL_CE (1 << 0) 1021 1022/* USB Host Controller */ 1023#ifndef USB_OHCI_LEN 1024#define USB_OHCI_LEN 0x00100000 1025#endif 1026 1027#ifndef CONFIG_SOC_AU1200 1028 1029/* USB Device Controller */ 1030#define USBD_EP0RD 0xB0200000 1031#define USBD_EP0WR 0xB0200004 1032#define USBD_EP2WR 0xB0200008 1033#define USBD_EP3WR 0xB020000C 1034#define USBD_EP4RD 0xB0200010 1035#define USBD_EP5RD 0xB0200014 1036#define USBD_INTEN 0xB0200018 1037#define USBD_INTSTAT 0xB020001C 1038# define USBDEV_INT_SOF (1 << 12) 1039# define USBDEV_INT_HF_BIT 6 1040# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1041# define USBDEV_INT_CMPLT_BIT 0 1042# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1043#define USBD_CONFIG 0xB0200020 1044#define USBD_EP0CS 0xB0200024 1045#define USBD_EP2CS 0xB0200028 1046#define USBD_EP3CS 0xB020002C 1047#define USBD_EP4CS 0xB0200030 1048#define USBD_EP5CS 0xB0200034 1049# define USBDEV_CS_SU (1 << 14) 1050# define USBDEV_CS_NAK (1 << 13) 1051# define USBDEV_CS_ACK (1 << 12) 1052# define USBDEV_CS_BUSY (1 << 11) 1053# define USBDEV_CS_TSIZE_BIT 1 1054# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1055# define USBDEV_CS_STALL (1 << 0) 1056#define USBD_EP0RDSTAT 0xB0200040 1057#define USBD_EP0WRSTAT 0xB0200044 1058#define USBD_EP2WRSTAT 0xB0200048 1059#define USBD_EP3WRSTAT 0xB020004C 1060#define USBD_EP4RDSTAT 0xB0200050 1061#define USBD_EP5RDSTAT 0xB0200054 1062# define USBDEV_FSTAT_FLUSH (1 << 6) 1063# define USBDEV_FSTAT_UF (1 << 5) 1064# define USBDEV_FSTAT_OF (1 << 4) 1065# define USBDEV_FSTAT_FCNT_BIT 0 1066# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1067#define USBD_ENABLE 0xB0200058 1068# define USBDEV_ENABLE (1 << 1) 1069# define USBDEV_CE (1 << 0) 1070 1071#endif /* !CONFIG_SOC_AU1200 */ 1072 1073/* Ethernet Controllers */ 1074 1075/* 4 byte offsets from AU1000_ETH_BASE */ 1076#define MAC_CONTROL 0x0 1077# define MAC_RX_ENABLE (1 << 2) 1078# define MAC_TX_ENABLE (1 << 3) 1079# define MAC_DEF_CHECK (1 << 5) 1080# define MAC_SET_BL(X) (((X) & 0x3) << 6) 1081# define MAC_AUTO_PAD (1 << 8) 1082# define MAC_DISABLE_RETRY (1 << 10) 1083# define MAC_DISABLE_BCAST (1 << 11) 1084# define MAC_LATE_COL (1 << 12) 1085# define MAC_HASH_MODE (1 << 13) 1086# define MAC_HASH_ONLY (1 << 15) 1087# define MAC_PASS_ALL (1 << 16) 1088# define MAC_INVERSE_FILTER (1 << 17) 1089# define MAC_PROMISCUOUS (1 << 18) 1090# define MAC_PASS_ALL_MULTI (1 << 19) 1091# define MAC_FULL_DUPLEX (1 << 20) 1092# define MAC_NORMAL_MODE 0 1093# define MAC_INT_LOOPBACK (1 << 21) 1094# define MAC_EXT_LOOPBACK (1 << 22) 1095# define MAC_DISABLE_RX_OWN (1 << 23) 1096# define MAC_BIG_ENDIAN (1 << 30) 1097# define MAC_RX_ALL (1 << 31) 1098#define MAC_ADDRESS_HIGH 0x4 1099#define MAC_ADDRESS_LOW 0x8 1100#define MAC_MCAST_HIGH 0xC 1101#define MAC_MCAST_LOW 0x10 1102#define MAC_MII_CNTRL 0x14 1103# define MAC_MII_BUSY (1 << 0) 1104# define MAC_MII_READ 0 1105# define MAC_MII_WRITE (1 << 1) 1106# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 1107# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 1108#define MAC_MII_DATA 0x18 1109#define MAC_FLOW_CNTRL 0x1C 1110# define MAC_FLOW_CNTRL_BUSY (1 << 0) 1111# define MAC_FLOW_CNTRL_ENABLE (1 << 1) 1112# define MAC_PASS_CONTROL (1 << 2) 1113# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 1114#define MAC_VLAN1_TAG 0x20 1115#define MAC_VLAN2_TAG 0x24 1116 1117/* Ethernet Controller Enable */ 1118 1119# define MAC_EN_CLOCK_ENABLE (1 << 0) 1120# define MAC_EN_RESET0 (1 << 1) 1121# define MAC_EN_TOSS (0 << 2) 1122# define MAC_EN_CACHEABLE (1 << 3) 1123# define MAC_EN_RESET1 (1 << 4) 1124# define MAC_EN_RESET2 (1 << 5) 1125# define MAC_DMA_RESET (1 << 6) 1126 1127/* Ethernet Controller DMA Channels */ 1128 1129#define MAC0_TX_DMA_ADDR 0xB4004000 1130#define MAC1_TX_DMA_ADDR 0xB4004200 1131/* offsets from MAC_TX_RING_ADDR address */ 1132#define MAC_TX_BUFF0_STATUS 0x0 1133# define TX_FRAME_ABORTED (1 << 0) 1134# define TX_JAB_TIMEOUT (1 << 1) 1135# define TX_NO_CARRIER (1 << 2) 1136# define TX_LOSS_CARRIER (1 << 3) 1137# define TX_EXC_DEF (1 << 4) 1138# define TX_LATE_COLL_ABORT (1 << 5) 1139# define TX_EXC_COLL (1 << 6) 1140# define TX_UNDERRUN (1 << 7) 1141# define TX_DEFERRED (1 << 8) 1142# define TX_LATE_COLL (1 << 9) 1143# define TX_COLL_CNT_MASK (0xF << 10) 1144# define TX_PKT_RETRY (1 << 31) 1145#define MAC_TX_BUFF0_ADDR 0x4 1146# define TX_DMA_ENABLE (1 << 0) 1147# define TX_T_DONE (1 << 1) 1148# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 1149#define MAC_TX_BUFF0_LEN 0x8 1150#define MAC_TX_BUFF1_STATUS 0x10 1151#define MAC_TX_BUFF1_ADDR 0x14 1152#define MAC_TX_BUFF1_LEN 0x18 1153#define MAC_TX_BUFF2_STATUS 0x20 1154#define MAC_TX_BUFF2_ADDR 0x24 1155#define MAC_TX_BUFF2_LEN 0x28 1156#define MAC_TX_BUFF3_STATUS 0x30 1157#define MAC_TX_BUFF3_ADDR 0x34 1158#define MAC_TX_BUFF3_LEN 0x38 1159 1160#define MAC0_RX_DMA_ADDR 0xB4004100 1161#define MAC1_RX_DMA_ADDR 0xB4004300 1162/* offsets from MAC_RX_RING_ADDR */ 1163#define MAC_RX_BUFF0_STATUS 0x0 1164# define RX_FRAME_LEN_MASK 0x3fff 1165# define RX_WDOG_TIMER (1 << 14) 1166# define RX_RUNT (1 << 15) 1167# define RX_OVERLEN (1 << 16) 1168# define RX_COLL (1 << 17) 1169# define RX_ETHER (1 << 18) 1170# define RX_MII_ERROR (1 << 19) 1171# define RX_DRIBBLING (1 << 20) 1172# define RX_CRC_ERROR (1 << 21) 1173# define RX_VLAN1 (1 << 22) 1174# define RX_VLAN2 (1 << 23) 1175# define RX_LEN_ERROR (1 << 24) 1176# define RX_CNTRL_FRAME (1 << 25) 1177# define RX_U_CNTRL_FRAME (1 << 26) 1178# define RX_MCAST_FRAME (1 << 27) 1179# define RX_BCAST_FRAME (1 << 28) 1180# define RX_FILTER_FAIL (1 << 29) 1181# define RX_PACKET_FILTER (1 << 30) 1182# define RX_MISSED_FRAME (1 << 31) 1183 1184# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1185 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1186 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1187#define MAC_RX_BUFF0_ADDR 0x4 1188# define RX_DMA_ENABLE (1 << 0) 1189# define RX_T_DONE (1 << 1) 1190# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 1191# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 1192#define MAC_RX_BUFF1_STATUS 0x10 1193#define MAC_RX_BUFF1_ADDR 0x14 1194#define MAC_RX_BUFF2_STATUS 0x20 1195#define MAC_RX_BUFF2_ADDR 0x24 1196#define MAC_RX_BUFF3_STATUS 0x30 1197#define MAC_RX_BUFF3_ADDR 0x34 1198 1199/* UARTS 0-3 */ 1200#define UART_BASE UART0_ADDR 1201#ifdef CONFIG_SOC_AU1200 1202#define UART_DEBUG_BASE UART1_ADDR 1203#else 1204#define UART_DEBUG_BASE UART3_ADDR 1205#endif 1206 1207#define UART_RX 0 /* Receive buffer */ 1208#define UART_TX 4 /* Transmit buffer */ 1209#define UART_IER 8 /* Interrupt Enable Register */ 1210#define UART_IIR 0xC /* Interrupt ID Register */ 1211#define UART_FCR 0x10 /* FIFO Control Register */ 1212#define UART_LCR 0x14 /* Line Control Register */ 1213#define UART_MCR 0x18 /* Modem Control Register */ 1214#define UART_LSR 0x1C /* Line Status Register */ 1215#define UART_MSR 0x20 /* Modem Status Register */ 1216#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1217#define UART_MOD_CNTRL 0x100 /* Module Control */ 1218 1219#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 1220#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 1221#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 1222#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 1223#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ 1224#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ 1225#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ 1226#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ 1227#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ 1228#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ 1229#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ 1230#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ 1231#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ 1232 1233/* 1234 * These are the definitions for the Line Control Register 1235 */ 1236#define UART_LCR_SBC 0x40 /* Set break control */ 1237#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 1238#define UART_LCR_EPAR 0x10 /* Even parity select */ 1239#define UART_LCR_PARITY 0x08 /* Parity Enable */ 1240#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 1241#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 1242#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 1243#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 1244#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 1245 1246/* 1247 * These are the definitions for the Line Status Register 1248 */ 1249#define UART_LSR_TEMT 0x40 /* Transmitter empty */ 1250#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 1251#define UART_LSR_BI 0x10 /* Break interrupt indicator */ 1252#define UART_LSR_FE 0x08 /* Frame error indicator */ 1253#define UART_LSR_PE 0x04 /* Parity error indicator */ 1254#define UART_LSR_OE 0x02 /* Overrun error indicator */ 1255#define UART_LSR_DR 0x01 /* Receiver data ready */ 1256 1257/* 1258 * These are the definitions for the Interrupt Identification Register 1259 */ 1260#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 1261#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 1262#define UART_IIR_MSI 0x00 /* Modem status interrupt */ 1263#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 1264#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 1265#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 1266 1267/* 1268 * These are the definitions for the Interrupt Enable Register 1269 */ 1270#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 1271#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 1272#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 1273#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 1274 1275/* 1276 * These are the definitions for the Modem Control Register 1277 */ 1278#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 1279#define UART_MCR_OUT2 0x08 /* Out2 complement */ 1280#define UART_MCR_OUT1 0x04 /* Out1 complement */ 1281#define UART_MCR_RTS 0x02 /* RTS complement */ 1282#define UART_MCR_DTR 0x01 /* DTR complement */ 1283 1284/* 1285 * These are the definitions for the Modem Status Register 1286 */ 1287#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 1288#define UART_MSR_RI 0x40 /* Ring Indicator */ 1289#define UART_MSR_DSR 0x20 /* Data Set Ready */ 1290#define UART_MSR_CTS 0x10 /* Clear to Send */ 1291#define UART_MSR_DDCD 0x08 /* Delta DCD */ 1292#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 1293#define UART_MSR_DDSR 0x02 /* Delta DSR */ 1294#define UART_MSR_DCTS 0x01 /* Delta CTS */ 1295#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 1296 1297/* SSIO */ 1298#define SSI0_STATUS 0xB1600000 1299# define SSI_STATUS_BF (1 << 4) 1300# define SSI_STATUS_OF (1 << 3) 1301# define SSI_STATUS_UF (1 << 2) 1302# define SSI_STATUS_D (1 << 1) 1303# define SSI_STATUS_B (1 << 0) 1304#define SSI0_INT 0xB1600004 1305# define SSI_INT_OI (1 << 3) 1306# define SSI_INT_UI (1 << 2) 1307# define SSI_INT_DI (1 << 1) 1308#define SSI0_INT_ENABLE 0xB1600008 1309# define SSI_INTE_OIE (1 << 3) 1310# define SSI_INTE_UIE (1 << 2) 1311# define SSI_INTE_DIE (1 << 1) 1312#define SSI0_CONFIG 0xB1600020 1313# define SSI_CONFIG_AO (1 << 24) 1314# define SSI_CONFIG_DO (1 << 23) 1315# define SSI_CONFIG_ALEN_BIT 20 1316# define SSI_CONFIG_ALEN_MASK (0x7 << 20) 1317# define SSI_CONFIG_DLEN_BIT 16 1318# define SSI_CONFIG_DLEN_MASK (0x7 << 16) 1319# define SSI_CONFIG_DD (1 << 11) 1320# define SSI_CONFIG_AD (1 << 10) 1321# define SSI_CONFIG_BM_BIT 8 1322# define SSI_CONFIG_BM_MASK (0x3 << 8) 1323# define SSI_CONFIG_CE (1 << 7) 1324# define SSI_CONFIG_DP (1 << 6) 1325# define SSI_CONFIG_DL (1 << 5) 1326# define SSI_CONFIG_EP (1 << 4) 1327#define SSI0_ADATA 0xB1600024 1328# define SSI_AD_D (1 << 24) 1329# define SSI_AD_ADDR_BIT 16 1330# define SSI_AD_ADDR_MASK (0xff << 16) 1331# define SSI_AD_DATA_BIT 0 1332# define SSI_AD_DATA_MASK (0xfff << 0) 1333#define SSI0_CLKDIV 0xB1600028 1334#define SSI0_CONTROL 0xB1600100 1335# define SSI_CONTROL_CD (1 << 1) 1336# define SSI_CONTROL_E (1 << 0) 1337 1338/* SSI1 */ 1339#define SSI1_STATUS 0xB1680000 1340#define SSI1_INT 0xB1680004 1341#define SSI1_INT_ENABLE 0xB1680008 1342#define SSI1_CONFIG 0xB1680020 1343#define SSI1_ADATA 0xB1680024 1344#define SSI1_CLKDIV 0xB1680028 1345#define SSI1_ENABLE 0xB1680100 1346 1347/* 1348 * Register content definitions 1349 */ 1350#define SSI_STATUS_BF (1 << 4) 1351#define SSI_STATUS_OF (1 << 3) 1352#define SSI_STATUS_UF (1 << 2) 1353#define SSI_STATUS_D (1 << 1) 1354#define SSI_STATUS_B (1 << 0) 1355 1356/* SSI_INT */ 1357#define SSI_INT_OI (1 << 3) 1358#define SSI_INT_UI (1 << 2) 1359#define SSI_INT_DI (1 << 1) 1360 1361/* SSI_INTEN */ 1362#define SSI_INTEN_OIE (1 << 3) 1363#define SSI_INTEN_UIE (1 << 2) 1364#define SSI_INTEN_DIE (1 << 1) 1365 1366#define SSI_CONFIG_AO (1 << 24) 1367#define SSI_CONFIG_DO (1 << 23) 1368#define SSI_CONFIG_ALEN (7 << 20) 1369#define SSI_CONFIG_DLEN (15 << 16) 1370#define SSI_CONFIG_DD (1 << 11) 1371#define SSI_CONFIG_AD (1 << 10) 1372#define SSI_CONFIG_BM (3 << 8) 1373#define SSI_CONFIG_CE (1 << 7) 1374#define SSI_CONFIG_DP (1 << 6) 1375#define SSI_CONFIG_DL (1 << 5) 1376#define SSI_CONFIG_EP (1 << 4) 1377#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) 1378#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) 1379#define SSI_CONFIG_BM_HI (0 << 8) 1380#define SSI_CONFIG_BM_LO (1 << 8) 1381#define SSI_CONFIG_BM_CY (2 << 8) 1382 1383#define SSI_ADATA_D (1 << 24) 1384#define SSI_ADATA_ADDR (0xFF << 16) 1385#define SSI_ADATA_DATA 0x0FFF 1386#define SSI_ADATA_ADDR_N(N) (N << 16) 1387 1388#define SSI_ENABLE_CD (1 << 1) 1389#define SSI_ENABLE_E (1 << 0) 1390 1391/* IrDA Controller */ 1392#define IRDA_BASE 0xB0300000 1393#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1394#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1395#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1396#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1397#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1398#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1399#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1400#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1401# define IR_RX_INVERT_LED (1 << 0) 1402# define IR_TX_INVERT_LED (1 << 1) 1403# define IR_ST (1 << 2) 1404# define IR_SF (1 << 3) 1405# define IR_SIR (1 << 4) 1406# define IR_MIR (1 << 5) 1407# define IR_FIR (1 << 6) 1408# define IR_16CRC (1 << 7) 1409# define IR_TD (1 << 8) 1410# define IR_RX_ALL (1 << 9) 1411# define IR_DMA_ENABLE (1 << 10) 1412# define IR_RX_ENABLE (1 << 11) 1413# define IR_TX_ENABLE (1 << 12) 1414# define IR_LOOPBACK (1 << 14) 1415# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1416 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1417#define IR_SIR_FLAGS (IRDA_BASE + 0x24) 1418#define IR_ENABLE (IRDA_BASE + 0x28) 1419# define IR_RX_STATUS (1 << 9) 1420# define IR_TX_STATUS (1 << 10) 1421#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) 1422#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) 1423#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) 1424#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) 1425#define IR_CONFIG_2 (IRDA_BASE + 0x3C) 1426# define IR_MODE_INV (1 << 0) 1427# define IR_ONE_PIN (1 << 1) 1428#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) 1429 1430/* GPIO */ 1431#define SYS_PINFUNC 0xB190002C 1432# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ 1433# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ 1434# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ 1435# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ 1436# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ 1437# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ 1438# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ 1439# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ 1440# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ 1441# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ 1442# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ 1443# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ 1444# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ 1445# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ 1446# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ 1447# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ 1448 1449/* Au1100 only */ 1450# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ 1451# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ 1452# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ 1453# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ 1454 1455/* Au1550 only. Redefines lots of pins */ 1456# define SYS_PF_PSC2_MASK (7 << 17) 1457# define SYS_PF_PSC2_AC97 0 1458# define SYS_PF_PSC2_SPI 0 1459# define SYS_PF_PSC2_I2S (1 << 17) 1460# define SYS_PF_PSC2_SMBUS (3 << 17) 1461# define SYS_PF_PSC2_GPIO (7 << 17) 1462# define SYS_PF_PSC3_MASK (7 << 20) 1463# define SYS_PF_PSC3_AC97 0 1464# define SYS_PF_PSC3_SPI 0 1465# define SYS_PF_PSC3_I2S (1 << 20) 1466# define SYS_PF_PSC3_SMBUS (3 << 20) 1467# define SYS_PF_PSC3_GPIO (7 << 20) 1468# define SYS_PF_PSC1_S1 (1 << 1) 1469# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1470 1471/* Au1200 only */ 1472#ifdef CONFIG_SOC_AU1200 1473#define SYS_PINFUNC_DMA (1 << 31) 1474#define SYS_PINFUNC_S0A (1 << 30) 1475#define SYS_PINFUNC_S1A (1 << 29) 1476#define SYS_PINFUNC_LP0 (1 << 28) 1477#define SYS_PINFUNC_LP1 (1 << 27) 1478#define SYS_PINFUNC_LD16 (1 << 26) 1479#define SYS_PINFUNC_LD8 (1 << 25) 1480#define SYS_PINFUNC_LD1 (1 << 24) 1481#define SYS_PINFUNC_LD0 (1 << 23) 1482#define SYS_PINFUNC_P1A (3 << 21) 1483#define SYS_PINFUNC_P1B (1 << 20) 1484#define SYS_PINFUNC_FS3 (1 << 19) 1485#define SYS_PINFUNC_P0A (3 << 17) 1486#define SYS_PINFUNC_CS (1 << 16) 1487#define SYS_PINFUNC_CIM (1 << 15) 1488#define SYS_PINFUNC_P1C (1 << 14) 1489#define SYS_PINFUNC_U1T (1 << 12) 1490#define SYS_PINFUNC_U1R (1 << 11) 1491#define SYS_PINFUNC_EX1 (1 << 10) 1492#define SYS_PINFUNC_EX0 (1 << 9) 1493#define SYS_PINFUNC_U0R (1 << 8) 1494#define SYS_PINFUNC_MC (1 << 7) 1495#define SYS_PINFUNC_S0B (1 << 6) 1496#define SYS_PINFUNC_S0C (1 << 5) 1497#define SYS_PINFUNC_P0B (1 << 4) 1498#define SYS_PINFUNC_U0T (1 << 3) 1499#define SYS_PINFUNC_S1B (1 << 2) 1500#endif 1501 1502#define SYS_TRIOUTRD 0xB1900100 1503#define SYS_TRIOUTCLR 0xB1900100 1504#define SYS_OUTPUTRD 0xB1900108 1505#define SYS_OUTPUTSET 0xB1900108 1506#define SYS_OUTPUTCLR 0xB190010C 1507#define SYS_PINSTATERD 0xB1900110 1508#define SYS_PININPUTEN 0xB1900110 1509 1510/* GPIO2, Au1500, Au1550 only */ 1511#define GPIO2_BASE 0xB1700000 1512#define GPIO2_DIR (GPIO2_BASE + 0) 1513#define GPIO2_OUTPUT (GPIO2_BASE + 8) 1514#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 1515#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 1516#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 1517 1518/* Power Management */ 1519#define SYS_SCRATCH0 0xB1900018 1520#define SYS_SCRATCH1 0xB190001C 1521#define SYS_WAKEMSK 0xB1900034 1522#define SYS_ENDIAN 0xB1900038 1523#define SYS_POWERCTRL 0xB190003C 1524#define SYS_WAKESRC 0xB190005C 1525#define SYS_SLPPWR 0xB1900078 1526#define SYS_SLEEP 0xB190007C 1527 1528/* Clock Controller */ 1529#define SYS_FREQCTRL0 0xB1900020 1530# define SYS_FC_FRDIV2_BIT 22 1531# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1532# define SYS_FC_FE2 (1 << 21) 1533# define SYS_FC_FS2 (1 << 20) 1534# define SYS_FC_FRDIV1_BIT 12 1535# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1536# define SYS_FC_FE1 (1 << 11) 1537# define SYS_FC_FS1 (1 << 10) 1538# define SYS_FC_FRDIV0_BIT 2 1539# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1540# define SYS_FC_FE0 (1 << 1) 1541# define SYS_FC_FS0 (1 << 0) 1542#define SYS_FREQCTRL1 0xB1900024 1543# define SYS_FC_FRDIV5_BIT 22 1544# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1545# define SYS_FC_FE5 (1 << 21) 1546# define SYS_FC_FS5 (1 << 20) 1547# define SYS_FC_FRDIV4_BIT 12 1548# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1549# define SYS_FC_FE4 (1 << 11) 1550# define SYS_FC_FS4 (1 << 10) 1551# define SYS_FC_FRDIV3_BIT 2 1552# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1553# define SYS_FC_FE3 (1 << 1) 1554# define SYS_FC_FS3 (1 << 0) 1555#define SYS_CLKSRC 0xB1900028 1556# define SYS_CS_ME1_BIT 27 1557# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) 1558# define SYS_CS_DE1 (1 << 26) 1559# define SYS_CS_CE1 (1 << 25) 1560# define SYS_CS_ME0_BIT 22 1561# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) 1562# define SYS_CS_DE0 (1 << 21) 1563# define SYS_CS_CE0 (1 << 20) 1564# define SYS_CS_MI2_BIT 17 1565# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 1566# define SYS_CS_DI2 (1 << 16) 1567# define SYS_CS_CI2 (1 << 15) 1568#ifdef CONFIG_SOC_AU1100 1569# define SYS_CS_ML_BIT 7 1570# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) 1571# define SYS_CS_DL (1 << 6) 1572# define SYS_CS_CL (1 << 5) 1573#else 1574# define SYS_CS_MUH_BIT 12 1575# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 1576# define SYS_CS_DUH (1 << 11) 1577# define SYS_CS_CUH (1 << 10) 1578# define SYS_CS_MUD_BIT 7 1579# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 1580# define SYS_CS_DUD (1 << 6) 1581# define SYS_CS_CUD (1 << 5) 1582#endif 1583# define SYS_CS_MIR_BIT 2 1584# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 1585# define SYS_CS_DIR (1 << 1) 1586# define SYS_CS_CIR (1 << 0) 1587 1588# define SYS_CS_MUX_AUX 0x1 1589# define SYS_CS_MUX_FQ0 0x2 1590# define SYS_CS_MUX_FQ1 0x3 1591# define SYS_CS_MUX_FQ2 0x4 1592# define SYS_CS_MUX_FQ3 0x5 1593# define SYS_CS_MUX_FQ4 0x6 1594# define SYS_CS_MUX_FQ5 0x7 1595#define SYS_CPUPLL 0xB1900060 1596#define SYS_AUXPLL 0xB1900064 1597 1598/* AC97 Controller */ 1599#define AC97C_CONFIG 0xB0000000 1600# define AC97C_RECV_SLOTS_BIT 13 1601# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1602# define AC97C_XMIT_SLOTS_BIT 3 1603# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1604# define AC97C_SG (1 << 2) 1605# define AC97C_SYNC (1 << 1) 1606# define AC97C_RESET (1 << 0) 1607#define AC97C_STATUS 0xB0000004 1608# define AC97C_XU (1 << 11) 1609# define AC97C_XO (1 << 10) 1610# define AC97C_RU (1 << 9) 1611# define AC97C_RO (1 << 8) 1612# define AC97C_READY (1 << 7) 1613# define AC97C_CP (1 << 6) 1614# define AC97C_TR (1 << 5) 1615# define AC97C_TE (1 << 4) 1616# define AC97C_TF (1 << 3) 1617# define AC97C_RR (1 << 2) 1618# define AC97C_RE (1 << 1) 1619# define AC97C_RF (1 << 0) 1620#define AC97C_DATA 0xB0000008 1621#define AC97C_CMD 0xB000000C 1622# define AC97C_WD_BIT 16 1623# define AC97C_READ (1 << 7) 1624# define AC97C_INDEX_MASK 0x7f 1625#define AC97C_CNTRL 0xB0000010 1626# define AC97C_RS (1 << 1) 1627# define AC97C_CE (1 << 0) 1628 1629/* Secure Digital (SD) Controller */ 1630#define SD0_XMIT_FIFO 0xB0600000 1631#define SD0_RECV_FIFO 0xB0600004 1632#define SD1_XMIT_FIFO 0xB0680000 1633#define SD1_RECV_FIFO 0xB0680004 1634 1635#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1636/* Au1500 PCI Controller */ 1637#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ 1638#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1639#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1640# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ 1641 (1 << 25) | (1 << 26) | (1 << 27)) 1642#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1643#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1644#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1645#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1646#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1647#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1648#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1649#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1650#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1651#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1652#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1653#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1654 1655#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ 1656 1657/* 1658 * All of our structures, like PCI resource, have 32-bit members. 1659 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1660 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch 1661 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1662 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM 1663 * addresses. For PCI I/O, it's simpler because we get to do the ioremap 1664 * ourselves and then adjust the device's resources. 1665 */ 1666#define Au1500_EXT_CFG 0x600000000ULL 1667#define Au1500_EXT_CFG_TYPE1 0x680000000ULL 1668#define Au1500_PCI_IO_START 0x500000000ULL 1669#define Au1500_PCI_IO_END 0x5000FFFFFULL 1670#define Au1500_PCI_MEM_START 0x440000000ULL 1671#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1672 1673#define PCI_IO_START 0x00001000 1674#define PCI_IO_END 0x000FFFFF 1675#define PCI_MEM_START 0x40000000 1676#define PCI_MEM_END 0x4FFFFFFF 1677 1678#define PCI_FIRST_DEVFN (0 << 3) 1679#define PCI_LAST_DEVFN (19 << 3) 1680 1681#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1682#define IOPORT_RESOURCE_END 0xffffffff 1683#define IOMEM_RESOURCE_START 0x10000000 1684#define IOMEM_RESOURCE_END 0xffffffff 1685 1686#else /* Au1000 and Au1100 and Au1200 */ 1687 1688/* Don't allow any legacy ports probing */ 1689#define IOPORT_RESOURCE_START 0x10000000 1690#define IOPORT_RESOURCE_END 0xffffffff 1691#define IOMEM_RESOURCE_START 0x10000000 1692#define IOMEM_RESOURCE_END 0xffffffff 1693 1694#define PCI_IO_START 0 1695#define PCI_IO_END 0 1696#define PCI_MEM_START 0 1697#define PCI_MEM_END 0 1698#define PCI_FIRST_DEVFN 0 1699#define PCI_LAST_DEVFN 0 1700 1701#endif 1702 1703#ifndef _LANGUAGE_ASSEMBLY 1704typedef volatile struct { 1705 /* 0x0000 */ u32 toytrim; 1706 /* 0x0004 */ u32 toywrite; 1707 /* 0x0008 */ u32 toymatch0; 1708 /* 0x000C */ u32 toymatch1; 1709 /* 0x0010 */ u32 toymatch2; 1710 /* 0x0014 */ u32 cntrctrl; 1711 /* 0x0018 */ u32 scratch0; 1712 /* 0x001C */ u32 scratch1; 1713 /* 0x0020 */ u32 freqctrl0; 1714 /* 0x0024 */ u32 freqctrl1; 1715 /* 0x0028 */ u32 clksrc; 1716 /* 0x002C */ u32 pinfunc; 1717 /* 0x0030 */ u32 reserved0; 1718 /* 0x0034 */ u32 wakemsk; 1719 /* 0x0038 */ u32 endian; 1720 /* 0x003C */ u32 powerctrl; 1721 /* 0x0040 */ u32 toyread; 1722 /* 0x0044 */ u32 rtctrim; 1723 /* 0x0048 */ u32 rtcwrite; 1724 /* 0x004C */ u32 rtcmatch0; 1725 /* 0x0050 */ u32 rtcmatch1; 1726 /* 0x0054 */ u32 rtcmatch2; 1727 /* 0x0058 */ u32 rtcread; 1728 /* 0x005C */ u32 wakesrc; 1729 /* 0x0060 */ u32 cpupll; 1730 /* 0x0064 */ u32 auxpll; 1731 /* 0x0068 */ u32 reserved1; 1732 /* 0x006C */ u32 reserved2; 1733 /* 0x0070 */ u32 reserved3; 1734 /* 0x0074 */ u32 reserved4; 1735 /* 0x0078 */ u32 slppwr; 1736 /* 0x007C */ u32 sleep; 1737 /* 0x0080 */ u32 reserved5[32]; 1738 /* 0x0100 */ u32 trioutrd; 1739#define trioutclr trioutrd 1740 /* 0x0104 */ u32 reserved6; 1741 /* 0x0108 */ u32 outputrd; 1742#define outputset outputrd 1743 /* 0x010C */ u32 outputclr; 1744 /* 0x0110 */ u32 pinstaterd; 1745#define pininputen pinstaterd 1746} AU1X00_SYS; 1747 1748static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; 1749 1750#endif 1751 1752/* 1753 * Processor information based on PRID. 1754 * Copied from PowerPC. 1755 */ 1756#ifndef _LANGUAGE_ASSEMBLY 1757struct cpu_spec { 1758 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1759 unsigned int prid_mask; 1760 unsigned int prid_value; 1761 1762 char *cpu_name; 1763 unsigned char cpu_od; /* Set Config[OD] */ 1764 unsigned char cpu_bclk; /* Enable BCLK switching */ 1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ 1766}; 1767 1768extern struct cpu_spec cpu_specs[]; 1769extern struct cpu_spec *cur_cpu_spec[]; 1770#endif 1771 1772#endif 1773