1bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// The LLVM Compiler Infrastructure 494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// This file is distributed under the University of Illinois Open Source 694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// License. See LICENSE.TXT for details. 794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 10bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// This implements the Emit routines for the SelectionDAG class, which creates 11bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// MachineInstrs based on the decisions of the SelectionDAG instruction 12bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// selection. 1394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 1494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 1594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#define DEBUG_TYPE "instr-emitter" 17bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#include "InstrEmitter.h" 18a8efe28a44996978faa42a387f1a6087a7b942c7Evan Cheng#include "SDNodeDbgValue.h" 1994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineConstantPool.h" 2094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineFunction.h" 2194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineInstrBuilder.h" 2294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 2394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetData.h" 2494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetMachine.h" 2594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetInstrInfo.h" 2694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetLowering.h" 2794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/ADT/Statistic.h" 2894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/Debug.h" 29c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/MathExtras.h" 3194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohmanusing namespace llvm; 3294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 33d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// MinRCSize - Smallest register class we allow when constraining virtual 34d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// registers. If satisfying all register class constraints would require 35d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// using a smaller register class, emit a COPY to a new virtual register 36d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// instead. 37d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesenconst unsigned MinRCSize = 4; 38d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 39bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountResults - The results of target nodes have register or immediate 4029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// operands first, then an optional chain, and optional glue operands (which do 41bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// not go into the resulting MachineInstr). 42bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountResults(SDNode *Node) { 43bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumValues(); 44f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getValueType(N - 1) == MVT::Glue) 45bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 46bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getValueType(N - 1) == MVT::Other) 47bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Skip over chain result. 48bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 49bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 50bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 5133a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen/// countOperands - The inputs to target nodes have any actual inputs first, 5229d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// followed by an optional chain operand, then an optional glue operand. 53bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// Compute the number of actual operands that will go into the resulting 54bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// MachineInstr. 5533a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen/// 5633a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 5733a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen/// the chain and glue. These operands may be implicit on the machine instr. 58baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesenstatic unsigned countOperands(SDNode *Node, unsigned NumExpUses, 59baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesen unsigned &NumImpUses) { 60bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumOperands(); 61f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 62bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 63bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 64bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Ignore chain if it exists. 6533a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen 6633a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 67baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesen NumImpUses = N - NumExpUses; 68baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesen for (unsigned I = N; I > NumExpUses; --I) { 6933a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 7033a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen continue; 7133a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 7233a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 7333a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen continue; 7433a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen NumImpUses = N - I; 7533a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen break; 7633a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen } 7733a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen 78bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 79bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 80bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 8194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 8294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// implicit physical register output. 83bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter:: 845202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris LattnerEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 855202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris Lattner unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 8694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 8794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 8894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Just use the input register directly! 8994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 9094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 9194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 9294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 938e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 9494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 9594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return; 9694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 9794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 9894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 9994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 10094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool MatchReg = true; 1011cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng const TargetRegisterClass *UseRC = NULL; 102c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen EVT VT = Node->getValueType(ResNo); 103c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 104c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen // Stick to the preferred register classes for legal types. 105c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen if (TLI->isTypeLegal(VT)) 106c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen UseRC = TLI->getRegClassFor(VT); 107c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 108e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!IsClone && !IsCloned) 109e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 110e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 111e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 112e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool Match = true; 1133af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 114e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 115e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == ResNo) { 116e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 117e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 118e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng VRBase = DestReg; 119e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 120e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else if (DestReg != SrcReg) 121e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 122e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else { 123e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 124e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDValue Op = User->getOperand(i); 125e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (Op.getNode() != Node || Op.getResNo() != ResNo) 126e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 127e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(Op.getResNo()); 128f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (VT == MVT::Other || VT == MVT::Glue) 129e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 130e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 131e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->isMachineOpcode()) { 132e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 1332a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = 0; 134f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (i+II.getNumDefs() < II.getNumOperands()) { 135f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick RC = TRI->getAllocatableClass( 136397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 137f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick } 138e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!UseRC) 139e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UseRC = RC; 140f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman else if (RC) { 141e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *ComRC = 142e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen TRI->getCommonSubClass(UseRC, RC); 143f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // If multiple uses expect disjoint register classes, we emit 144f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // copies in AddRegisterOperand. 145f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen if (ComRC) 146f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen UseRC = ComRC; 147f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 148e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 1491cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } 15094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 151e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng MatchReg &= Match; 152e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (VRBase) 153e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng break; 15494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 15594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 15694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 157d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 158c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 15994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 16094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase) { 161bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstRC = MRI->getRegClass(VRBase); 1621cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } else if (UseRC) { 1631cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1641cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = UseRC; 16594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 1661cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = TLI->getRegClassFor(VT); 16794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 1683af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 16994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If all uses are reading from the src physical register and copying the 17094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // register is either impossible or very expensive, then don't create a copy. 17194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (MatchReg && SrcRC->getCopyCost() < 0) { 17294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = SrcReg; 17394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 17494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg, emit the copy. 175bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(DstRC); 17692c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 17792c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen VRBase).addReg(SrcReg); 17894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 17994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 18094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 18194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 18294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 18394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 1848e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 18594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 18694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 18794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 18894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getDstOfCopyToRegUse - If the only use of the specified result number of 18994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// node is a CopyToReg, return its destination register. Return 0 otherwise. 190bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 191bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned ResNo) const { 19294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!Node->hasOneUse()) 19394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 19494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 19594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *Node->use_begin(); 1963af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 19794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node && 19894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getResNo() == ResNo) { 19994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 20094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(Reg)) 20194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return Reg; 20294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 20394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 20494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 20594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 206bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 207e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II, 208e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool IsClone, bool IsCloned, 2095c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 210518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 21194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 21294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 21394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (unsigned i = 0; i < II.getNumDefs(); ++i) { 21494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the specific node value is only used by a CopyToReg and the dest reg 215f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // is a vreg in the same register class, use the CopyToReg'd destination 216f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // register instead of creating a new vreg. 21794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 218f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass *RC = 219397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 2208955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (II.OpInfo[i].isOptionalDef()) { 2218955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng // Optional def must be a physical register. 2228955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng unsigned NumResults = CountResults(Node); 2238955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 2248955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 2258955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 2268955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng } 227e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng 2288955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (!VRBase && !IsClone && !IsCloned) 229e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 230e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 231e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 2323af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 233e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 234e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == i) { 235e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 236e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(Reg)) { 237bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 238f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (RegRC == RC) { 239f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VRBase = Reg; 240f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 241f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman break; 242f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 243e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 24494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 24594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 24694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 24794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the result registers for this node and add the result regs to 24894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the machine instruction. 24994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase == 0) { 25094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(RC && "Isn't a register operand!"); 251bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(RC); 25294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 25394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 25494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, i); 2565c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng if (IsClone) 2575c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng VRBaseMap.erase(Op); 25894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 2598e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 26094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 26194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 26294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 26394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 26494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getVR - Return the virtual register corresponding to the specified result 26594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// of the specified node. 266bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getVR(SDValue Op, 267bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 26894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode() && 269518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 27094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add an IMPLICIT_DEF instruction before every use. 27194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 272e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 27394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // does not include operand register class info. 27494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!VReg) { 27594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 276bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VReg = MRI->createVirtualRegister(RC); 27794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 2783cd26a2909cd5d002fe2742041a264ba217ba88eDan Gohman BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 279518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 28094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return VReg; 28194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 28294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 28394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 28494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 28594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return I->second; 28694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 28794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 288c040719a153df8202f10054f33c9ac581b1c6c57Bill Wendling 289f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// AddRegisterOperand - Add the specified register as an operand to the 290f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// specified machine instr. Insert register copies if the register is 291f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// not in the required register class. 292f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 293bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 294bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 295e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 296bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 2978b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 298825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 299f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 30029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 301f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Get/emit the operand. 302f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Op, VRBaseMap); 303f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 304f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 305e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 306e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptDef = IIOpNum < MCID.getNumOperands() && 307e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCID.OpInfo[IIOpNum].isOptionalDef(); 308f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 309f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // If the instruction requires a register in a different class, create 31008f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // a new virtual register and copy the value into it, but first attempt to 31108f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // shrink VReg's register class within reason. For example, if VReg == GR32 31208f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 313f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (II) { 3142a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *DstRC = 0; 3152a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (IIOpNum < II->getNumOperands()) 316397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 3175a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) && 318f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Don't have operand info for this instruction!"); 31908f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 320bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 32192c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 32292c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 323f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VReg = NewVReg; 324f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 325f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 326f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 32747bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman // If this value has only one use, that use is a kill. This is a 3289d7019f586719a03f3519142ca2166166962e433Dan Gohman // conservative approximation. InstrEmitter does trivial coalescing 3299d7019f586719a03f3519142ca2166166962e433Dan Gohman // with CopyFromReg nodes, so don't emit kill flags for them. 3308b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // Avoid kill flags on Schedule cloned nodes, since there will be 3318b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // multiple uses. 3329d7019f586719a03f3519142ca2166166962e433Dan Gohman // Tied operands are never killed, so we need to check that. And that 3339d7019f586719a03f3519142ca2166166962e433Dan Gohman // means we need to determine the index of the operand. 3349d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isKill = Op.hasOneUse() && 3359d7019f586719a03f3519142ca2166166962e433Dan Gohman Op.getNode()->getOpcode() != ISD::CopyFromReg && 3368b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !IsDebug && 3378b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !(IsClone || IsCloned); 3389d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isKill) { 3399d7019f586719a03f3519142ca2166166962e433Dan Gohman unsigned Idx = MI->getNumOperands(); 3409d7019f586719a03f3519142ca2166166962e433Dan Gohman while (Idx > 0 && 3419d7019f586719a03f3519142ca2166166962e433Dan Gohman MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3429d7019f586719a03f3519142ca2166166962e433Dan Gohman --Idx; 343e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 3449d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isTied) 3459d7019f586719a03f3519142ca2166166962e433Dan Gohman isKill = false; 3469d7019f586719a03f3519142ca2166166962e433Dan Gohman } 34747bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman 348bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 34947bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman false/*isImp*/, isKill, 350bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isDead*/, false/*isUndef*/, 351bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isEarlyClobber*/, 352bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 0/*SubReg*/, IsDebug)); 353f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 354f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 35594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// AddOperand - Add the specified operand to the specified machine instr. II 35694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// specifies the instruction information for the node, and IIOpNum is the 35733a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen/// operand number (in the II) that we are adding. 358bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 359bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 360e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 361bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 3628b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 36394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode()) { 3648b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3658b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 36694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 367d842962e27b10b6831c2421fa257e3fd58a85b18Chris Lattner MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 36894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3694fbd796a1251a27e6590765a0a34876f436a0af9Dan Gohman const ConstantFP *CFP = F->getConstantFPValue(); 37094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFPImm(CFP)); 37194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 37233a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen // Turn additional physreg operands into implicit uses on non-variadic 37333a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen // instructions. This is used by call and return instructions passing 37433a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen // arguments in registers. 37533a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 37633a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp)); 3779cf37e8b48732fccd4c301ed51aafed7074bd84eJakob Stoklund Olesen } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 3789cf37e8b48732fccd4c301ed51aafed7074bd84eJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask())); 37994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3806ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3816ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner TGA->getTargetFlags())); 382f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 383f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 38494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 38594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 38694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3876ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3886ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner JT->getTargetFlags())); 38994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 39094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman int Offset = CP->getOffset(); 39194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Align = CP->getAlignment(); 392db125cfaf57cc83e7dd7453de2d509bc8efd0e5eChris Lattner Type *Type = CP->getType(); 39394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // MachineConstantPool wants an explicit alignment. 39494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 395bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getPrefTypeAlignment(Type); 39694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 39794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Alignment of vector types. FIXME! 398bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getTypeAllocSize(Type); 39994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 40094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4013af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 40294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Idx; 403bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineConstantPool *MCP = MF->getConstantPool(); 40494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (CP->isMachineConstantPoolEntry()) 405bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 40694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 407bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 4086ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 4096ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner CP->getTargetFlags())); 410056292fd738924f3f7703725d8f630983794b5a5Bill Wendling } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 41131e2c7b4c13c2f31774614b1124533628958d0cdDaniel Dunbar MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 4126ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner ES->getTargetFlags())); 4138c2b52552c90f39e4b2fed43e309e599e742b6acDan Gohman } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 41429cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 41529cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman BA->getTargetFlags())); 41674500bdba3eae36a1a8a17d8bad0b971b9c212ecJakob Stoklund Olesen } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 41774500bdba3eae36a1a8a17d8bad0b971b9c212ecJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateTargetIndex(TI->getIndex(), 41874500bdba3eae36a1a8a17d8bad0b971b9c212ecJakob Stoklund Olesen TI->getOffset(), 41974500bdba3eae36a1a8a17d8bad0b971b9c212ecJakob Stoklund Olesen TI->getTargetFlags())); 42094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 421825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 422f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 42329d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 4248b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 4258b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 426f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 427f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 428f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 429d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesenunsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 430d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen EVT VT, DebugLoc DL) { 431d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 432d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 433d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 434d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 435d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // within reason. 436d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (RC && RC != VRC) 437d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 438d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 439d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg has been adjusted. It can be used with SubIdx operands now. 440d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (RC) 441d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen return VReg; 442d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 443d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 444d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // register instead. 445d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 446d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen assert(RC && "No legal register class for VT supports that SubIdx"); 447d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen unsigned NewReg = MRI->createVirtualRegister(RC); 448d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 449d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen .addReg(VReg); 450d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen return NewReg; 451d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen} 452d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 45394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitSubregNode - Generate machine code for subreg nodes. 45494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 4553af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trickvoid InstrEmitter::EmitSubregNode(SDNode *Node, 4568b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 4578b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 45894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 45994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Opc = Node->getMachineOpcode(); 4603af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 46194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 46294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 46394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 46494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman UI != E; ++UI) { 46594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *UI; 4663af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 46794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node) { 46894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 46994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 47094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = DestReg; 47194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 47294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 47394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 47494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4753af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 476518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG) { 477d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 478d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // constraints on the %dst register, COPY can target all legal register 479d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // classes. 480f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 481d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); 48294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 483f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 4840b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MachineInstr *DefMI = MRI->getVRegDef(VReg); 4850b71d3972d9138c7482233bc44a9a207634769efEvan Cheng unsigned SrcReg, DstReg, DefSubIdx; 4860b71d3972d9138c7482233bc44a9a207634769efEvan Cheng if (DefMI && 4870b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 488875913439ca8f073852ec8315d3b32b875184582Evan Cheng SubIdx == DefSubIdx && 489875913439ca8f073852ec8315d3b32b875184582Evan Cheng TRC == MRI->getRegClass(SrcReg)) { 4900b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Optimize these: 4910b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1025 = s/zext r1024, 4 4920b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = extract_subreg r1025, 4 4930b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // to a copy 4940b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = copy r1024 4950b71d3972d9138c7482233bc44a9a207634769efEvan Cheng VRBase = MRI->createVirtualRegister(TRC); 4960b71d3972d9138c7482233bc44a9a207634769efEvan Cheng BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 4970b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 4988ccaad526abdf39141b11b6d480b027d73a2d2a8Jakob Stoklund Olesen MRI->clearKillFlags(SrcReg); 4990b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } else { 500d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg may not support a SubIdx sub-register, and we may need to 501d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // constrain its register class or issue a COPY to a compatible register 502d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // class. 503d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen VReg = ConstrainForSubReg(VReg, SubIdx, 504d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen Node->getOperand(0).getValueType(), 505d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen Node->getDebugLoc()); 506d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 507d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // Create the destreg if it is missing. 508d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (VRBase == 0) 509d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen VRBase = MRI->createVirtualRegister(TRC); 5105ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 5110b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Create the extract_subreg machine instruction. 512d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 513d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 5140b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } 515518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner } else if (Opc == TargetOpcode::INSERT_SUBREG || 516518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 51794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N0 = Node->getOperand(0); 51894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N1 = Node->getOperand(1); 51994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N2 = Node->getOperand(2); 520f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 5215ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 5222c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // Figure out the register class to create for the destreg. It should be 5232c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // the largest legal register class supporting SubIdx sub-registers. 5242c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // RegisterCoalescer will constrain it further if it decides to eliminate 5252c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // the INSERT_SUBREG instruction. 5262c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5272c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst = INSERT_SUBREG %src, %sub, SubIdx 5282c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5292c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // is lowered by TwoAddressInstructionPass to: 5302c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5312c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst = COPY %src 5322c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst:SubIdx = COPY %sub 5332c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5342c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // There is no constraint on the %src register class. 5352c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5362c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); 5372c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 5382c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 5392c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen 5402c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 541bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 5425ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 54394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the insert_subreg or subreg_to_reg machine instruction. 544bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 54594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 5463af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 54794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If creating a subreg_to_reg, then the first input operand 54894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // is an implicit value immediate, otherwise it's a register 549518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::SUBREG_TO_REG) { 55094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 551f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 55294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 5538b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 5548b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 55594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the subregster being inserted 5568b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 5578b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 55894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 559bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 56094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 561c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 5623af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 56394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, 0); 56494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 5658e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 56694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 56794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 56894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 56988c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 57088c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// COPY_TO_REGCLASS is just a normal copy, except that the destination 571f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// register is constrained to be in a particular register class. 572f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// 573f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 574bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 575bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 576f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 577f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 57892c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen // Create the new VReg in the destination class and emit a copy. 579f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 580f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass *DstRC = 581f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 582bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 58392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 58492c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen NewVReg).addReg(VReg); 585f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 586f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SDValue Op(Node, 0); 587f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 5888e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 589f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(isNew && "Node emitted out of order - early"); 590f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 591f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 592ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 593ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// 594ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Chengvoid InstrEmitter::EmitRegSequence(SDNode *Node, 5958b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 5968b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 5971300f3019e5d590231bbc3d907626708515d3212Owen Anderson unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 5981300f3019e5d590231bbc3d907626708515d3212Owen Anderson const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 599f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 600ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 601ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 602ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NumOps = Node->getNumOperands(); 6031300f3019e5d590231bbc3d907626708515d3212Owen Anderson assert((NumOps & 1) == 1 && 6041300f3019e5d590231bbc3d907626708515d3212Owen Anderson "REG_SEQUENCE must have an odd number of operands!"); 605e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 6061300f3019e5d590231bbc3d907626708515d3212Owen Anderson for (unsigned i = 1; i != NumOps; ++i) { 607ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op = Node->getOperand(i); 6081300f3019e5d590231bbc3d907626708515d3212Owen Anderson if ((i & 1) == 0) { 609cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 610cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper // Skip physical registers as they don't have a vreg to get and we'll 611cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper // insert copies for them in TwoAddressInstructionPass anyway. 612cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 613cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 614cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 615cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 616cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper const TargetRegisterClass *SRC = 61727e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 618cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper if (SRC && SRC != RC) { 619cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper MRI->setRegClass(NewVReg, SRC); 620cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper RC = SRC; 621cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper } 6225012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng } 623ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 6248b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 6258b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 626ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 627ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 628ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MBB->insert(InsertPos, MI); 629ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op(Node, 0); 630ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 6318e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 632ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert(isNew && "Node emitted out of order - early"); 633ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng} 634ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 635bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// EmitDbgValue - Generate machine instruction for a dbg_value node. 636bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// 637891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanMachineInstr * 638891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanInstrEmitter::EmitDbgValue(SDDbgValue *SD, 639891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 640bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng uint64_t Offset = SD->getOffset(); 641bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MDNode* MDPtr = SD->getMDPtr(); 642bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DebugLoc DL = SD->getDebugLoc(); 643bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 644f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen if (SD->getKind() == SDDbgValue::FRAMEIX) { 645f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Stack address; this needs to be lowered in target-dependent fashion. 646f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // EmitTargetCodeForFrameDebugValue is responsible for allocation. 647f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen unsigned FrameIx = SD->getFrameIx(); 648962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 649f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen } 650f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Otherwise, we're going to create an instruction here. 651e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 652bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 653bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng if (SD->getKind() == SDDbgValue::SDNODE) { 654c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDNode *Node = SD->getSDNode(); 655c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDValue Op = SDValue(Node, SD->getResNo()); 656c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // It's possible we replaced this SDNode with other(s) and therefore 657c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // didn't generate code for it. It's better to catch these cases where 658c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // they happen and transfer the debug info, but trying to guarantee that 659c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // in all cases would be very fragile; this is a safeguard for any 660c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // that were missed. 661c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 662c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen if (I==VRBaseMap.end()) 663c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen MIB.addReg(0U); // undef 664c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen else 665c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 6668b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 667bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng } else if (SD->getKind() == SDDbgValue::CONST) { 66846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Value *V = SD->getConst(); 66946510a73e977273ec67747eb34cbdb43f815e451Dan Gohman if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 6708594d429e02c688d428036f8563f09572da3fbffDevang Patel if (CI->getBitWidth() > 64) 6718594d429e02c688d428036f8563f09572da3fbffDevang Patel MIB.addCImm(CI); 6724ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman else 6734ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addImm(CI->getSExtValue()); 67446510a73e977273ec67747eb34cbdb43f815e451Dan Gohman } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 675bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addFPImm(CF); 676bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } else { 677bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // Could be an Undef. In any case insert an Undef so we can see what we 678bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // dropped. 679bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 680bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } 68106a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } else { 68206a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen // Insert an Undef so we can see what we dropped. 683bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 68406a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } 685bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 686bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addImm(Offset).addMetadata(MDPtr); 687bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng return &*MIB; 68806a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen} 68906a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen 6903d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitMachineNode - Generate machine code for a target-specific node and 6913d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 69294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 6933d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 6943d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 695af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 6963d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Opc = Node->getMachineOpcode(); 6973af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 6983d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle subreg insert/extract specially 6993af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (Opc == TargetOpcode::EXTRACT_SUBREG || 7003d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::INSERT_SUBREG || 7013d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 7028b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 7033d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 7043d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 70594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7063d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle COPY_TO_REGCLASS specially. 7073d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 7083d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyToRegClassNode(Node, VRBaseMap); 7093d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 7103d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 711f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 712ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng // Handle REG_SEQUENCE specially. 713ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (Opc == TargetOpcode::REG_SEQUENCE) { 7148b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 715ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng return; 716ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 717ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 7183d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::IMPLICIT_DEF) 7193d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // We want a unique VR for each IMPLICIT_DEF use. 7203d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 7213af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 722e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(Opc); 7233d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumResults = CountResults(Node); 72433a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen unsigned NumImpUses = 0; 725baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesen unsigned NodeOperands = 726baa74e4b35d96ee154c68fa6d204d854cb45f969Jakob Stoklund Olesen countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses); 72747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 72894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 7293d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumMIOperands = NodeOperands + NumResults; 73047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (II.isVariadic()) 73147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 73247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "Too few operands for a variadic node!"); 73347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner else 73447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 73533a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 73633a537a5c41e60507ac9a4ea987c1a395cbb74feJakob Stoklund Olesen NumImpUses && 73747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "#operands for dag node doesn't match .td file!"); 73894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 73994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7403d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Create the new machine instruction. 7413d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 742db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman 7433d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Add result register values for things that are defined by this 7443d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction. 7453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (NumResults) 7463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 7473af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 7483d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Emit all of the actual operands of this instruction, adding them to the 7493d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction as appropriate. 7503d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner bool HasOptPRefs = II.getNumDefs() > NumResults; 7513d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner assert((!HasOptPRefs || !HasPhysRegOuts) && 7523d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner "Unable to cope with optional defs and phys regs defs!"); 7533d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 7543d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = NumSkip; i != NodeOperands; ++i) 7553d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 7568b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 7573d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7583d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Transfer all of the memory reference descriptions of this instruction. 7593d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 7603d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner cast<MachineSDNode>(Node)->memoperands_end()); 7613d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 76214152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // Insert the instruction into position in the block. This needs to 76314152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // happen before any custom inserter hook is called so that the 76414152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // hook knows where in the block to insert the replacement code. 76514152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman MBB->insert(InsertPos, MI); 76614152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman 76759cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // The MachineInstr may also define physregs instead of virtregs. These 76859cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // physreg values can reach other instructions in different ways: 76959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 77059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 1. When there is a use of a Node value beyond the explicitly defined 77159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // virtual registers, we emit a CopyFromReg for one of the implicitly 77259cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // defined physregs. This only happens when HasPhysRegOuts is true. 77359cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 77459cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 2. A CopyFromReg reading a physreg may be glued to this instruction. 77559cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 77659cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 3. A glued instruction may implicitly use a physreg. 77759cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 77859cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 4. A glued instruction may use a RegisterSDNode operand. 77959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // 78059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // Collect all the used physreg defs, and make sure that any unused physreg 78159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // defs are marked as dead. 78259cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen SmallVector<unsigned, 8> UsedRegs; 78359cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen 784bece04845e6746fd162bc36e79a6cfd095165c23Eric Christopher // Additional results must be physical register defs. 7853d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (HasPhysRegOuts) { 7863d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 7873d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 78859cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (!Node->hasAnyUseOfValue(i)) 78959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen continue; 79059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // This implicitly defined physreg has a use. 79159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen UsedRegs.push_back(Reg); 79259cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 79394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 79494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7953af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 79659cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // Scan the glue chain for any used physregs. 79759cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 79859cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 79959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (F->getOpcode() == ISD::CopyFromReg) { 80059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 80159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen continue; 802f77c03a8599ca354393292bb6c918ea8dab6a21dHal Finkel } else if (F->getOpcode() == ISD::CopyToReg) { 803f77c03a8599ca354393292bb6c918ea8dab6a21dHal Finkel // Skip CopyToReg nodes that are internal to the glue chain. 804f77c03a8599ca354393292bb6c918ea8dab6a21dHal Finkel continue; 80559cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen } 80659cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // Collect declared implicit uses. 80759cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 80859cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen UsedRegs.append(MCID.getImplicitUses(), 80959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen MCID.getImplicitUses() + MCID.getNumImplicitUses()); 81059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // In addition to declared implicit uses, we must also check for 81159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // direct RegisterSDNode operands. 81259cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 81359cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 81459cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen unsigned Reg = R->getReg(); 81559cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(Reg)) 81659cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen UsedRegs.push_back(Reg); 81759cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen } 81847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner } 81959cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen } 82059cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen 82159cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen // Finally mark unused registers as dead. 82259cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen if (!UsedRegs.empty() || II.getImplicitDefs()) 82359cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46Jakob Stoklund Olesen MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 82437fefc20d3a1e3934a377567d54a141f67752227Evan Cheng 82537fefc20d3a1e3934a377567d54a141f67752227Evan Cheng // Run post-isel target hook to adjust this instruction if needed. 8263be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick#ifdef NDEBUG 82783a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick if (II.hasPostISelHook()) 8283be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick#endif 82983a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick TLI->AdjustInstrPostInstrSelection(MI, Node); 8303d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner} 83194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 8323d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitSpecialNode - Generate machine code for a target-independent node and 8333d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 8343d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 8353d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 8363d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner DenseMap<SDValue, unsigned> &VRBaseMap) { 83794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman switch (Node->getOpcode()) { 83894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman default: 83994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 840bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Node->dump(); 84194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 842c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("This target-independent node should have been selected!"); 84394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::EntryToken: 844c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("EntryToken should have been excluded from the schedule!"); 84537b7387da90ffd42d28ad0f08fca00b684294b2cEvan Cheng case ISD::MERGE_VALUES: 84694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::TokenFactor: // fall thru 84794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 84894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyToReg: { 84994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg; 85094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue SrcVal = Node->getOperand(2); 85194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 85294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = R->getReg(); 85394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 85494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = getVR(SrcVal, VRBaseMap); 8553af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 85694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 85794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 85894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 859f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 86092c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 86192c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen DestReg).addReg(SrcReg); 86294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 86394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 86494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyFromReg: { 86594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 866e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 86794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 86894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 8697561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner case ISD::EH_LABEL: { 8707561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 8717561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 8727561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner TII->get(TargetOpcode::EH_LABEL)).addSym(S); 8737561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner break; 8747561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner } 8753af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 876c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem case ISD::LIFETIME_START: 877c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem case ISD::LIFETIME_END: { 878c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 879c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 880c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem 881c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 882c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 883c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem .addFrameIndex(FI->getIndex()); 884c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem break; 885c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem } 886c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem 88794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::INLINEASM: { 88894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned NumOps = Node->getNumOperands(); 889f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 89029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner --NumOps; // Ignore the glue operand. 8913af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 89294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the inline asm machine instruction. 893bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 894518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::INLINEASM)); 89594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 89694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the asm string as an external symbol operand. 897decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 898decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 89994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateES(AsmStr)); 9003af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 901c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Add the HasSideEffect and isAlignStack bits. 902c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng int64_t ExtraInfo = 903c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 904f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen getZExtValue(); 905c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); 906f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen 90766390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen // Remember to operand index of the group flags. 90866390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen SmallVector<unsigned, 8> GroupIdx; 90966390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen 91094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add all of the operand registers to the instruction. 911decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 912f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned Flags = 913f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 91466390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 9153af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 91666390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen GroupIdx.push_back(MI->getNumOperands()); 91794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(Flags)); 91894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman ++i; // Skip the ID value. 9193af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 920decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner switch (InlineAsm::getKind(Flags)) { 921c23197a26f34f559ea9797de51e187087c039c42Torok Edwin default: llvm_unreachable("Bad flags!"); 922decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDef: 92366390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen for (unsigned j = 0; j != NumVals; ++j, ++i) { 92494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 9253013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // FIXME: Add dead flags for physical and virtual registers defined. 9263013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // For now, mark physical register defs as implicit to help fast 9273013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // regalloc. This makes inline asm look a lot like calls. 9283013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, true, 9293013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 93094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 93194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 932decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDefEarlyClobber: 933f792fa90f1125553008659c743cba85b9b5d2e5eJakob Stoklund Olesen case InlineAsm::Kind_Clobber: 93466390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen for (unsigned j = 0; j != NumVals; ++j, ++i) { 935913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 936c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 9373013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 938c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isKill=*/ false, 939c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isDead=*/ false, 940c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isUndef=*/false, 941c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isEarlyClobber=*/ true)); 942913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen } 943913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen break; 944decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegUse: // Use of register. 945decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Imm: // Immediate. 946decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Mem: // Addressing mode. 94794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // The addressing mode has been selected, just add all of the 94894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // operands to the machine instruction. 94966390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen for (unsigned j = 0; j != NumVals; ++j, ++i) 9508b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 9518b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/false, IsClone, IsCloned); 95266390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen 95366390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen // Manually set isTied bits. 95466390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 95566390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen unsigned DefGroup = 0; 95666390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 95766390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen unsigned DefIdx = GroupIdx[DefGroup] + 1; 95866390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen unsigned UseIdx = GroupIdx.back() + 1; 95994083149fd6891c8a72472cf1814fa6600a75979Jakob Stoklund Olesen for (unsigned j = 0; j != NumVals; ++j) 96094083149fd6891c8a72472cf1814fa6600a75979Jakob Stoklund Olesen MI->tieOperands(DefIdx + j, UseIdx + j); 96166390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen } 96266390805ad58871cde3f5ccd72a7dcac9b1cd4d8Jakob Stoklund Olesen } 96394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 96494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 96594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 9663af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 967cf9a415182aca6a432105a2a12168e1049de180aChris Lattner // Get the mdnode from the asm if it exists and add it to the instruction. 968cf9a415182aca6a432105a2a12168e1049de180aChris Lattner SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 969cf9a415182aca6a432105a2a12168e1049de180aChris Lattner const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 970cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson if (MD) 971cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson MI->addOperand(MachineOperand::CreateMetadata(MD)); 9723af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 973bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 97494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 97594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 97694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 97794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 97894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 979bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 980bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// at the given position in the given block. 981bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 982bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineBasicBlock::iterator insertpos) 983bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman : MF(mbb->getParent()), 984bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MRI(&MF->getRegInfo()), 985bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TM(&MF->getTarget()), 986bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TII(TM->getInstrInfo()), 987bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TRI(TM->getRegisterInfo()), 988bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TLI(TM->getTargetLowering()), 989bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB(mbb), InsertPos(insertpos) { 99094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 991