InstrEmitter.cpp revision 92c1f72c548e6a5e793ef19a0b04910992115b6c
1bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// The LLVM Compiler Infrastructure 494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// This file is distributed under the University of Illinois Open Source 694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// License. See LICENSE.TXT for details. 794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 10bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// This implements the Emit routines for the SelectionDAG class, which creates 11bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// MachineInstrs based on the decisions of the SelectionDAG instruction 12bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// selection. 1394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 1494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 1594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#define DEBUG_TYPE "instr-emitter" 17bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#include "InstrEmitter.h" 18a8efe28a44996978faa42a387f1a6087a7b942c7Evan Cheng#include "SDNodeDbgValue.h" 1994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineConstantPool.h" 2094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineFunction.h" 2194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineInstrBuilder.h" 2294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 2394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetData.h" 2494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetMachine.h" 2594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetInstrInfo.h" 2694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetLowering.h" 2794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/ADT/Statistic.h" 2894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/Debug.h" 29c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/MathExtras.h" 3194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohmanusing namespace llvm; 3294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 33bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountResults - The results of target nodes have register or immediate 34bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// operands first, then an optional chain, and optional flag operands (which do 35bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// not go into the resulting MachineInstr). 36bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountResults(SDNode *Node) { 37bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumValues(); 38bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman while (N && Node->getValueType(N - 1) == MVT::Flag) 39bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 40bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getValueType(N - 1) == MVT::Other) 41bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Skip over chain result. 42bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 43bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 44bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 45bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountOperands - The inputs to target nodes have any actual inputs first, 46bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// followed by an optional chain operand, then an optional flag operand. 47bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// Compute the number of actual operands that will go into the resulting 48bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// MachineInstr. 49bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountOperands(SDNode *Node) { 50bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumOperands(); 51bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 53bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Ignore chain if it exists. 55bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 56bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 57bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 5894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 5994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// implicit physical register output. 60bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter:: 615202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris LattnerEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 625202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris Lattner unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 6394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 6494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 6594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Just use the input register directly! 6694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 6794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 6894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 6994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 7094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 7194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 7294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return; 7394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 7694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 7794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool MatchReg = true; 781cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng const TargetRegisterClass *UseRC = NULL; 79e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!IsClone && !IsCloned) 80e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 82e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 83e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool Match = true; 84e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 85e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 86e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == ResNo) { 87e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng VRBase = DestReg; 90e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 91e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else if (DestReg != SrcReg) 92e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 93e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else { 94e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDValue Op = User->getOperand(i); 96e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (Op.getNode() != Node || Op.getResNo() != ResNo) 97e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 98e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(Op.getResNo()); 99825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson if (VT == MVT::Other || VT == MVT::Flag) 100e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 101e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 102e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->isMachineOpcode()) { 103e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 1042a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = 0; 1052a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (i+II.getNumDefs() < II.getNumOperands()) 1062a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!UseRC) 108e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UseRC = RC; 109f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman else if (RC) { 110f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // If multiple uses expect disjoint register classes, we emit 112f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // copies in AddRegisterOperand. 113f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen if (ComRC) 114f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen UseRC = ComRC; 115f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 116e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 1171cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } 11894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 119e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng MatchReg &= Match; 120e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (VRBase) 121e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng break; 12294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 12394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 124e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(ResNo); 12594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 12794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 12894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 12994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase) { 130bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstRC = MRI->getRegClass(VRBase); 1311cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } else if (UseRC) { 1321cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1331cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = UseRC; 13494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 1351cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = TLI->getRegClassFor(VT); 13694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 13794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 13894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If all uses are reading from the src physical register and copying the 13994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // register is either impossible or very expensive, then don't create a copy. 14094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (MatchReg && SrcRC->getCopyCost() < 0) { 14194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = SrcReg; 14294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 14394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg, emit the copy. 144bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(DstRC); 14592c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 14692c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen VRBase).addReg(SrcReg); 14794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 14894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 14994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 15094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 15194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 15294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 15394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 15494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 15594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 15694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 15794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getDstOfCopyToRegUse - If the only use of the specified result number of 15894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// node is a CopyToReg, return its destination register. Return 0 otherwise. 159bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 160bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned ResNo) const { 16194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!Node->hasOneUse()) 16294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 16394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *Node->use_begin(); 16594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 16694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node && 16794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getResNo() == ResNo) { 16894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 16994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(Reg)) 17094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return Reg; 17194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 17294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 17394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 17494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 175bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 176e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng const TargetInstrDesc &II, 177e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool IsClone, bool IsCloned, 1785c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 179518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 18094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 18194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 18294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (unsigned i = 0; i < II.getNumDefs(); ++i) { 18394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the specific node value is only used by a CopyToReg and the dest reg 184f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // is a vreg in the same register class, use the CopyToReg'd destination 185f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // register instead of creating a new vreg. 18694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 1872a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 1888955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (II.OpInfo[i].isOptionalDef()) { 1898955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng // Optional def must be a physical register. 1908955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng unsigned NumResults = CountResults(Node); 1918955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 1928955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 1938955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 1948955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng } 195e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng 1968955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (!VRBase && !IsClone && !IsCloned) 197e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 198e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 199e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 200e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 201e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 202e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == i) { 203e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 204e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(Reg)) { 205bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 206f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (RegRC == RC) { 207f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VRBase = Reg; 208f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 209f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman break; 210f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 211e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 21294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 21594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the result registers for this node and add the result regs to 21694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the machine instruction. 21794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase == 0) { 21894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(RC && "Isn't a register operand!"); 219bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(RC); 22094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 22194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 22294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 22394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, i); 2245c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng if (IsClone) 2255c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng VRBaseMap.erase(Op); 22694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 22794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 22894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 22994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 23094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 23194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 23294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getVR - Return the virtual register corresponding to the specified result 23394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// of the specified node. 234bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getVR(SDValue Op, 235bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 23694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode() && 237518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 23894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add an IMPLICIT_DEF instruction before every use. 23994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 24094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 24194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // does not include operand register class info. 24294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!VReg) { 24394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 244bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VReg = MRI->createVirtualRegister(RC); 24594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 2463cd26a2909cd5d002fe2742041a264ba217ba88eDan Gohman BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 247518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 24894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return VReg; 24994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 25094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 25294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 25394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return I->second; 25494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 25594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 257f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// AddRegisterOperand - Add the specified register as an operand to the 258f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// specified machine instr. Insert register copies if the register is 259f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// not in the required register class. 260f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 261bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 262bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 263bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetInstrDesc *II, 264bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 2658b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 266825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 267825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson Op.getValueType() != MVT::Flag && 268f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Chain and flag operands should occur at end of operand list!"); 269f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Get/emit the operand. 270f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Op, VRBaseMap); 271f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 272f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 273f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetInstrDesc &TID = MI->getDesc(); 274f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isOptDef = IIOpNum < TID.getNumOperands() && 275f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman TID.OpInfo[IIOpNum].isOptionalDef(); 276f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 277f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // If the instruction requires a register in a different class, create 278f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // a new virtual register and copy the value into it. 279f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (II) { 280bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 2812a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *DstRC = 0; 2822a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (IIOpNum < II->getNumOperands()) 2832a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 284f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 285f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Don't have operand info for this instruction!"); 286f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 287bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 28892c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 28992c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 290f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VReg = NewVReg; 291f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 292f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 293f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 29447bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman // If this value has only one use, that use is a kill. This is a 2959d7019f586719a03f3519142ca2166166962e433Dan Gohman // conservative approximation. InstrEmitter does trivial coalescing 2969d7019f586719a03f3519142ca2166166962e433Dan Gohman // with CopyFromReg nodes, so don't emit kill flags for them. 2978b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // Avoid kill flags on Schedule cloned nodes, since there will be 2988b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // multiple uses. 2999d7019f586719a03f3519142ca2166166962e433Dan Gohman // Tied operands are never killed, so we need to check that. And that 3009d7019f586719a03f3519142ca2166166962e433Dan Gohman // means we need to determine the index of the operand. 3019d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isKill = Op.hasOneUse() && 3029d7019f586719a03f3519142ca2166166962e433Dan Gohman Op.getNode()->getOpcode() != ISD::CopyFromReg && 3038b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !IsDebug && 3048b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !(IsClone || IsCloned); 3059d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isKill) { 3069d7019f586719a03f3519142ca2166166962e433Dan Gohman unsigned Idx = MI->getNumOperands(); 3079d7019f586719a03f3519142ca2166166962e433Dan Gohman while (Idx > 0 && 3089d7019f586719a03f3519142ca2166166962e433Dan Gohman MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3099d7019f586719a03f3519142ca2166166962e433Dan Gohman --Idx; 3109d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 3119d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isTied) 3129d7019f586719a03f3519142ca2166166962e433Dan Gohman isKill = false; 3139d7019f586719a03f3519142ca2166166962e433Dan Gohman } 31447bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman 315bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 31647bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman false/*isImp*/, isKill, 317bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isDead*/, false/*isUndef*/, 318bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isEarlyClobber*/, 319bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 0/*SubReg*/, IsDebug)); 320f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 321f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 32294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// AddOperand - Add the specified operand to the specified machine instr. II 32394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// specifies the instruction information for the node, and IIOpNum is the 32494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// operand number (in the II) that we are adding. IIOpNum and II are used for 32594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// assertions only. 326bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 327bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 328bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetInstrDesc *II, 329bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 3308b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 33194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode()) { 3328b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3338b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 33494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 335d842962e27b10b6831c2421fa257e3fd58a85b18Chris Lattner MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 33694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3374fbd796a1251a27e6590765a0a34876f436a0af9Dan Gohman const ConstantFP *CFP = F->getConstantFPValue(); 33894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFPImm(CFP)); 33994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 34086b49f8e2de796cb46c7c8b6a4c4900533fd53f4Dale Johannesen MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 34194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3426ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3436ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner TGA->getTargetFlags())); 344f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 345f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 34694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 34794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 34894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3496ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3506ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner JT->getTargetFlags())); 35194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 35294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman int Offset = CP->getOffset(); 35394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Align = CP->getAlignment(); 35494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const Type *Type = CP->getType(); 35594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // MachineConstantPool wants an explicit alignment. 35694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 357bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getPrefTypeAlignment(Type); 35894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 35994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Alignment of vector types. FIXME! 360bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getTypeAllocSize(Type); 36194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 36494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Idx; 365bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineConstantPool *MCP = MF->getConstantPool(); 36694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (CP->isMachineConstantPoolEntry()) 367bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 36894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 369bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 3706ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 3716ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner CP->getTargetFlags())); 372056292fd738924f3f7703725d8f630983794b5a5Bill Wendling } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 37331e2c7b4c13c2f31774614b1124533628958d0cdDaniel Dunbar MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 3746ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner ES->getTargetFlags())); 3758c2b52552c90f39e4b2fed43e309e599e742b6acDan Gohman } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 37629cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 37729cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman BA->getTargetFlags())); 37894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 379825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 380825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson Op.getValueType() != MVT::Flag && 38194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "Chain and flag operands should occur at end of operand list!"); 3828b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3838b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 384f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 385f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 386f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 387f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 388f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// "SubIdx"'th sub-register class is the specified register class and whose 389f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// type matches the specified type. 390f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanstatic const TargetRegisterClass* 391f8c7394781f7cf27ac52ca087e289436d36844daDan GohmangetSuperRegisterRegClass(const TargetRegisterClass *TRC, 392e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson unsigned SubIdx, EVT VT) { 393f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Pick the register class of the superegister for this type 394f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 395f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman E = TRC->superregclasses_end(); I != E; ++I) 396fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 397f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return *I; 398f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(false && "Couldn't find the register class"); 399f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return 0; 40094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 40194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 40294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitSubregNode - Generate machine code for subreg nodes. 40394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 404bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::EmitSubregNode(SDNode *Node, 4058b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 4068b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 40794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 40894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Opc = Node->getMachineOpcode(); 40994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 41094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 41194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 41294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 41394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman UI != E; ++UI) { 41494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *UI; 41594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 41694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node) { 41794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 41894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 41994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = DestReg; 42094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 42194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 425518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG) { 4260bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub 427f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 42894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 42994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 430f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 431bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 432fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 433fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 43494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 4355ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Figure out the register class to create for the destreg. 4365ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Note that if we're going to directly use an existing register, 4375ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // it must be precisely the required class, and not a subclass 4385ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // thereof. 439bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 44094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg 44194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(SRC && "Couldn't find source register class"); 442bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 44394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4445ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 4450bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen // Create the extract_subreg machine instruction. 4460bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 4470bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen TII->get(TargetOpcode::COPY), VRBase); 4480bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen 4490bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen // Add source, and subreg index 4508b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false, 4518b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 4520bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) && 4530bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen "Cannot yet extract from physregs"); 4540bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen MI->getOperand(1).setSubReg(SubIdx); 455bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 456518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner } else if (Opc == TargetOpcode::INSERT_SUBREG || 457518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 45894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N0 = Node->getOperand(0); 45994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N1 = Node->getOperand(1); 46094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N2 = Node->getOperand(2); 461f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned SubReg = getVR(N1, VRBaseMap); 462f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 463bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 4645ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman const TargetRegisterClass *SRC = 465ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 4665ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 46794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 4685ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Note that if we're going to directly use an existing register, 4695ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // it must be precisely the required class, and not a subclass 4705ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // thereof. 471bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 4725ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Create the reg 4735ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman assert(SRC && "Couldn't find source register class"); 474bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 47594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4765ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 47794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the insert_subreg or subreg_to_reg machine instruction. 478bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 47994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 48094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 48194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If creating a subreg_to_reg, then the first input operand 48294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // is an implicit value immediate, otherwise it's a register 483518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::SUBREG_TO_REG) { 48494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 485f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 48694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 4878b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 4888b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 48994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the subregster being inserted 4908b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 4918b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 49294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 493bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 49494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 495c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 49694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 49794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, 0); 49894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 49994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 50094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 50194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 50294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 50388c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 50488c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// COPY_TO_REGCLASS is just a normal copy, except that the destination 505f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// register is constrained to be in a particular register class. 506f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// 507f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 508bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 509bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 510f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 511f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 51292c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen // Create the new VReg in the destination class and emit a copy. 513f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 514f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 515bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 51692c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 51792c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen NewVReg).addReg(VReg); 518f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 519f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SDValue Op(Node, 0); 520f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 521f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman isNew = isNew; // Silence compiler warning. 522f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(isNew && "Node emitted out of order - early"); 523f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 524f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 525ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 526ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// 527ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Chengvoid InstrEmitter::EmitRegSequence(SDNode *Node, 5288b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 5298b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 530ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); 531ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NewVReg = MRI->createVirtualRegister(RC); 532ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 533ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 534ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NumOps = Node->getNumOperands(); 535ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert((NumOps & 1) == 0 && 536ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng "REG_SEQUENCE must have an even number of operands!"); 537ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 538ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng for (unsigned i = 0; i != NumOps; ++i) { 539ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op = Node->getOperand(i); 540ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (i & 1) { 541ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 542ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 54360ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 54460ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *SRC = 54527e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 54627e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng if (!SRC) 54727e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng llvm_unreachable("Invalid subregister index in REG_SEQUENCE"); 5485012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng if (SRC != RC) { 54927e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng MRI->setRegClass(NewVReg, SRC); 5505012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng RC = SRC; 5515012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng } 552ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 5538b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 5548b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 555ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 556ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 557ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MBB->insert(InsertPos, MI); 558ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op(Node, 0); 559ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 560ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng isNew = isNew; // Silence compiler warning. 561ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert(isNew && "Node emitted out of order - early"); 562ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng} 563ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 564bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// EmitDbgValue - Generate machine instruction for a dbg_value node. 565bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// 566891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanMachineInstr * 567891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanInstrEmitter::EmitDbgValue(SDDbgValue *SD, 568891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 569bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng uint64_t Offset = SD->getOffset(); 570bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MDNode* MDPtr = SD->getMDPtr(); 571bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DebugLoc DL = SD->getDebugLoc(); 572bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 573f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen if (SD->getKind() == SDDbgValue::FRAMEIX) { 574f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Stack address; this needs to be lowered in target-dependent fashion. 575f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // EmitTargetCodeForFrameDebugValue is responsible for allocation. 576f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen unsigned FrameIx = SD->getFrameIx(); 577962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 578f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen } 579f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Otherwise, we're going to create an instruction here. 58006a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 581bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 582bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng if (SD->getKind() == SDDbgValue::SDNODE) { 583c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDNode *Node = SD->getSDNode(); 584c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDValue Op = SDValue(Node, SD->getResNo()); 585c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // It's possible we replaced this SDNode with other(s) and therefore 586c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // didn't generate code for it. It's better to catch these cases where 587c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // they happen and transfer the debug info, but trying to guarantee that 588c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // in all cases would be very fragile; this is a safeguard for any 589c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // that were missed. 590c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 591c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen if (I==VRBaseMap.end()) 592c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen MIB.addReg(0U); // undef 593c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen else 594c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 5958b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 596bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng } else if (SD->getKind() == SDDbgValue::CONST) { 59746510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Value *V = SD->getConst(); 59846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 599cc87bfb59b34a0543b48d93f661f2abaee6b4ceeDevang Patel // FIXME: SDDbgValue constants aren't updated with legalization, so it's 600cc87bfb59b34a0543b48d93f661f2abaee6b4ceeDevang Patel // possible to have i128 constants in them at this point. Dwarf writer 601cc87bfb59b34a0543b48d93f661f2abaee6b4ceeDevang Patel // does not handle i128 constants at the moment so, as a crude workaround, 602cc87bfb59b34a0543b48d93f661f2abaee6b4ceeDevang Patel // just drop the debug info if this happens. 6034ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman if (!CI->getValue().isSignedIntN(64)) 6044ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addReg(0U); 6054ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman else 6064ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addImm(CI->getSExtValue()); 60746510a73e977273ec67747eb34cbdb43f815e451Dan Gohman } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 608bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addFPImm(CF); 609bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } else { 610bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // Could be an Undef. In any case insert an Undef so we can see what we 611bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // dropped. 612bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 613bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } 61406a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } else { 61506a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen // Insert an Undef so we can see what we dropped. 616bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 61706a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } 618bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 619bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addImm(Offset).addMetadata(MDPtr); 620bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng return &*MIB; 62106a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen} 62206a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen 6233d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitMachineNode - Generate machine code for a target-specific node and 6243d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 62594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 6263d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 6273d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 628af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 6293d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Opc = Node->getMachineOpcode(); 6303d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6313d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle subreg insert/extract specially 6323d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG || 6333d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::INSERT_SUBREG || 6343d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 6358b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 6363d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6373d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 63894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6393d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle COPY_TO_REGCLASS specially. 6403d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 6413d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyToRegClassNode(Node, VRBaseMap); 6423d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6433d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 644f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 645ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng // Handle REG_SEQUENCE specially. 646ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (Opc == TargetOpcode::REG_SEQUENCE) { 6478b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 648ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng return; 649ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 650ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 6513d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::IMPLICIT_DEF) 6523d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // We want a unique VR for each IMPLICIT_DEF use. 6533d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6543d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6553d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner const TargetInstrDesc &II = TII->get(Opc); 6563d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumResults = CountResults(Node); 6573d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NodeOperands = CountOperands(Node); 65847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 65994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 6603d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumMIOperands = NodeOperands + NumResults; 66147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (II.isVariadic()) 66247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 66347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "Too few operands for a variadic node!"); 66447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner else 66547cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 66647cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 66747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "#operands for dag node doesn't match .td file!"); 66894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 66994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6703d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Create the new machine instruction. 6713d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 672db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman 673db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // The MachineInstr constructor adds implicit-def operands. Scan through 674db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // these to determine which are dead. 675db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (MI->getNumOperands() != 0 && 676db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman Node->getValueType(Node->getNumValues()-1) == MVT::Flag) { 677db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // First, collect all used registers. 678db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman SmallVector<unsigned, 8> UsedRegs; 679db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman for (SDNode *F = Node->getFlaggedUser(); F; F = F->getFlaggedUser()) 680db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (F->getOpcode() == ISD::CopyFromReg) 681db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 682db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman else { 683db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Collect declared implicit uses. 684db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman const TargetInstrDesc &TID = TII->get(F->getMachineOpcode()); 685db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.append(TID.getImplicitUses(), 686db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman TID.getImplicitUses() + TID.getNumImplicitUses()); 687db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // In addition to declared implicit uses, we must also check for 688db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // direct RegisterSDNode operands. 689db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 690db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 691db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman unsigned Reg = R->getReg(); 692db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) 693db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(Reg); 694db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 695db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 696db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Then mark unused registers as dead. 697db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 698db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 6993d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7003d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Add result register values for things that are defined by this 7013d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction. 7023d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (NumResults) 7033d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 7043d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7053d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Emit all of the actual operands of this instruction, adding them to the 7063d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction as appropriate. 7073d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner bool HasOptPRefs = II.getNumDefs() > NumResults; 7083d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner assert((!HasOptPRefs || !HasPhysRegOuts) && 7093d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner "Unable to cope with optional defs and phys regs defs!"); 7103d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 7113d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = NumSkip; i != NodeOperands; ++i) 7123d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 7138b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 7143d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7153d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Transfer all of the memory reference descriptions of this instruction. 7163d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 7173d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner cast<MachineSDNode>(Node)->memoperands_end()); 7183d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 71914152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // Insert the instruction into position in the block. This needs to 72014152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // happen before any custom inserter hook is called so that the 72114152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // hook knows where in the block to insert the replacement code. 72214152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman MBB->insert(InsertPos, MI); 72314152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman 7243d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (II.usesCustomInsertionHook()) { 7253d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Insert this instruction into the basic block using a target 7263d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // specific inserter which may returns a new basic block. 72784023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman bool AtEnd = InsertPos == MBB->end(); 72884023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB); 72984023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman if (NewMBB != MBB) { 73084023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman if (AtEnd) 73184023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman InsertPos = NewMBB->end(); 73284023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman MBB = NewMBB; 73384023e0fbefc406a4c611d3d64a10df5d3a97dd7Dan Gohman } 7347bf198fd607b356e767e0577cac81c3491c4bc90Chris Lattner return; 7353d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 7367bf198fd607b356e767e0577cac81c3491c4bc90Chris Lattner 7373d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Additional results must be an physical register def. 7383d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (HasPhysRegOuts) { 7393d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 7403d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 7413d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Node->hasAnyUseOfValue(i)) 7423d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 7433d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // If there are no uses, mark the register as dead now, so that 7443d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // MachineLICM/Sink can see that it's dead. Don't do this if the 7453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // node has a Flag value, for the benefit of targets still using 7463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Flag for values in physregs. 7473d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 7483d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->addRegisterDead(Reg, TRI); 74994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 75094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 75147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner 75247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // If the instruction has implicit defs and the node doesn't, mark the 75347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // implicit def as dead. If the node has any flag outputs, we don't do this 75447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // because we don't know what implicit defs are being used by flagged nodes. 755d05e8055362be52fc33dcc685ba2ae5c722506b5Evan Cheng if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 75647cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (const unsigned *IDList = II.getImplicitDefs()) { 75747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 75847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner i != e; ++i) 75947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 76047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner } 7613d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner} 76294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7633d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitSpecialNode - Generate machine code for a target-independent node and 7643d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 7653d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 7663d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 7673d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner DenseMap<SDValue, unsigned> &VRBaseMap) { 76894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman switch (Node->getOpcode()) { 76994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman default: 77094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 771bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Node->dump(); 77294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 773c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("This target-independent node should have been selected!"); 77494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 77594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::EntryToken: 776c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("EntryToken should have been excluded from the schedule!"); 77794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 77837b7387da90ffd42d28ad0f08fca00b684294b2cEvan Cheng case ISD::MERGE_VALUES: 77994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::TokenFactor: // fall thru 78094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 78194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyToReg: { 78294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg; 78394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue SrcVal = Node->getOperand(2); 78494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 78594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = R->getReg(); 78694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 78794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = getVR(SrcVal, VRBaseMap); 78894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 78994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 79094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 79194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 792f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 79392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 79492c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen DestReg).addReg(SrcReg); 79594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 79694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 79794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyFromReg: { 79894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 799e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 80094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 80194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 8027561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner case ISD::EH_LABEL: { 8037561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 8047561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 8057561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner TII->get(TargetOpcode::EH_LABEL)).addSym(S); 8067561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner break; 8077561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner } 8087561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner 80994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::INLINEASM: { 81094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned NumOps = Node->getNumOperands(); 811825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 81294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman --NumOps; // Ignore the flag operand. 81394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 81494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the inline asm machine instruction. 815bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 816518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::INLINEASM)); 81794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 81894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the asm string as an external symbol operand. 819decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 820decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 82194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateES(AsmStr)); 82294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 823f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen // Add the isAlignStack bit. 824f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen int64_t isAlignStack = 825f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))-> 826f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen getZExtValue(); 827f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen MI->addOperand(MachineOperand::CreateImm(isAlignStack)); 828f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen 82994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add all of the operand registers to the instruction. 830decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 831f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned Flags = 832f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 833697cbbfb00c318f98d6eb51945f077e2bfe8781eEvan Cheng unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 83494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 83594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(Flags)); 83694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman ++i; // Skip the ID value. 83794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 838decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner switch (InlineAsm::getKind(Flags)) { 839c23197a26f34f559ea9797de51e187087c039c42Torok Edwin default: llvm_unreachable("Bad flags!"); 840decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDef: 84194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) { 84294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 8433013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // FIXME: Add dead flags for physical and virtual registers defined. 8443013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // For now, mark physical register defs as implicit to help fast 8453013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // regalloc. This makes inline asm look a lot like calls. 8463013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, true, 8473013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 84894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 84994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 850decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDefEarlyClobber: 851913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen for (; NumVals; --NumVals, ++i) { 852913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 853c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 8543013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 855c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isKill=*/ false, 856c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isDead=*/ false, 857c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isUndef=*/false, 858c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isEarlyClobber=*/ true)); 859913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen } 860913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen break; 861decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegUse: // Use of register. 862decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Imm: // Immediate. 863decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Mem: // Addressing mode. 86494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // The addressing mode has been selected, just add all of the 86594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // operands to the machine instruction. 86694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) 8678b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 8688b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/false, IsClone, IsCloned); 86994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 87094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 87194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 872cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 873cf9a415182aca6a432105a2a12168e1049de180aChris Lattner // Get the mdnode from the asm if it exists and add it to the instruction. 874cf9a415182aca6a432105a2a12168e1049de180aChris Lattner SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 875cf9a415182aca6a432105a2a12168e1049de180aChris Lattner const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 876cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson if (MD) 877cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson MI->addOperand(MachineOperand::CreateMetadata(MD)); 878cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 879bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 88094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 88194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 88294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 88394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 88494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 885bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 886bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// at the given position in the given block. 887bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 888bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineBasicBlock::iterator insertpos) 889bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman : MF(mbb->getParent()), 890bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MRI(&MF->getRegInfo()), 891bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TM(&MF->getTarget()), 892bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TII(TM->getInstrInfo()), 893bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TRI(TM->getRegisterInfo()), 894bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TLI(TM->getTargetLowering()), 895bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB(mbb), InsertPos(insertpos) { 89694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 897