InstrEmitter.cpp revision 9cf37e8b48732fccd4c301ed51aafed7074bd84e
1bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// The LLVM Compiler Infrastructure 494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// This file is distributed under the University of Illinois Open Source 694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// License. See LICENSE.TXT for details. 794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 10bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// This implements the Emit routines for the SelectionDAG class, which creates 11bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// MachineInstrs based on the decisions of the SelectionDAG instruction 12bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// selection. 1394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 1494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 1594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#define DEBUG_TYPE "instr-emitter" 17bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#include "InstrEmitter.h" 18a8efe28a44996978faa42a387f1a6087a7b942c7Evan Cheng#include "SDNodeDbgValue.h" 1994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineConstantPool.h" 2094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineFunction.h" 2194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineInstrBuilder.h" 2294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 2394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetData.h" 2494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetMachine.h" 2594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetInstrInfo.h" 2694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetLowering.h" 2794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/ADT/Statistic.h" 2894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/Debug.h" 29c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/MathExtras.h" 3194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohmanusing namespace llvm; 3294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 33d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// MinRCSize - Smallest register class we allow when constraining virtual 34d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// registers. If satisfying all register class constraints would require 35d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// using a smaller register class, emit a COPY to a new virtual register 36d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen/// instead. 37d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesenconst unsigned MinRCSize = 4; 38d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 39bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountResults - The results of target nodes have register or immediate 4029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// operands first, then an optional chain, and optional glue operands (which do 41bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// not go into the resulting MachineInstr). 42bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountResults(SDNode *Node) { 43bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumValues(); 44f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getValueType(N - 1) == MVT::Glue) 45bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 46bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getValueType(N - 1) == MVT::Other) 47bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Skip over chain result. 48bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 49bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 50bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 51bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountOperands - The inputs to target nodes have any actual inputs first, 5229d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// followed by an optional chain operand, then an optional glue operand. 53bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// Compute the number of actual operands that will go into the resulting 54bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// MachineInstr. 55bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountOperands(SDNode *Node) { 56bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumOperands(); 57f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 58bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 59bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 60bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Ignore chain if it exists. 61bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 62bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 63bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 6494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 6594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// implicit physical register output. 66bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter:: 675202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris LattnerEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 685202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris Lattner unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 6994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 7094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 7194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Just use the input register directly! 7294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 7394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 7494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 7594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 768e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 7794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 7894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return; 7994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 8094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 8194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 8294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 8394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool MatchReg = true; 841cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng const TargetRegisterClass *UseRC = NULL; 85c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen EVT VT = Node->getValueType(ResNo); 86c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 87c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen // Stick to the preferred register classes for legal types. 88c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen if (TLI->isTypeLegal(VT)) 89c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen UseRC = TLI->getRegClassFor(VT); 90c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 91e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!IsClone && !IsCloned) 92e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 93e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 94e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 95e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool Match = true; 963af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 97e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 98e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == ResNo) { 99e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 100e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 101e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng VRBase = DestReg; 102e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 103e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else if (DestReg != SrcReg) 104e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 105e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else { 106e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 107e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDValue Op = User->getOperand(i); 108e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (Op.getNode() != Node || Op.getResNo() != ResNo) 109e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 110e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(Op.getResNo()); 111f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (VT == MVT::Other || VT == MVT::Glue) 112e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 113e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 114e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->isMachineOpcode()) { 115e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 1162a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = 0; 1172a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (i+II.getNumDefs() < II.getNumOperands()) 11815993f83a419950f06d2879d6701530ae6449317Evan Cheng RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); 119e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!UseRC) 120e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UseRC = RC; 121f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman else if (RC) { 122e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *ComRC = 123e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen TRI->getCommonSubClass(UseRC, RC); 124f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // If multiple uses expect disjoint register classes, we emit 125f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // copies in AddRegisterOperand. 126f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen if (ComRC) 127f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen UseRC = ComRC; 128f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 129e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 1301cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } 13194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 132e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng MatchReg &= Match; 133e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (VRBase) 134e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng break; 13594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 13694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 13794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 138d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 139c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 14094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 14194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase) { 142bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstRC = MRI->getRegClass(VRBase); 1431cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } else if (UseRC) { 1441cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1451cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = UseRC; 14694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 1471cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = TLI->getRegClassFor(VT); 14894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 1493af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 15094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If all uses are reading from the src physical register and copying the 15194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // register is either impossible or very expensive, then don't create a copy. 15294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (MatchReg && SrcRC->getCopyCost() < 0) { 15394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = SrcReg; 15494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 15594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg, emit the copy. 156bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(DstRC); 15792c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 15892c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen VRBase).addReg(SrcReg); 15994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 16094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 16294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 16394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 16494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 1658e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 16694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 16794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 16894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getDstOfCopyToRegUse - If the only use of the specified result number of 17094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// node is a CopyToReg, return its destination register. Return 0 otherwise. 171bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 172bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned ResNo) const { 17394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!Node->hasOneUse()) 17494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 17594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 17694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *Node->use_begin(); 1773af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 17894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node && 17994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getResNo() == ResNo) { 18094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 18194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(Reg)) 18294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return Reg; 18394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 18494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 18594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 18694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 187bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 188e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II, 189e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool IsClone, bool IsCloned, 1905c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 191518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 19294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 19394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 19494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (unsigned i = 0; i < II.getNumDefs(); ++i) { 19594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the specific node value is only used by a CopyToReg and the dest reg 196f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // is a vreg in the same register class, use the CopyToReg'd destination 197f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // register instead of creating a new vreg. 19894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 19915993f83a419950f06d2879d6701530ae6449317Evan Cheng const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); 2008955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (II.OpInfo[i].isOptionalDef()) { 2018955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng // Optional def must be a physical register. 2028955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng unsigned NumResults = CountResults(Node); 2038955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 2048955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 2058955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 2068955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng } 207e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng 2088955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (!VRBase && !IsClone && !IsCloned) 209e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 210e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 211e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 2123af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 213e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 214e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == i) { 215e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 216e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(Reg)) { 217bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 218f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (RegRC == RC) { 219f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VRBase = Reg; 220f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 221f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman break; 222f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 223e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 22494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 22594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 22694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 22794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the result registers for this node and add the result regs to 22894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the machine instruction. 22994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase == 0) { 23094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(RC && "Isn't a register operand!"); 231bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(RC); 23294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 23394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 23494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 23594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, i); 2365c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng if (IsClone) 2375c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng VRBaseMap.erase(Op); 23894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 2398e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 24094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 24194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 24294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 24394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 24494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getVR - Return the virtual register corresponding to the specified result 24594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// of the specified node. 246bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getVR(SDValue Op, 247bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 24894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode() && 249518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 25094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add an IMPLICIT_DEF instruction before every use. 25194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 252e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 25394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // does not include operand register class info. 25494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!VReg) { 25594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 256bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VReg = MRI->createVirtualRegister(RC); 25794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 2583cd26a2909cd5d002fe2742041a264ba217ba88eDan Gohman BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 259518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 26094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return VReg; 26194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 26294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 26394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 26494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 26594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return I->second; 26694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 26794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 268c040719a153df8202f10054f33c9ac581b1c6c57Bill Wendling 269f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// AddRegisterOperand - Add the specified register as an operand to the 270f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// specified machine instr. Insert register copies if the register is 271f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// not in the required register class. 272f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 273bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 274bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 275e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 276bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 2778b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 278825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 279f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 28029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 281f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Get/emit the operand. 282f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Op, VRBaseMap); 283f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 284f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 285e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 286e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptDef = IIOpNum < MCID.getNumOperands() && 287e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCID.OpInfo[IIOpNum].isOptionalDef(); 288f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 289f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // If the instruction requires a register in a different class, create 29008f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // a new virtual register and copy the value into it, but first attempt to 29108f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // shrink VReg's register class within reason. For example, if VReg == GR32 29208f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 293f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (II) { 2942a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *DstRC = 0; 2952a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (IIOpNum < II->getNumOperands()) 29615993f83a419950f06d2879d6701530ae6449317Evan Cheng DstRC = TII->getRegClass(*II, IIOpNum, TRI); 2975a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) && 298f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Don't have operand info for this instruction!"); 29908f5cdf5b33b8202edddb24abee6af2a0b3ae49cJakob Stoklund Olesen if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 300bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 30192c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 30292c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 303f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VReg = NewVReg; 304f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 305f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 306f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 30747bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman // If this value has only one use, that use is a kill. This is a 3089d7019f586719a03f3519142ca2166166962e433Dan Gohman // conservative approximation. InstrEmitter does trivial coalescing 3099d7019f586719a03f3519142ca2166166962e433Dan Gohman // with CopyFromReg nodes, so don't emit kill flags for them. 3108b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // Avoid kill flags on Schedule cloned nodes, since there will be 3118b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // multiple uses. 3129d7019f586719a03f3519142ca2166166962e433Dan Gohman // Tied operands are never killed, so we need to check that. And that 3139d7019f586719a03f3519142ca2166166962e433Dan Gohman // means we need to determine the index of the operand. 3149d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isKill = Op.hasOneUse() && 3159d7019f586719a03f3519142ca2166166962e433Dan Gohman Op.getNode()->getOpcode() != ISD::CopyFromReg && 3168b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !IsDebug && 3178b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !(IsClone || IsCloned); 3189d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isKill) { 3199d7019f586719a03f3519142ca2166166962e433Dan Gohman unsigned Idx = MI->getNumOperands(); 3209d7019f586719a03f3519142ca2166166962e433Dan Gohman while (Idx > 0 && 3219d7019f586719a03f3519142ca2166166962e433Dan Gohman MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3229d7019f586719a03f3519142ca2166166962e433Dan Gohman --Idx; 323e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 3249d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isTied) 3259d7019f586719a03f3519142ca2166166962e433Dan Gohman isKill = false; 3269d7019f586719a03f3519142ca2166166962e433Dan Gohman } 32747bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman 328bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 32947bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman false/*isImp*/, isKill, 330bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isDead*/, false/*isUndef*/, 331bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isEarlyClobber*/, 332bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 0/*SubReg*/, IsDebug)); 333f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 334f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 33594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// AddOperand - Add the specified operand to the specified machine instr. II 33694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// specifies the instruction information for the node, and IIOpNum is the 3373af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick/// operand number (in the II) that we are adding. IIOpNum and II are used for 33894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// assertions only. 339bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 340bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 341e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 342bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 3438b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 34494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode()) { 3458b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3468b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 34794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 348d842962e27b10b6831c2421fa257e3fd58a85b18Chris Lattner MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 34994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3504fbd796a1251a27e6590765a0a34876f436a0af9Dan Gohman const ConstantFP *CFP = F->getConstantFPValue(); 35194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFPImm(CFP)); 35294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 353c040719a153df8202f10054f33c9ac581b1c6c57Bill Wendling MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 3549cf37e8b48732fccd4c301ed51aafed7074bd84eJakob Stoklund Olesen } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 3559cf37e8b48732fccd4c301ed51aafed7074bd84eJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask())); 35694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3576ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3586ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner TGA->getTargetFlags())); 359f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 360f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 36194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 36294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 36394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3646ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3656ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner JT->getTargetFlags())); 36694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 36794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman int Offset = CP->getOffset(); 36894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Align = CP->getAlignment(); 369db125cfaf57cc83e7dd7453de2d509bc8efd0e5eChris Lattner Type *Type = CP->getType(); 37094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // MachineConstantPool wants an explicit alignment. 37194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 372bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getPrefTypeAlignment(Type); 37394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 37494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Alignment of vector types. FIXME! 375bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getTypeAllocSize(Type); 37694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 37794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 3783af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 37994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Idx; 380bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineConstantPool *MCP = MF->getConstantPool(); 38194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (CP->isMachineConstantPoolEntry()) 382bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 38394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 384bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 3856ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 3866ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner CP->getTargetFlags())); 387056292fd738924f3f7703725d8f630983794b5a5Bill Wendling } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 38831e2c7b4c13c2f31774614b1124533628958d0cdDaniel Dunbar MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 3896ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner ES->getTargetFlags())); 3908c2b52552c90f39e4b2fed43e309e599e742b6acDan Gohman } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 39129cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 39229cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman BA->getTargetFlags())); 39394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 394825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 395f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 39629d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 3978b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3988b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 399f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 400f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 401f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 402d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesenunsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 403d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen EVT VT, DebugLoc DL) { 404d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 405d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 406d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 407d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 408d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // within reason. 409d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (RC && RC != VRC) 410d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 411d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 412d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg has been adjusted. It can be used with SubIdx operands now. 413d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (RC) 414d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen return VReg; 415d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 416d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 417d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // register instead. 418d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 419d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen assert(RC && "No legal register class for VT supports that SubIdx"); 420d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen unsigned NewReg = MRI->createVirtualRegister(RC); 421d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 422d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen .addReg(VReg); 423d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen return NewReg; 424d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen} 425d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 42694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitSubregNode - Generate machine code for subreg nodes. 42794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 4283af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trickvoid InstrEmitter::EmitSubregNode(SDNode *Node, 4298b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 4308b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 43194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 43294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Opc = Node->getMachineOpcode(); 4333af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 43494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 43594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 43694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 43794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman UI != E; ++UI) { 43894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *UI; 4393af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (User->getOpcode() == ISD::CopyToReg && 44094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node) { 44194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 44294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 44394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = DestReg; 44494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 44594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 44694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 44794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4483af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 449518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG) { 450d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 451d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // constraints on the %dst register, COPY can target all legal register 452d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // classes. 453f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 454d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); 45594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 456f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 4570b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MachineInstr *DefMI = MRI->getVRegDef(VReg); 4580b71d3972d9138c7482233bc44a9a207634769efEvan Cheng unsigned SrcReg, DstReg, DefSubIdx; 4590b71d3972d9138c7482233bc44a9a207634769efEvan Cheng if (DefMI && 4600b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 4610b71d3972d9138c7482233bc44a9a207634769efEvan Cheng SubIdx == DefSubIdx) { 4620b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Optimize these: 4630b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1025 = s/zext r1024, 4 4640b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = extract_subreg r1025, 4 4650b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // to a copy 4660b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = copy r1024 4670b71d3972d9138c7482233bc44a9a207634769efEvan Cheng VRBase = MRI->createVirtualRegister(TRC); 4680b71d3972d9138c7482233bc44a9a207634769efEvan Cheng BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 4690b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 4700b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } else { 471d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // VReg may not support a SubIdx sub-register, and we may need to 472d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // constrain its register class or issue a COPY to a compatible register 473d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // class. 474d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen VReg = ConstrainForSubReg(VReg, SubIdx, 475d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen Node->getOperand(0).getValueType(), 476d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen Node->getDebugLoc()); 477d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen 478d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen // Create the destreg if it is missing. 479d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen if (VRBase == 0) 480d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen VRBase = MRI->createVirtualRegister(TRC); 4815ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 4820b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Create the extract_subreg machine instruction. 483d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 484d2ed2d71c95462a6b14e7c7c8c82cb727ed342ebJakob Stoklund Olesen TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 4850b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } 486518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner } else if (Opc == TargetOpcode::INSERT_SUBREG || 487518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 48894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N0 = Node->getOperand(0); 48994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N1 = Node->getOperand(1); 49094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N2 = Node->getOperand(2); 491f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 4925ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 4932c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // Figure out the register class to create for the destreg. It should be 4942c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // the largest legal register class supporting SubIdx sub-registers. 4952c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // RegisterCoalescer will constrain it further if it decides to eliminate 4962c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // the INSERT_SUBREG instruction. 4972c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 4982c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst = INSERT_SUBREG %src, %sub, SubIdx 4992c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5002c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // is lowered by TwoAddressInstructionPass to: 5012c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5022c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst = COPY %src 5032c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // %dst:SubIdx = COPY %sub 5042c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5052c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // There is no constraint on the %src register class. 5062c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen // 5072c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); 5082c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 5092c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 5102c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen 5112c3bef8a15c84ad8ef043f8e8ff08ffe1b96720bJakob Stoklund Olesen if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 512bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 5135ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 51494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the insert_subreg or subreg_to_reg machine instruction. 515bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 51694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 5173af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 51894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If creating a subreg_to_reg, then the first input operand 51994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // is an implicit value immediate, otherwise it's a register 520518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::SUBREG_TO_REG) { 52194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 522f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 52394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 5248b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 5258b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 52694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the subregster being inserted 5278b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 5288b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 52994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 530bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 53194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 532c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 5333af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 53494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, 0); 53594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 5368e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 53794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 53894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 53994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 54088c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 54188c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// COPY_TO_REGCLASS is just a normal copy, except that the destination 542f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// register is constrained to be in a particular register class. 543f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// 544f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 545bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 546bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 547f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 548f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 54992c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen // Create the new VReg in the destination class and emit a copy. 550f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 551f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 552bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 55392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 55492c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen NewVReg).addReg(VReg); 555f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 556f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SDValue Op(Node, 0); 557f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 5588e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 559f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(isNew && "Node emitted out of order - early"); 560f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 561f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 562ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 563ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// 564ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Chengvoid InstrEmitter::EmitRegSequence(SDNode *Node, 5658b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 5668b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 5671300f3019e5d590231bbc3d907626708515d3212Owen Anderson unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 5681300f3019e5d590231bbc3d907626708515d3212Owen Anderson const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 569ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NewVReg = MRI->createVirtualRegister(RC); 570ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 571ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 572ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NumOps = Node->getNumOperands(); 5731300f3019e5d590231bbc3d907626708515d3212Owen Anderson assert((NumOps & 1) == 1 && 5741300f3019e5d590231bbc3d907626708515d3212Owen Anderson "REG_SEQUENCE must have an odd number of operands!"); 575e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 5761300f3019e5d590231bbc3d907626708515d3212Owen Anderson for (unsigned i = 1; i != NumOps; ++i) { 577ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op = Node->getOperand(i); 5781300f3019e5d590231bbc3d907626708515d3212Owen Anderson if ((i & 1) == 0) { 579cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 580cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper // Skip physical registers as they don't have a vreg to get and we'll 581cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper // insert copies for them in TwoAddressInstructionPass anyway. 582cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 583cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 584cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 585cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 586cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper const TargetRegisterClass *SRC = 58727e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 588cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper if (SRC && SRC != RC) { 589cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper MRI->setRegClass(NewVReg, SRC); 590cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper RC = SRC; 591cd7f02bb43ec07e0a2bd6d90177b353c94408586Pete Cooper } 5925012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng } 593ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 5948b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 5958b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 596ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 597ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 598ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MBB->insert(InsertPos, MI); 599ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op(Node, 0); 600ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 6018e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 602ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert(isNew && "Node emitted out of order - early"); 603ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng} 604ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 605bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// EmitDbgValue - Generate machine instruction for a dbg_value node. 606bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// 607891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanMachineInstr * 608891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanInstrEmitter::EmitDbgValue(SDDbgValue *SD, 609891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 610bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng uint64_t Offset = SD->getOffset(); 611bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MDNode* MDPtr = SD->getMDPtr(); 612bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DebugLoc DL = SD->getDebugLoc(); 613bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 614f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen if (SD->getKind() == SDDbgValue::FRAMEIX) { 615f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Stack address; this needs to be lowered in target-dependent fashion. 616f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // EmitTargetCodeForFrameDebugValue is responsible for allocation. 617f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen unsigned FrameIx = SD->getFrameIx(); 618962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 619f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen } 620f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Otherwise, we're going to create an instruction here. 621e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 622bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 623bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng if (SD->getKind() == SDDbgValue::SDNODE) { 624c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDNode *Node = SD->getSDNode(); 625c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDValue Op = SDValue(Node, SD->getResNo()); 626c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // It's possible we replaced this SDNode with other(s) and therefore 627c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // didn't generate code for it. It's better to catch these cases where 628c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // they happen and transfer the debug info, but trying to guarantee that 629c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // in all cases would be very fragile; this is a safeguard for any 630c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // that were missed. 631c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 632c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen if (I==VRBaseMap.end()) 633c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen MIB.addReg(0U); // undef 634c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen else 635c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 6368b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 637bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng } else if (SD->getKind() == SDDbgValue::CONST) { 63846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Value *V = SD->getConst(); 63946510a73e977273ec67747eb34cbdb43f815e451Dan Gohman if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 6408594d429e02c688d428036f8563f09572da3fbffDevang Patel if (CI->getBitWidth() > 64) 6418594d429e02c688d428036f8563f09572da3fbffDevang Patel MIB.addCImm(CI); 6424ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman else 6434ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addImm(CI->getSExtValue()); 64446510a73e977273ec67747eb34cbdb43f815e451Dan Gohman } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 645bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addFPImm(CF); 646bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } else { 647bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // Could be an Undef. In any case insert an Undef so we can see what we 648bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // dropped. 649bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 650bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } 65106a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } else { 65206a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen // Insert an Undef so we can see what we dropped. 653bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 65406a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } 655bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 656bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addImm(Offset).addMetadata(MDPtr); 657bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng return &*MIB; 65806a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen} 65906a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen 6603d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitMachineNode - Generate machine code for a target-specific node and 6613d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 66294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 6633d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 6643d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 665af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 6663d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Opc = Node->getMachineOpcode(); 6673af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 6683d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle subreg insert/extract specially 6693af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick if (Opc == TargetOpcode::EXTRACT_SUBREG || 6703d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::INSERT_SUBREG || 6713d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 6728b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 6733d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6743d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 67594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6763d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle COPY_TO_REGCLASS specially. 6773d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 6783d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyToRegClassNode(Node, VRBaseMap); 6793d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6803d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 681f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 682ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng // Handle REG_SEQUENCE specially. 683ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (Opc == TargetOpcode::REG_SEQUENCE) { 6848b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 685ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng return; 686ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 687ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 6883d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::IMPLICIT_DEF) 6893d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // We want a unique VR for each IMPLICIT_DEF use. 6903d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6913af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 692e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(Opc); 6933d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumResults = CountResults(Node); 6943d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NodeOperands = CountOperands(Node); 69547cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 69694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 6973d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumMIOperands = NodeOperands + NumResults; 69847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (II.isVariadic()) 69947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 70047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "Too few operands for a variadic node!"); 70147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner else 70247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 70347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 70447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "#operands for dag node doesn't match .td file!"); 70594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 70694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7073d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Create the new machine instruction. 7083d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 709db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman 710db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // The MachineInstr constructor adds implicit-def operands. Scan through 711db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // these to determine which are dead. 712db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (MI->getNumOperands() != 0 && 713f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 714db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // First, collect all used registers. 715db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman SmallVector<unsigned, 8> UsedRegs; 71629d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) 717db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (F->getOpcode() == ISD::CopyFromReg) 718db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 719db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman else { 720db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Collect declared implicit uses. 721e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 722e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UsedRegs.append(MCID.getImplicitUses(), 723e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCID.getImplicitUses() + MCID.getNumImplicitUses()); 724db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // In addition to declared implicit uses, we must also check for 725db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // direct RegisterSDNode operands. 726db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 727db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 728db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman unsigned Reg = R->getReg(); 729c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(Reg)) 730db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(Reg); 731db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 732db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 733db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Then mark unused registers as dead. 734db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 735db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 7363af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 7373d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Add result register values for things that are defined by this 7383d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction. 7393d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (NumResults) 7403d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 7413af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 7423d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Emit all of the actual operands of this instruction, adding them to the 7433d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction as appropriate. 7443d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner bool HasOptPRefs = II.getNumDefs() > NumResults; 7453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner assert((!HasOptPRefs || !HasPhysRegOuts) && 7463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner "Unable to cope with optional defs and phys regs defs!"); 7473d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 7483d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = NumSkip; i != NodeOperands; ++i) 7493d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 7508b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 7513d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7523d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Transfer all of the memory reference descriptions of this instruction. 7533d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 7543d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner cast<MachineSDNode>(Node)->memoperands_end()); 7553d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 75614152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // Insert the instruction into position in the block. This needs to 75714152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // happen before any custom inserter hook is called so that the 75814152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // hook knows where in the block to insert the replacement code. 75914152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman MBB->insert(InsertPos, MI); 76014152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman 761bece04845e6746fd162bc36e79a6cfd095165c23Eric Christopher // Additional results must be physical register defs. 7623d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (HasPhysRegOuts) { 7633d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 7643d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 7653d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Node->hasAnyUseOfValue(i)) 7663d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 7673d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // If there are no uses, mark the register as dead now, so that 7683d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // MachineLICM/Sink can see that it's dead. Don't do this if the 76929d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // node has a Glue value, for the benefit of targets still using 77029d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // Glue for values in physregs. 771f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 7723d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->addRegisterDead(Reg, TRI); 77394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 77494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7753af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 77647cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // If the instruction has implicit defs and the node doesn't, mark the 77729d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // implicit def as dead. If the node has any glue outputs, we don't do this 77829d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // because we don't know what implicit defs are being used by glued nodes. 779f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 78047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (const unsigned *IDList = II.getImplicitDefs()) { 78147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 78247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner i != e; ++i) 78347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 78447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner } 78537fefc20d3a1e3934a377567d54a141f67752227Evan Cheng 78637fefc20d3a1e3934a377567d54a141f67752227Evan Cheng // Run post-isel target hook to adjust this instruction if needed. 7873be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick#ifdef NDEBUG 78883a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick if (II.hasPostISelHook()) 7893be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick#endif 79083a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick TLI->AdjustInstrPostInstrSelection(MI, Node); 7913d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner} 79294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7933d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitSpecialNode - Generate machine code for a target-independent node and 7943d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 7953d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 7963d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 7973d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner DenseMap<SDValue, unsigned> &VRBaseMap) { 79894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman switch (Node->getOpcode()) { 79994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman default: 80094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 801bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Node->dump(); 80294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 803c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("This target-independent node should have been selected!"); 80494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 80594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::EntryToken: 806c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("EntryToken should have been excluded from the schedule!"); 80794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 80837b7387da90ffd42d28ad0f08fca00b684294b2cEvan Cheng case ISD::MERGE_VALUES: 80994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::TokenFactor: // fall thru 81094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 81194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyToReg: { 81294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg; 81394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue SrcVal = Node->getOperand(2); 81494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 81594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = R->getReg(); 81694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 81794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = getVR(SrcVal, VRBaseMap); 8183af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 81994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 82094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 82194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 822f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 82392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 82492c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen DestReg).addReg(SrcReg); 82594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 82694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 82794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyFromReg: { 82894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 829e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 83094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 83194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 8327561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner case ISD::EH_LABEL: { 8337561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 8347561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 8357561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner TII->get(TargetOpcode::EH_LABEL)).addSym(S); 8367561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner break; 8377561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner } 8383af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 83994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::INLINEASM: { 84094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned NumOps = Node->getNumOperands(); 841f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 84229d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner --NumOps; // Ignore the glue operand. 8433af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 84494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the inline asm machine instruction. 845bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 846518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::INLINEASM)); 84794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 84894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the asm string as an external symbol operand. 849decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 850decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 85194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateES(AsmStr)); 8523af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 853c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Add the HasSideEffect and isAlignStack bits. 854c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng int64_t ExtraInfo = 855c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 856f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen getZExtValue(); 857c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); 858f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen 85994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add all of the operand registers to the instruction. 860decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 861f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned Flags = 862f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 863697cbbfb00c318f98d6eb51945f077e2bfe8781eEvan Cheng unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 8643af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 86594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(Flags)); 86694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman ++i; // Skip the ID value. 8673af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 868decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner switch (InlineAsm::getKind(Flags)) { 869c23197a26f34f559ea9797de51e187087c039c42Torok Edwin default: llvm_unreachable("Bad flags!"); 870decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDef: 87194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) { 87294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 8733013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // FIXME: Add dead flags for physical and virtual registers defined. 8743013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // For now, mark physical register defs as implicit to help fast 8753013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // regalloc. This makes inline asm look a lot like calls. 8763013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, true, 8773013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 87894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 87994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 880decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDefEarlyClobber: 881f792fa90f1125553008659c743cba85b9b5d2e5eJakob Stoklund Olesen case InlineAsm::Kind_Clobber: 882913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen for (; NumVals; --NumVals, ++i) { 883913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 884c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 8853013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 886c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isKill=*/ false, 887c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isDead=*/ false, 888c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isUndef=*/false, 889c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isEarlyClobber=*/ true)); 890913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen } 891913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen break; 892decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegUse: // Use of register. 893decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Imm: // Immediate. 894decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Mem: // Addressing mode. 89594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // The addressing mode has been selected, just add all of the 89694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // operands to the machine instruction. 89794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) 8988b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 8998b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/false, IsClone, IsCloned); 90094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 90194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 90294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 9033af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 904cf9a415182aca6a432105a2a12168e1049de180aChris Lattner // Get the mdnode from the asm if it exists and add it to the instruction. 905cf9a415182aca6a432105a2a12168e1049de180aChris Lattner SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 906cf9a415182aca6a432105a2a12168e1049de180aChris Lattner const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 907cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson if (MD) 908cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson MI->addOperand(MachineOperand::CreateMetadata(MD)); 9093af7a67629292840f0dbae8fad4e333b009e69ddAndrew Trick 910bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 91194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 91294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 91394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 91494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 91594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 916bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 917bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// at the given position in the given block. 918bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 919bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineBasicBlock::iterator insertpos) 920bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman : MF(mbb->getParent()), 921bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MRI(&MF->getRegInfo()), 922bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TM(&MF->getTarget()), 923bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TII(TM->getInstrInfo()), 924bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TRI(TM->getRegisterInfo()), 925bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TLI(TM->getTargetLowering()), 926bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB(mbb), InsertPos(insertpos) { 92794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 928