InstrEmitter.cpp revision e837dead3c8dc3445ef6a0e2322179c57e264a13
1bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// The LLVM Compiler Infrastructure 494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// This file is distributed under the University of Illinois Open Source 694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// License. See LICENSE.TXT for details. 794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 10bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// This implements the Emit routines for the SelectionDAG class, which creates 11bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// MachineInstrs based on the decisions of the SelectionDAG instruction 12bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// selection. 1394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 1494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 1594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#define DEBUG_TYPE "instr-emitter" 17bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#include "InstrEmitter.h" 18a8efe28a44996978faa42a387f1a6087a7b942c7Evan Cheng#include "SDNodeDbgValue.h" 1994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineConstantPool.h" 2094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineFunction.h" 2194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineInstrBuilder.h" 2294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 2394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetData.h" 2494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetMachine.h" 2594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetInstrInfo.h" 2694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetLowering.h" 2794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/ADT/Statistic.h" 2894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/Debug.h" 29c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/MathExtras.h" 3194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohmanusing namespace llvm; 3294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 33bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountResults - The results of target nodes have register or immediate 3429d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// operands first, then an optional chain, and optional glue operands (which do 35bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// not go into the resulting MachineInstr). 36bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountResults(SDNode *Node) { 37bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumValues(); 38f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getValueType(N - 1) == MVT::Glue) 39bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 40bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getValueType(N - 1) == MVT::Other) 41bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Skip over chain result. 42bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 43bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 44bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 45bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountOperands - The inputs to target nodes have any actual inputs first, 4629d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner/// followed by an optional chain operand, then an optional glue operand. 47bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// Compute the number of actual operands that will go into the resulting 48bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// MachineInstr. 49bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountOperands(SDNode *Node) { 50bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumOperands(); 51f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 52bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 53bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Ignore chain if it exists. 55bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 56bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 57bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 5894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 5994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// implicit physical register output. 60bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter:: 615202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris LattnerEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 625202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris Lattner unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 6394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 6494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 6594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Just use the input register directly! 6694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 6794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 6894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 6994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 708e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 7194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 7294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return; 7394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 7694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 7794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool MatchReg = true; 781cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng const TargetRegisterClass *UseRC = NULL; 79c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen EVT VT = Node->getValueType(ResNo); 80c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 81c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen // Stick to the preferred register classes for legal types. 82c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen if (TLI->isTypeLegal(VT)) 83c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen UseRC = TLI->getRegClassFor(VT); 84c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 85e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!IsClone && !IsCloned) 86e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 87e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 88e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 89e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool Match = true; 90e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 91e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 92e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == ResNo) { 93e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 94e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 95e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng VRBase = DestReg; 96e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 97e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else if (DestReg != SrcReg) 98e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 99e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else { 100e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 101e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDValue Op = User->getOperand(i); 102e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (Op.getNode() != Node || Op.getResNo() != ResNo) 103e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 104e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(Op.getResNo()); 105f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (VT == MVT::Other || VT == MVT::Glue) 106e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 107e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 108e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->isMachineOpcode()) { 109e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 1102a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = 0; 1112a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (i+II.getNumDefs() < II.getNumOperands()) 11215993f83a419950f06d2879d6701530ae6449317Evan Cheng RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); 113e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!UseRC) 114e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UseRC = RC; 115f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman else if (RC) { 116f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 117f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // If multiple uses expect disjoint register classes, we emit 118f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // copies in AddRegisterOperand. 119f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen if (ComRC) 120f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen UseRC = ComRC; 121f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 122e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 1231cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } 12494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 125e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng MatchReg &= Match; 126e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (VRBase) 127e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng break; 12894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 12994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 13094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 131d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 132c02a6fa7d8f0ccf2e0059bc40978a466fff3fcabJakob Stoklund Olesen 13394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 13494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase) { 135bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstRC = MRI->getRegClass(VRBase); 1361cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } else if (UseRC) { 1371cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1381cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = UseRC; 13994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 1401cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = TLI->getRegClassFor(VT); 14194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 14294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 14394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If all uses are reading from the src physical register and copying the 14494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // register is either impossible or very expensive, then don't create a copy. 14594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (MatchReg && SrcRC->getCopyCost() < 0) { 14694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = SrcReg; 14794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 14894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg, emit the copy. 149bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(DstRC); 15092c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 15192c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen VRBase).addReg(SrcReg); 15294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 15394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 15494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 15594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 15694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 15794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 1588e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 15994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 16094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 16194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getDstOfCopyToRegUse - If the only use of the specified result number of 16394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// node is a CopyToReg, return its destination register. Return 0 otherwise. 164bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 165bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned ResNo) const { 16694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!Node->hasOneUse()) 16794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 16894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *Node->use_begin(); 17094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 17194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node && 17294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getResNo() == ResNo) { 17394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 17494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(Reg)) 17594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return Reg; 17694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 17794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 17894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 17994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 180bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 181e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II, 182e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool IsClone, bool IsCloned, 1835c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 184518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 18594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 18694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 18794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (unsigned i = 0; i < II.getNumDefs(); ++i) { 18894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the specific node value is only used by a CopyToReg and the dest reg 189f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // is a vreg in the same register class, use the CopyToReg'd destination 190f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // register instead of creating a new vreg. 19194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 19215993f83a419950f06d2879d6701530ae6449317Evan Cheng const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); 1938955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (II.OpInfo[i].isOptionalDef()) { 1948955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng // Optional def must be a physical register. 1958955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng unsigned NumResults = CountResults(Node); 1968955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 1978955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 1988955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 1998955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng } 200e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng 2018955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (!VRBase && !IsClone && !IsCloned) 202e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 203e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 204e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 205e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 206e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 207e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == i) { 208e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 209e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(Reg)) { 210bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 211f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (RegRC == RC) { 212f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VRBase = Reg; 213f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 214f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman break; 215f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 216e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 21794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 22094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the result registers for this node and add the result regs to 22194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the machine instruction. 22294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase == 0) { 22394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(RC && "Isn't a register operand!"); 224bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(RC); 22594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 22694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 22794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 22894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, i); 2295c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng if (IsClone) 2305c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng VRBaseMap.erase(Op); 23194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 2328e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 23394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 23494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 23594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 23694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 23794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getVR - Return the virtual register corresponding to the specified result 23894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// of the specified node. 239bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getVR(SDValue Op, 240bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 24194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode() && 242518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 24394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add an IMPLICIT_DEF instruction before every use. 24494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 245e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 24694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // does not include operand register class info. 24794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!VReg) { 24894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 249bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VReg = MRI->createVirtualRegister(RC); 25094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 2513cd26a2909cd5d002fe2742041a264ba217ba88eDan Gohman BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 252518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 25394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return VReg; 25494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 25594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 25794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 25894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return I->second; 25994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 26094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 261c040719a153df8202f10054f33c9ac581b1c6c57Bill Wendling 262f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// AddRegisterOperand - Add the specified register as an operand to the 263f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// specified machine instr. Insert register copies if the register is 264f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// not in the required register class. 265f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 266bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 267bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 268e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 269bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 2708b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 271825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 272f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 27329d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 274f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Get/emit the operand. 275f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Op, VRBaseMap); 276f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 277f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 278e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 279e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptDef = IIOpNum < MCID.getNumOperands() && 280e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCID.OpInfo[IIOpNum].isOptionalDef(); 281f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 282f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // If the instruction requires a register in a different class, create 283f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // a new virtual register and copy the value into it. 284f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (II) { 285bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 2862a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *DstRC = 0; 2872a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (IIOpNum < II->getNumOperands()) 28815993f83a419950f06d2879d6701530ae6449317Evan Cheng DstRC = TII->getRegClass(*II, IIOpNum, TRI); 289e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) && 290f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Don't have operand info for this instruction!"); 291fa226bccaa90c520cac154df74069bbabb976eabJakob Stoklund Olesen if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) { 292bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 29392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 29492c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 295f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VReg = NewVReg; 296f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 297f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 298f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 29947bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman // If this value has only one use, that use is a kill. This is a 3009d7019f586719a03f3519142ca2166166962e433Dan Gohman // conservative approximation. InstrEmitter does trivial coalescing 3019d7019f586719a03f3519142ca2166166962e433Dan Gohman // with CopyFromReg nodes, so don't emit kill flags for them. 3028b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // Avoid kill flags on Schedule cloned nodes, since there will be 3038b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman // multiple uses. 3049d7019f586719a03f3519142ca2166166962e433Dan Gohman // Tied operands are never killed, so we need to check that. And that 3059d7019f586719a03f3519142ca2166166962e433Dan Gohman // means we need to determine the index of the operand. 3069d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isKill = Op.hasOneUse() && 3079d7019f586719a03f3519142ca2166166962e433Dan Gohman Op.getNode()->getOpcode() != ISD::CopyFromReg && 3088b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !IsDebug && 3098b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman !(IsClone || IsCloned); 3109d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isKill) { 3119d7019f586719a03f3519142ca2166166962e433Dan Gohman unsigned Idx = MI->getNumOperands(); 3129d7019f586719a03f3519142ca2166166962e433Dan Gohman while (Idx > 0 && 3139d7019f586719a03f3519142ca2166166962e433Dan Gohman MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3149d7019f586719a03f3519142ca2166166962e433Dan Gohman --Idx; 315e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 3169d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isTied) 3179d7019f586719a03f3519142ca2166166962e433Dan Gohman isKill = false; 3189d7019f586719a03f3519142ca2166166962e433Dan Gohman } 31947bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman 320bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 32147bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman false/*isImp*/, isKill, 322bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isDead*/, false/*isUndef*/, 323bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isEarlyClobber*/, 324bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 0/*SubReg*/, IsDebug)); 325f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 326f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 32794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// AddOperand - Add the specified operand to the specified machine instr. II 32894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// specifies the instruction information for the node, and IIOpNum is the 32994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// operand number (in the II) that we are adding. IIOpNum and II are used for 33094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// assertions only. 331bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 332bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 333e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc *II, 334bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 3358b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsDebug, bool IsClone, bool IsCloned) { 33694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode()) { 3378b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3388b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 33994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 340d842962e27b10b6831c2421fa257e3fd58a85b18Chris Lattner MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 34194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3424fbd796a1251a27e6590765a0a34876f436a0af9Dan Gohman const ConstantFP *CFP = F->getConstantFPValue(); 34394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFPImm(CFP)); 34494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 345c040719a153df8202f10054f33c9ac581b1c6c57Bill Wendling MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 34694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3476ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3486ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner TGA->getTargetFlags())); 349f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 350f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 35194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 35294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 35394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3546ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3556ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner JT->getTargetFlags())); 35694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 35794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman int Offset = CP->getOffset(); 35894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Align = CP->getAlignment(); 35994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const Type *Type = CP->getType(); 36094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // MachineConstantPool wants an explicit alignment. 36194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 362bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getPrefTypeAlignment(Type); 36394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 36494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Alignment of vector types. FIXME! 365bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getTypeAllocSize(Type); 36694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 36994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Idx; 370bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineConstantPool *MCP = MF->getConstantPool(); 37194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (CP->isMachineConstantPoolEntry()) 372bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 37394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 374bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 3756ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 3766ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner CP->getTargetFlags())); 377056292fd738924f3f7703725d8f630983794b5a5Bill Wendling } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 37831e2c7b4c13c2f31774614b1124533628958d0cdDaniel Dunbar MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 3796ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner ES->getTargetFlags())); 3808c2b52552c90f39e4b2fed43e309e599e742b6acDan Gohman } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 38129cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 38229cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman BA->getTargetFlags())); 38394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 384825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 385f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Op.getValueType() != MVT::Glue && 38629d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner "Chain and glue operands should occur at end of operand list!"); 3878b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 3888b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsDebug, IsClone, IsCloned); 389f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 390f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 391f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 392f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 393f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// "SubIdx"'th sub-register class is the specified register class and whose 394f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// type matches the specified type. 395f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanstatic const TargetRegisterClass* 396f8c7394781f7cf27ac52ca087e289436d36844daDan GohmangetSuperRegisterRegClass(const TargetRegisterClass *TRC, 397e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson unsigned SubIdx, EVT VT) { 398f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Pick the register class of the superegister for this type 399f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 400f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman E = TRC->superregclasses_end(); I != E; ++I) 401fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 402f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return *I; 403f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(false && "Couldn't find the register class"); 404f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return 0; 40594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 40694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 40794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitSubregNode - Generate machine code for subreg nodes. 40894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 409bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::EmitSubregNode(SDNode *Node, 4108b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 4118b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 41294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 41394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Opc = Node->getMachineOpcode(); 41494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 41594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 41694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 41794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 41894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman UI != E; ++UI) { 41994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *UI; 42094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 42194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node) { 42294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 42394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 42494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = DestReg; 42594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 42694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 430518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG) { 4310bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub 432f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 43394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 43494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 435f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 4360b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MachineInstr *DefMI = MRI->getVRegDef(VReg); 4370b71d3972d9138c7482233bc44a9a207634769efEvan Cheng unsigned SrcReg, DstReg, DefSubIdx; 4380b71d3972d9138c7482233bc44a9a207634769efEvan Cheng if (DefMI && 4390b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 4400b71d3972d9138c7482233bc44a9a207634769efEvan Cheng SubIdx == DefSubIdx) { 4410b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Optimize these: 4420b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1025 = s/zext r1024, 4 4430b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = extract_subreg r1025, 4 4440b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // to a copy 4450b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // r1026 = copy r1024 4460b71d3972d9138c7482233bc44a9a207634769efEvan Cheng const TargetRegisterClass *TRC = MRI->getRegClass(SrcReg); 4470b71d3972d9138c7482233bc44a9a207634769efEvan Cheng VRBase = MRI->createVirtualRegister(TRC); 4480b71d3972d9138c7482233bc44a9a207634769efEvan Cheng BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 4490b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 4500b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } else { 4510b71d3972d9138c7482233bc44a9a207634769efEvan Cheng const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 4520b71d3972d9138c7482233bc44a9a207634769efEvan Cheng const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 4530b71d3972d9138c7482233bc44a9a207634769efEvan Cheng assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 45494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 4550b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Figure out the register class to create for the destreg. 4560b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Note that if we're going to directly use an existing register, 4570b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // it must be precisely the required class, and not a subclass 4580b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // thereof. 4590b71d3972d9138c7482233bc44a9a207634769efEvan Cheng if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 4600b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Create the reg 4610b71d3972d9138c7482233bc44a9a207634769efEvan Cheng assert(SRC && "Couldn't find source register class"); 4620b71d3972d9138c7482233bc44a9a207634769efEvan Cheng VRBase = MRI->createVirtualRegister(SRC); 4630b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } 4645ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 4650b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Create the extract_subreg machine instruction. 4660b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 4670b71d3972d9138c7482233bc44a9a207634769efEvan Cheng TII->get(TargetOpcode::COPY), VRBase); 4680bc25f40402f48ba42fc45403f635b20d90fabb3Jakob Stoklund Olesen 4690b71d3972d9138c7482233bc44a9a207634769efEvan Cheng // Add source, and subreg index 4700b71d3972d9138c7482233bc44a9a207634769efEvan Cheng AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false, 4710b71d3972d9138c7482233bc44a9a207634769efEvan Cheng IsClone, IsCloned); 4720b71d3972d9138c7482233bc44a9a207634769efEvan Cheng assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg())&& 4730b71d3972d9138c7482233bc44a9a207634769efEvan Cheng "Cannot yet extract from physregs"); 4740b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MI->getOperand(1).setSubReg(SubIdx); 4750b71d3972d9138c7482233bc44a9a207634769efEvan Cheng MBB->insert(InsertPos, MI); 4760b71d3972d9138c7482233bc44a9a207634769efEvan Cheng } 477518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner } else if (Opc == TargetOpcode::INSERT_SUBREG || 478518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 47994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N0 = Node->getOperand(0); 48094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N1 = Node->getOperand(1); 48194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N2 = Node->getOperand(2); 482f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned SubReg = getVR(N1, VRBaseMap); 483f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 484bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 4855ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman const TargetRegisterClass *SRC = 486ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 4875ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 48894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 4895ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Note that if we're going to directly use an existing register, 4905ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // it must be precisely the required class, and not a subclass 4915ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // thereof. 492bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 4935ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Create the reg 4945ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman assert(SRC && "Couldn't find source register class"); 495bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 49694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4975ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 49894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the insert_subreg or subreg_to_reg machine instruction. 499bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 50094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 50194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 50294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If creating a subreg_to_reg, then the first input operand 50394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // is an implicit value immediate, otherwise it's a register 504518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::SUBREG_TO_REG) { 50594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 506f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 50794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 5088b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 5098b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 51094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the subregster being inserted 5118b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 5128b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 51394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 514bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 51594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 516c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 51794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 51894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, 0); 51994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 5208e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 52194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 52294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 52394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 52488c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 52588c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// COPY_TO_REGCLASS is just a normal copy, except that the destination 526f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// register is constrained to be in a particular register class. 527f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// 528f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 529bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 530bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 531f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 532f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 53392c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen // Create the new VReg in the destination class and emit a copy. 534f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 535f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 536bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 53792c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 53892c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen NewVReg).addReg(VReg); 539f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 540f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SDValue Op(Node, 0); 541f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 5428e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 543f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(isNew && "Node emitted out of order - early"); 544f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 545f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 546ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 547ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// 548ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Chengvoid InstrEmitter::EmitRegSequence(SDNode *Node, 5498b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap, 5508b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman bool IsClone, bool IsCloned) { 5511300f3019e5d590231bbc3d907626708515d3212Owen Anderson unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 5521300f3019e5d590231bbc3d907626708515d3212Owen Anderson const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 553ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NewVReg = MRI->createVirtualRegister(RC); 554ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 555ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 556ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NumOps = Node->getNumOperands(); 5571300f3019e5d590231bbc3d907626708515d3212Owen Anderson assert((NumOps & 1) == 1 && 5581300f3019e5d590231bbc3d907626708515d3212Owen Anderson "REG_SEQUENCE must have an odd number of operands!"); 559e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 5601300f3019e5d590231bbc3d907626708515d3212Owen Anderson for (unsigned i = 1; i != NumOps; ++i) { 561ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op = Node->getOperand(i); 5621300f3019e5d590231bbc3d907626708515d3212Owen Anderson if ((i & 1) == 0) { 563ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 564ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 56560ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 56660ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *SRC = 56727e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 568495de3b783c239b4b3244a1e739b2a5b82561b1bBob Wilson if (SRC && SRC != RC) { 56927e4840e03a6fea9f7a36a83b09a8ab7fed1a620Evan Cheng MRI->setRegClass(NewVReg, SRC); 5705012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng RC = SRC; 5715012f9b82525121c28709ad7a2cc27818a38c213Evan Cheng } 572ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 5738b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 5748b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman IsClone, IsCloned); 575ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 576ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 577ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MBB->insert(InsertPos, MI); 578ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op(Node, 0); 579ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 5808e68c3873549ca31533e2e3e40dda3a43cb79566Jeffrey Yasskin (void)isNew; // Silence compiler warning. 581ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert(isNew && "Node emitted out of order - early"); 582ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng} 583ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 584bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// EmitDbgValue - Generate machine instruction for a dbg_value node. 585bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// 586891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanMachineInstr * 587891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanInstrEmitter::EmitDbgValue(SDDbgValue *SD, 588891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 589bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng uint64_t Offset = SD->getOffset(); 590bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MDNode* MDPtr = SD->getMDPtr(); 591bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DebugLoc DL = SD->getDebugLoc(); 592bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 593f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen if (SD->getKind() == SDDbgValue::FRAMEIX) { 594f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Stack address; this needs to be lowered in target-dependent fashion. 595f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // EmitTargetCodeForFrameDebugValue is responsible for allocation. 596f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen unsigned FrameIx = SD->getFrameIx(); 597962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 598f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen } 599f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Otherwise, we're going to create an instruction here. 600e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 601bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 602bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng if (SD->getKind() == SDDbgValue::SDNODE) { 603c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDNode *Node = SD->getSDNode(); 604c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDValue Op = SDValue(Node, SD->getResNo()); 605c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // It's possible we replaced this SDNode with other(s) and therefore 606c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // didn't generate code for it. It's better to catch these cases where 607c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // they happen and transfer the debug info, but trying to guarantee that 608c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // in all cases would be very fragile; this is a safeguard for any 609c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // that were missed. 610c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 611c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen if (I==VRBaseMap.end()) 612c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen MIB.addReg(0U); // undef 613c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen else 614c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 6158b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 616bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng } else if (SD->getKind() == SDDbgValue::CONST) { 61746510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Value *V = SD->getConst(); 61846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 6198594d429e02c688d428036f8563f09572da3fbffDevang Patel if (CI->getBitWidth() > 64) 6208594d429e02c688d428036f8563f09572da3fbffDevang Patel MIB.addCImm(CI); 6214ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman else 6224ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addImm(CI->getSExtValue()); 62346510a73e977273ec67747eb34cbdb43f815e451Dan Gohman } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 624bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addFPImm(CF); 625bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } else { 626bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // Could be an Undef. In any case insert an Undef so we can see what we 627bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // dropped. 628bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 629bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } 63006a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } else { 63106a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen // Insert an Undef so we can see what we dropped. 632bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 63306a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } 634bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 635bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addImm(Offset).addMetadata(MDPtr); 636bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng return &*MIB; 63706a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen} 63806a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen 6393d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitMachineNode - Generate machine code for a target-specific node and 6403d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 64194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 6423d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 6433d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 644af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 6453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Opc = Node->getMachineOpcode(); 6463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6473d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle subreg insert/extract specially 6483d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG || 6493d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::INSERT_SUBREG || 6503d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 6518b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 6523d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6533d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 65494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6553d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle COPY_TO_REGCLASS specially. 6563d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 6573d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyToRegClassNode(Node, VRBaseMap); 6583d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6593d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 660f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 661ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng // Handle REG_SEQUENCE specially. 662ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (Opc == TargetOpcode::REG_SEQUENCE) { 6638b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 664ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng return; 665ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 666ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 6673d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::IMPLICIT_DEF) 6683d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // We want a unique VR for each IMPLICIT_DEF use. 6693d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6703d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 671e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &II = TII->get(Opc); 6723d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumResults = CountResults(Node); 6733d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NodeOperands = CountOperands(Node); 67447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 67594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 6763d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumMIOperands = NodeOperands + NumResults; 67747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (II.isVariadic()) 67847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 67947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "Too few operands for a variadic node!"); 68047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner else 68147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 68247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 68347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "#operands for dag node doesn't match .td file!"); 68494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 68594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6863d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Create the new machine instruction. 6873d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 688db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman 689db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // The MachineInstr constructor adds implicit-def operands. Scan through 690db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // these to determine which are dead. 691db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (MI->getNumOperands() != 0 && 692f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 693db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // First, collect all used registers. 694db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman SmallVector<unsigned, 8> UsedRegs; 69529d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) 696db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (F->getOpcode() == ISD::CopyFromReg) 697db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 698db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman else { 699db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Collect declared implicit uses. 700e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 701e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng UsedRegs.append(MCID.getImplicitUses(), 702e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCID.getImplicitUses() + MCID.getNumImplicitUses()); 703db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // In addition to declared implicit uses, we must also check for 704db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // direct RegisterSDNode operands. 705db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 706db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 707db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman unsigned Reg = R->getReg(); 708c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(Reg)) 709db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman UsedRegs.push_back(Reg); 710db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 711db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 712db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman // Then mark unused registers as dead. 713db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 714db4971259ce94cea26e555e9ade82672a3581f5cDan Gohman } 7153d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7163d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Add result register values for things that are defined by this 7173d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction. 7183d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (NumResults) 7193d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 7203d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7213d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Emit all of the actual operands of this instruction, adding them to the 7223d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction as appropriate. 7233d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner bool HasOptPRefs = II.getNumDefs() > NumResults; 7243d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner assert((!HasOptPRefs || !HasPhysRegOuts) && 7253d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner "Unable to cope with optional defs and phys regs defs!"); 7263d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 7273d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = NumSkip; i != NodeOperands; ++i) 7283d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 7298b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 7303d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 7313d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Transfer all of the memory reference descriptions of this instruction. 7323d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 7333d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner cast<MachineSDNode>(Node)->memoperands_end()); 7343d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 73514152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // Insert the instruction into position in the block. This needs to 73614152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // happen before any custom inserter hook is called so that the 73714152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman // hook knows where in the block to insert the replacement code. 73814152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman MBB->insert(InsertPos, MI); 73914152b480d09c7ca912af7c06d00b0ff3912e4f5Dan Gohman 740bece04845e6746fd162bc36e79a6cfd095165c23Eric Christopher // Additional results must be physical register defs. 7413d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (HasPhysRegOuts) { 7423d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 7433d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 7443d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Node->hasAnyUseOfValue(i)) 7453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 7463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // If there are no uses, mark the register as dead now, so that 7473d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // MachineLICM/Sink can see that it's dead. Don't do this if the 74829d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // node has a Glue value, for the benefit of targets still using 74929d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // Glue for values in physregs. 750f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 7513d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->addRegisterDead(Reg, TRI); 75294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 75394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 75447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner 75547cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // If the instruction has implicit defs and the node doesn't, mark the 75629d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // implicit def as dead. If the node has any glue outputs, we don't do this 75729d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner // because we don't know what implicit defs are being used by glued nodes. 758f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 75947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (const unsigned *IDList = II.getImplicitDefs()) { 76047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 76147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner i != e; ++i) 76247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 76347cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner } 7643d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner} 76594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7663d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitSpecialNode - Generate machine code for a target-independent node and 7673d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 7683d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 7693d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 7703d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner DenseMap<SDValue, unsigned> &VRBaseMap) { 77194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman switch (Node->getOpcode()) { 77294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman default: 77394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 774bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Node->dump(); 77594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 776c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("This target-independent node should have been selected!"); 77794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 77894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::EntryToken: 779c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("EntryToken should have been excluded from the schedule!"); 78094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 78137b7387da90ffd42d28ad0f08fca00b684294b2cEvan Cheng case ISD::MERGE_VALUES: 78294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::TokenFactor: // fall thru 78394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 78494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyToReg: { 78594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg; 78694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue SrcVal = Node->getOperand(2); 78794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 78894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = R->getReg(); 78994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 79094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = getVR(SrcVal, VRBaseMap); 79194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 79294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 79394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 79494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 795f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 79692c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 79792c1f72c548e6a5e793ef19a0b04910992115b6cJakob Stoklund Olesen DestReg).addReg(SrcReg); 79894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 79994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 80094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyFromReg: { 80194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 802e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 80394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 80494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 8057561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner case ISD::EH_LABEL: { 8067561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 8077561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 8087561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner TII->get(TargetOpcode::EH_LABEL)).addSym(S); 8097561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner break; 8107561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner } 8117561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner 81294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::INLINEASM: { 81394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned NumOps = Node->getNumOperands(); 814f1b4eafbfec976f939ec0ea3e8acf91cef5363e3Chris Lattner if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 81529d8f0cae425f1bba583565227eaebf58f26ce73Chris Lattner --NumOps; // Ignore the glue operand. 81694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 81794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the inline asm machine instruction. 818bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 819518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::INLINEASM)); 82094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 82194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the asm string as an external symbol operand. 822decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 823decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 82494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateES(AsmStr)); 82594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 826c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Add the HasSideEffect and isAlignStack bits. 827c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng int64_t ExtraInfo = 828c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 829f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen getZExtValue(); 830c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); 831f1e309eb4862459a76445942ba4dafc433b6f317Dale Johannesen 83294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add all of the operand registers to the instruction. 833decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 834f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned Flags = 835f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 836697cbbfb00c318f98d6eb51945f077e2bfe8781eEvan Cheng unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 83794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 83894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(Flags)); 83994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman ++i; // Skip the ID value. 84094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 841decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner switch (InlineAsm::getKind(Flags)) { 842c23197a26f34f559ea9797de51e187087c039c42Torok Edwin default: llvm_unreachable("Bad flags!"); 843decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDef: 84494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) { 84594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 8463013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // FIXME: Add dead flags for physical and virtual registers defined. 8473013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // For now, mark physical register defs as implicit to help fast 8483013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen // regalloc. This makes inline asm look a lot like calls. 8493013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, true, 8503013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 85194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 85294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 853decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDefEarlyClobber: 854f792fa90f1125553008659c743cba85b9b5d2e5eJakob Stoklund Olesen case InlineAsm::Kind_Clobber: 855913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen for (; NumVals; --NumVals, ++i) { 856913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 857c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 8583013a2068421335304dce861dd5977e8cf43cbcaJakob Stoklund Olesen /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 859c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isKill=*/ false, 860c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isDead=*/ false, 861c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isUndef=*/false, 862c3c2517fed43457fed8c2e891556866dba5b83cfJakob Stoklund Olesen /*isEarlyClobber=*/ true)); 863913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen } 864913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen break; 865decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegUse: // Use of register. 866decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Imm: // Immediate. 867decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Mem: // Addressing mode. 86894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // The addressing mode has been selected, just add all of the 86994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // operands to the machine instruction. 87094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) 8718b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 8728b3a8f5773d799762b61adf976b9771117f0f261Dan Gohman /*IsDebug=*/false, IsClone, IsCloned); 87394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 87494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 87594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 876cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 877cf9a415182aca6a432105a2a12168e1049de180aChris Lattner // Get the mdnode from the asm if it exists and add it to the instruction. 878cf9a415182aca6a432105a2a12168e1049de180aChris Lattner SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 879cf9a415182aca6a432105a2a12168e1049de180aChris Lattner const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 880cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson if (MD) 881cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson MI->addOperand(MachineOperand::CreateMetadata(MD)); 882cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 883bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 88494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 88594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 88694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 88794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 88894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 889bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 890bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// at the given position in the given block. 891bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 892bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineBasicBlock::iterator insertpos) 893bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman : MF(mbb->getParent()), 894bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MRI(&MF->getRegInfo()), 895bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TM(&MF->getTarget()), 896bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TII(TM->getInstrInfo()), 897bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TRI(TM->getRegisterInfo()), 898bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TLI(TM->getTargetLowering()), 899bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB(mbb), InsertPos(insertpos) { 90094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 901