1//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "llvm/MC/MCSubtargetInfo.h" 11#include "llvm/MC/MCInstrItineraries.h" 12#include "llvm/MC/SubtargetFeature.h" 13#include "llvm/ADT/StringRef.h" 14#include "llvm/ADT/Triple.h" 15#include "llvm/Support/raw_ostream.h" 16#include <algorithm> 17 18using namespace llvm; 19 20MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors. 21 22void 23MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, 24 const SubtargetFeatureKV *PF, 25 const SubtargetFeatureKV *PD, 26 const SubtargetInfoKV *ProcSched, 27 const InstrStage *IS, 28 const unsigned *OC, 29 const unsigned *FP, 30 unsigned NF, unsigned NP) { 31 TargetTriple = TT; 32 ProcFeatures = PF; 33 ProcDesc = PD; 34 ProcSchedModel = ProcSched; 35 Stages = IS; 36 OperandCycles = OC; 37 ForwardingPaths = FP; 38 NumFeatures = NF; 39 NumProcs = NP; 40 41 SubtargetFeatures Features(FS); 42 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 43 ProcFeatures, NumFeatures); 44} 45 46 47/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with 48/// feature string) and recompute feature bits. 49uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { 50 SubtargetFeatures Features(FS); 51 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 52 ProcFeatures, NumFeatures); 53 return FeatureBits; 54} 55 56/// ToggleFeature - Toggle a feature and returns the re-computed feature 57/// bits. This version does not change the implied bits. 58uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { 59 FeatureBits ^= FB; 60 return FeatureBits; 61} 62 63/// ToggleFeature - Toggle a feature and returns the re-computed feature 64/// bits. This version will also change all implied bits. 65uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { 66 SubtargetFeatures Features; 67 FeatureBits = Features.ToggleFeature(FeatureBits, FS, 68 ProcFeatures, NumFeatures); 69 return FeatureBits; 70} 71 72 73const MCSchedModel * 74MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { 75 assert(ProcSchedModel && "Processor machine model not available!"); 76 77#ifndef NDEBUG 78 for (size_t i = 1; i < NumProcs; i++) { 79 assert(strcmp(ProcSchedModel[i - 1].Key, ProcSchedModel[i].Key) < 0 && 80 "Processor machine model table is not sorted"); 81 } 82#endif 83 84 // Find entry 85 SubtargetInfoKV KV; 86 KV.Key = CPU.data(); 87 const SubtargetInfoKV *Found = 88 std::lower_bound(ProcSchedModel, ProcSchedModel+NumProcs, KV); 89 if (Found == ProcSchedModel+NumProcs || StringRef(Found->Key) != CPU) { 90 errs() << "'" << CPU 91 << "' is not a recognized processor for this target" 92 << " (ignoring processor)\n"; 93 return &MCSchedModel::DefaultSchedModel; 94 } 95 assert(Found->Value && "Missing processor SchedModel value"); 96 return (const MCSchedModel *)Found->Value; 97} 98 99InstrItineraryData 100MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { 101 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); 102 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); 103} 104