ARMBaseInstrInfo.cpp revision 04ac81d5db058a3a9492e1aff1f398a8643bfda9 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMRegisterInfo.h"
20#include "ARMGenInstrInfo.inc"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39static cl::opt<bool>
40EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41               cl::desc("Enable ARM 2-addr to 3-addr conv"));
42
43ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
45    Subtarget(STI) {
46}
47
48MachineInstr *
49ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50                                        MachineBasicBlock::iterator &MBBI,
51                                        LiveVariables *LV) const {
52  // FIXME: Thumb2 support.
53
54  if (!EnableARM3Addr)
55    return NULL;
56
57  MachineInstr *MI = MBBI;
58  MachineFunction &MF = *MI->getParent()->getParent();
59  uint64_t TSFlags = MI->getDesc().TSFlags;
60  bool isPre = false;
61  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62  default: return NULL;
63  case ARMII::IndexModePre:
64    isPre = true;
65    break;
66  case ARMII::IndexModePost:
67    break;
68  }
69
70  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71  // operation.
72  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
73  if (MemOpc == 0)
74    return NULL;
75
76  MachineInstr *UpdateMI = NULL;
77  MachineInstr *MemMI = NULL;
78  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79  const TargetInstrDesc &TID = MI->getDesc();
80  unsigned NumOps = TID.getNumOperands();
81  bool isLoad = !TID.mayStore();
82  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83  const MachineOperand &Base = MI->getOperand(2);
84  const MachineOperand &Offset = MI->getOperand(NumOps-3);
85  unsigned WBReg = WB.getReg();
86  unsigned BaseReg = Base.getReg();
87  unsigned OffReg = Offset.getReg();
88  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
90  switch (AddrMode) {
91  default:
92    assert(false && "Unknown indexed op!");
93    return NULL;
94  case ARMII::AddrMode2: {
95    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97    if (OffReg == 0) {
98      if (ARM_AM::getSOImmVal(Amt) == -1)
99        // Can't encode it in a so_imm operand. This transformation will
100        // add more than 1 instruction. Abandon!
101        return NULL;
102      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104        .addReg(BaseReg).addImm(Amt)
105        .addImm(Pred).addReg(0).addReg(0);
106    } else if (Amt != 0) {
107      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112        .addImm(Pred).addReg(0).addReg(0);
113    } else
114      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116        .addReg(BaseReg).addReg(OffReg)
117        .addImm(Pred).addReg(0).addReg(0);
118    break;
119  }
120  case ARMII::AddrMode3 : {
121    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123    if (OffReg == 0)
124      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127        .addReg(BaseReg).addImm(Amt)
128        .addImm(Pred).addReg(0).addReg(0);
129    else
130      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132        .addReg(BaseReg).addReg(OffReg)
133        .addImm(Pred).addReg(0).addReg(0);
134    break;
135  }
136  }
137
138  std::vector<MachineInstr*> NewMIs;
139  if (isPre) {
140    if (isLoad)
141      MemMI = BuildMI(MF, MI->getDebugLoc(),
142                      get(MemOpc), MI->getOperand(0).getReg())
143        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144    else
145      MemMI = BuildMI(MF, MI->getDebugLoc(),
146                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
147        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148    NewMIs.push_back(MemMI);
149    NewMIs.push_back(UpdateMI);
150  } else {
151    if (isLoad)
152      MemMI = BuildMI(MF, MI->getDebugLoc(),
153                      get(MemOpc), MI->getOperand(0).getReg())
154        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155    else
156      MemMI = BuildMI(MF, MI->getDebugLoc(),
157                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
158        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159    if (WB.isDead())
160      UpdateMI->getOperand(0).setIsDead();
161    NewMIs.push_back(UpdateMI);
162    NewMIs.push_back(MemMI);
163  }
164
165  // Transfer LiveVariables states, kill / dead info.
166  if (LV) {
167    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168      MachineOperand &MO = MI->getOperand(i);
169      if (MO.isReg() && MO.getReg() &&
170          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171        unsigned Reg = MO.getReg();
172
173        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174        if (MO.isDef()) {
175          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176          if (MO.isDead())
177            LV->addVirtualRegisterDead(Reg, NewMI);
178        }
179        if (MO.isUse() && MO.isKill()) {
180          for (unsigned j = 0; j < 2; ++j) {
181            // Look at the two new MI's in reverse order.
182            MachineInstr *NewMI = NewMIs[j];
183            if (!NewMI->readsRegister(Reg))
184              continue;
185            LV->addVirtualRegisterKilled(Reg, NewMI);
186            if (VI.removeKill(MI))
187              VI.Kills.push_back(NewMI);
188            break;
189          }
190        }
191      }
192    }
193  }
194
195  MFI->insert(MBBI, NewMIs[1]);
196  MFI->insert(MBBI, NewMIs[0]);
197  return NewMIs[0];
198}
199
200bool
201ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202                                        MachineBasicBlock::iterator MI,
203                                        const std::vector<CalleeSavedInfo> &CSI,
204                                        const TargetRegisterInfo *TRI) const {
205  if (CSI.empty())
206    return false;
207
208  DebugLoc DL;
209  if (MI != MBB.end()) DL = MI->getDebugLoc();
210
211  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212    unsigned Reg = CSI[i].getReg();
213    bool isKill = true;
214
215    // Add the callee-saved register as live-in unless it's LR and
216    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217    // then it's already added to the function and entry block live-in sets.
218    if (Reg == ARM::LR) {
219      MachineFunction &MF = *MBB.getParent();
220      if (MF.getFrameInfo()->isReturnAddressTaken() &&
221          MF.getRegInfo().isLiveIn(Reg))
222        isKill = false;
223    }
224
225    if (isKill)
226      MBB.addLiveIn(Reg);
227
228    // Insert the spill to the stack frame. The register is killed at the spill
229    //
230    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231    storeRegToStackSlot(MBB, MI, Reg, isKill,
232                        CSI[i].getFrameIdx(), RC, TRI);
233  }
234  return true;
235}
236
237// Branch analysis.
238bool
239ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240                                MachineBasicBlock *&FBB,
241                                SmallVectorImpl<MachineOperand> &Cond,
242                                bool AllowModify) const {
243  // If the block has no terminators, it just falls into the block after it.
244  MachineBasicBlock::iterator I = MBB.end();
245  if (I == MBB.begin())
246    return false;
247  --I;
248  while (I->isDebugValue()) {
249    if (I == MBB.begin())
250      return false;
251    --I;
252  }
253  if (!isUnpredicatedTerminator(I))
254    return false;
255
256  // Get the last instruction in the block.
257  MachineInstr *LastInst = I;
258
259  // If there is only one terminator instruction, process it.
260  unsigned LastOpc = LastInst->getOpcode();
261  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262    if (isUncondBranchOpcode(LastOpc)) {
263      TBB = LastInst->getOperand(0).getMBB();
264      return false;
265    }
266    if (isCondBranchOpcode(LastOpc)) {
267      // Block ends with fall-through condbranch.
268      TBB = LastInst->getOperand(0).getMBB();
269      Cond.push_back(LastInst->getOperand(1));
270      Cond.push_back(LastInst->getOperand(2));
271      return false;
272    }
273    return true;  // Can't handle indirect branch.
274  }
275
276  // Get the instruction before it if it is a terminator.
277  MachineInstr *SecondLastInst = I;
278
279  // If there are three terminators, we don't know what sort of block this is.
280  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
281    return true;
282
283  // If the block ends with a B and a Bcc, handle it.
284  unsigned SecondLastOpc = SecondLastInst->getOpcode();
285  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286    TBB =  SecondLastInst->getOperand(0).getMBB();
287    Cond.push_back(SecondLastInst->getOperand(1));
288    Cond.push_back(SecondLastInst->getOperand(2));
289    FBB = LastInst->getOperand(0).getMBB();
290    return false;
291  }
292
293  // If the block ends with two unconditional branches, handle it.  The second
294  // one is not executed, so remove it.
295  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296    TBB = SecondLastInst->getOperand(0).getMBB();
297    I = LastInst;
298    if (AllowModify)
299      I->eraseFromParent();
300    return false;
301  }
302
303  // ...likewise if it ends with a branch table followed by an unconditional
304  // branch. The branch folder can create these, and we must get rid of them for
305  // correctness of Thumb constant islands.
306  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307       isIndirectBranchOpcode(SecondLastOpc)) &&
308      isUncondBranchOpcode(LastOpc)) {
309    I = LastInst;
310    if (AllowModify)
311      I->eraseFromParent();
312    return true;
313  }
314
315  // Otherwise, can't handle this.
316  return true;
317}
318
319
320unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321  MachineBasicBlock::iterator I = MBB.end();
322  if (I == MBB.begin()) return 0;
323  --I;
324  while (I->isDebugValue()) {
325    if (I == MBB.begin())
326      return 0;
327    --I;
328  }
329  if (!isUncondBranchOpcode(I->getOpcode()) &&
330      !isCondBranchOpcode(I->getOpcode()))
331    return 0;
332
333  // Remove the branch.
334  I->eraseFromParent();
335
336  I = MBB.end();
337
338  if (I == MBB.begin()) return 1;
339  --I;
340  if (!isCondBranchOpcode(I->getOpcode()))
341    return 1;
342
343  // Remove the branch.
344  I->eraseFromParent();
345  return 2;
346}
347
348unsigned
349ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350                               MachineBasicBlock *FBB,
351                               const SmallVectorImpl<MachineOperand> &Cond,
352                               DebugLoc DL) const {
353  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354  int BOpc   = !AFI->isThumbFunction()
355    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356  int BccOpc = !AFI->isThumbFunction()
357    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
358
359  // Shouldn't be a fall through.
360  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361  assert((Cond.size() == 2 || Cond.size() == 0) &&
362         "ARM branch conditions have two components!");
363
364  if (FBB == 0) {
365    if (Cond.empty()) // Unconditional branch?
366      BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
367    else
368      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
370    return 1;
371  }
372
373  // Two-way conditional branch.
374  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
377  return 2;
378}
379
380bool ARMBaseInstrInfo::
381ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
384  return false;
385}
386
387bool ARMBaseInstrInfo::
388PredicateInstruction(MachineInstr *MI,
389                     const SmallVectorImpl<MachineOperand> &Pred) const {
390  unsigned Opc = MI->getOpcode();
391  if (isUncondBranchOpcode(Opc)) {
392    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
395    return true;
396  }
397
398  int PIdx = MI->findFirstPredOperandIdx();
399  if (PIdx != -1) {
400    MachineOperand &PMO = MI->getOperand(PIdx);
401    PMO.setImm(Pred[0].getImm());
402    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
403    return true;
404  }
405  return false;
406}
407
408bool ARMBaseInstrInfo::
409SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410                  const SmallVectorImpl<MachineOperand> &Pred2) const {
411  if (Pred1.size() > 2 || Pred2.size() > 2)
412    return false;
413
414  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
416  if (CC1 == CC2)
417    return true;
418
419  switch (CC1) {
420  default:
421    return false;
422  case ARMCC::AL:
423    return true;
424  case ARMCC::HS:
425    return CC2 == ARMCC::HI;
426  case ARMCC::LS:
427    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
428  case ARMCC::GE:
429    return CC2 == ARMCC::GT;
430  case ARMCC::LE:
431    return CC2 == ARMCC::LT;
432  }
433}
434
435bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436                                    std::vector<MachineOperand> &Pred) const {
437  // FIXME: This confuses implicit_def with optional CPSR def.
438  const TargetInstrDesc &TID = MI->getDesc();
439  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
440    return false;
441
442  bool Found = false;
443  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444    const MachineOperand &MO = MI->getOperand(i);
445    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
446      Pred.push_back(MO);
447      Found = true;
448    }
449  }
450
451  return Found;
452}
453
454/// isPredicable - Return true if the specified instruction can be predicated.
455/// By default, this returns true for every instruction with a
456/// PredicateOperand.
457bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458  const TargetInstrDesc &TID = MI->getDesc();
459  if (!TID.isPredicable())
460    return false;
461
462  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463    ARMFunctionInfo *AFI =
464      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465    return AFI->isThumb2Function();
466  }
467  return true;
468}
469
470/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
471DISABLE_INLINE
472static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
473                                unsigned JTI);
474static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
475                                unsigned JTI) {
476  assert(JTI < JT.size());
477  return JT[JTI].MBBs.size();
478}
479
480/// GetInstSize - Return the size of the specified MachineInstr.
481///
482unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483  const MachineBasicBlock &MBB = *MI->getParent();
484  const MachineFunction *MF = MBB.getParent();
485  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
486
487  // Basic size info comes from the TSFlags field.
488  const TargetInstrDesc &TID = MI->getDesc();
489  uint64_t TSFlags = TID.TSFlags;
490
491  unsigned Opc = MI->getOpcode();
492  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
493  default: {
494    // If this machine instr is an inline asm, measure it.
495    if (MI->getOpcode() == ARM::INLINEASM)
496      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
497    if (MI->isLabel())
498      return 0;
499    switch (Opc) {
500    default:
501      llvm_unreachable("Unknown or unset size field for instr!");
502    case TargetOpcode::IMPLICIT_DEF:
503    case TargetOpcode::KILL:
504    case TargetOpcode::PROLOG_LABEL:
505    case TargetOpcode::EH_LABEL:
506    case TargetOpcode::DBG_VALUE:
507      return 0;
508    }
509    break;
510  }
511  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
512  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
513  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
514  case ARMII::SizeSpecial: {
515    switch (Opc) {
516    case ARM::CONSTPOOL_ENTRY:
517      // If this machine instr is a constant pool entry, its size is recorded as
518      // operand #2.
519      return MI->getOperand(2).getImm();
520    case ARM::Int_eh_sjlj_longjmp:
521      return 16;
522    case ARM::tInt_eh_sjlj_longjmp:
523      return 10;
524    case ARM::Int_eh_sjlj_setjmp:
525    case ARM::Int_eh_sjlj_setjmp_nofp:
526      return 20;
527    case ARM::tInt_eh_sjlj_setjmp:
528    case ARM::t2Int_eh_sjlj_setjmp:
529    case ARM::t2Int_eh_sjlj_setjmp_nofp:
530      return 12;
531    case ARM::BR_JTr:
532    case ARM::BR_JTm:
533    case ARM::BR_JTadd:
534    case ARM::tBR_JTr:
535    case ARM::t2BR_JT:
536    case ARM::t2TBB:
537    case ARM::t2TBH: {
538      // These are jumptable branches, i.e. a branch followed by an inlined
539      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540      // entry is one byte; TBH two byte each.
541      unsigned EntrySize = (Opc == ARM::t2TBB)
542        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543      unsigned NumOps = TID.getNumOperands();
544      MachineOperand JTOP =
545        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546      unsigned JTI = JTOP.getIndex();
547      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
548      assert(MJTI != 0);
549      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550      assert(JTI < JT.size());
551      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552      // 4 aligned. The assembler / linker may add 2 byte padding just before
553      // the JT entries.  The size does not include this padding; the
554      // constant islands pass does separate bookkeeping for it.
555      // FIXME: If we know the size of the function is less than (1 << 16) *2
556      // bytes, we can use 16-bit entries instead. Then there won't be an
557      // alignment issue.
558      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559      unsigned NumEntries = getNumJTEntries(JT, JTI);
560      if (Opc == ARM::t2TBB && (NumEntries & 1))
561        // Make sure the instruction that follows TBB is 2-byte aligned.
562        // FIXME: Constant island pass should insert an "ALIGN" instruction
563        // instead.
564        ++NumEntries;
565      return NumEntries * EntrySize + InstSize;
566    }
567    default:
568      // Otherwise, pseudo-instruction sizes are zero.
569      return 0;
570    }
571  }
572  }
573  return 0; // Not reached
574}
575
576void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
577                                   MachineBasicBlock::iterator I, DebugLoc DL,
578                                   unsigned DestReg, unsigned SrcReg,
579                                   bool KillSrc) const {
580  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
581  bool GPRSrc  = ARM::GPRRegClass.contains(SrcReg);
582
583  if (GPRDest && GPRSrc) {
584    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
585                                  .addReg(SrcReg, getKillRegState(KillSrc))));
586    return;
587  }
588
589  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
590  bool SPRSrc  = ARM::SPRRegClass.contains(SrcReg);
591
592  unsigned Opc;
593  if (SPRDest && SPRSrc)
594    Opc = ARM::VMOVS;
595  else if (GPRDest && SPRSrc)
596    Opc = ARM::VMOVRS;
597  else if (SPRDest && GPRSrc)
598    Opc = ARM::VMOVSR;
599  else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
600    Opc = ARM::VMOVD;
601  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
602    Opc = ARM::VMOVQ;
603  else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
604    Opc = ARM::VMOVQQ;
605  else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
606    Opc = ARM::VMOVQQQQ;
607  else
608    llvm_unreachable("Impossible reg-to-reg copy");
609
610  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
611  MIB.addReg(SrcReg, getKillRegState(KillSrc));
612  if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
613    AddDefaultPred(MIB);
614}
615
616static const
617MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
618                             unsigned Reg, unsigned SubIdx, unsigned State,
619                             const TargetRegisterInfo *TRI) {
620  if (!SubIdx)
621    return MIB.addReg(Reg, State);
622
623  if (TargetRegisterInfo::isPhysicalRegister(Reg))
624    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
625  return MIB.addReg(Reg, State, SubIdx);
626}
627
628void ARMBaseInstrInfo::
629storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
630                    unsigned SrcReg, bool isKill, int FI,
631                    const TargetRegisterClass *RC,
632                    const TargetRegisterInfo *TRI) const {
633  DebugLoc DL;
634  if (I != MBB.end()) DL = I->getDebugLoc();
635  MachineFunction &MF = *MBB.getParent();
636  MachineFrameInfo &MFI = *MF.getFrameInfo();
637  unsigned Align = MFI.getObjectAlignment(FI);
638
639  MachineMemOperand *MMO =
640    MF.getMachineMemOperand(MachinePointerInfo(
641                                         PseudoSourceValue::getFixedStack(FI)),
642                            MachineMemOperand::MOStore,
643                            MFI.getObjectSize(FI),
644                            Align);
645
646  // tGPR is used sometimes in ARM instructions that need to avoid using
647  // certain registers.  Just treat it as GPR here. Likewise, rGPR.
648  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
649      || RC == ARM::rGPRRegisterClass)
650    RC = ARM::GPRRegisterClass;
651
652  switch (RC->getID()) {
653  case ARM::GPRRegClassID:
654    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
655                   .addReg(SrcReg, getKillRegState(isKill))
656                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
657    break;
658  case ARM::SPRRegClassID:
659    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
660                   .addReg(SrcReg, getKillRegState(isKill))
661                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
662    break;
663  case ARM::DPRRegClassID:
664  case ARM::DPR_VFP2RegClassID:
665  case ARM::DPR_8RegClassID:
666    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
667                   .addReg(SrcReg, getKillRegState(isKill))
668                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
669    break;
670  case ARM::QPRRegClassID:
671  case ARM::QPR_VFP2RegClassID:
672  case ARM::QPR_8RegClassID:
673    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
674      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
675                     .addFrameIndex(FI).addImm(16)
676                     .addReg(SrcReg, getKillRegState(isKill))
677                     .addMemOperand(MMO));
678    } else {
679      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
680                     .addReg(SrcReg, getKillRegState(isKill))
681                     .addFrameIndex(FI)
682                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
683                     .addMemOperand(MMO));
684    }
685    break;
686  case ARM::QQPRRegClassID:
687  case ARM::QQPR_VFP2RegClassID:
688    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
689      // FIXME: It's possible to only store part of the QQ register if the
690      // spilled def has a sub-register index.
691      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
692                     .addFrameIndex(FI).addImm(16)
693                     .addReg(SrcReg, getKillRegState(isKill))
694                     .addMemOperand(MMO));
695    } else {
696      MachineInstrBuilder MIB =
697        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
698                       .addFrameIndex(FI)
699                       .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
700        .addMemOperand(MMO);
701      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
702      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
703      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
704            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
705    }
706    break;
707  case ARM::QQQQPRRegClassID: {
708    MachineInstrBuilder MIB =
709      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
710                     .addFrameIndex(FI)
711                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
712      .addMemOperand(MMO);
713    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
714    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
715    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
716    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
717    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
718    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
719    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
720          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
721    break;
722  }
723  default:
724    llvm_unreachable("Unknown regclass!");
725  }
726}
727
728unsigned
729ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
730                                     int &FrameIndex) const {
731  switch (MI->getOpcode()) {
732  default: break;
733  case ARM::STR:
734  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
735    if (MI->getOperand(1).isFI() &&
736        MI->getOperand(2).isReg() &&
737        MI->getOperand(3).isImm() &&
738        MI->getOperand(2).getReg() == 0 &&
739        MI->getOperand(3).getImm() == 0) {
740      FrameIndex = MI->getOperand(1).getIndex();
741      return MI->getOperand(0).getReg();
742    }
743    break;
744  case ARM::t2STRi12:
745  case ARM::tSpill:
746  case ARM::VSTRD:
747  case ARM::VSTRS:
748    if (MI->getOperand(1).isFI() &&
749        MI->getOperand(2).isImm() &&
750        MI->getOperand(2).getImm() == 0) {
751      FrameIndex = MI->getOperand(1).getIndex();
752      return MI->getOperand(0).getReg();
753    }
754    break;
755  case ARM::VST1q64Pseudo:
756    if (MI->getOperand(0).isFI() &&
757        MI->getOperand(2).getSubReg() == 0) {
758      FrameIndex = MI->getOperand(0).getIndex();
759      return MI->getOperand(2).getReg();
760    }
761    break;
762  case ARM::VSTMQ:
763    if (MI->getOperand(1).isFI() &&
764        MI->getOperand(2).isImm() &&
765        MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
766        MI->getOperand(0).getSubReg() == 0) {
767      FrameIndex = MI->getOperand(1).getIndex();
768      return MI->getOperand(0).getReg();
769    }
770    break;
771  }
772
773  return 0;
774}
775
776void ARMBaseInstrInfo::
777loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
778                     unsigned DestReg, int FI,
779                     const TargetRegisterClass *RC,
780                     const TargetRegisterInfo *TRI) const {
781  DebugLoc DL;
782  if (I != MBB.end()) DL = I->getDebugLoc();
783  MachineFunction &MF = *MBB.getParent();
784  MachineFrameInfo &MFI = *MF.getFrameInfo();
785  unsigned Align = MFI.getObjectAlignment(FI);
786  MachineMemOperand *MMO =
787    MF.getMachineMemOperand(
788                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
789                            MachineMemOperand::MOLoad,
790                            MFI.getObjectSize(FI),
791                            Align);
792
793  // tGPR is used sometimes in ARM instructions that need to avoid using
794  // certain registers.  Just treat it as GPR here.
795  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
796      || RC == ARM::rGPRRegisterClass)
797    RC = ARM::GPRRegisterClass;
798
799  switch (RC->getID()) {
800  case ARM::GPRRegClassID:
801    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
802                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
803    break;
804  case ARM::SPRRegClassID:
805    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
806                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
807    break;
808  case ARM::DPRRegClassID:
809  case ARM::DPR_VFP2RegClassID:
810  case ARM::DPR_8RegClassID:
811    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
812                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
813    break;
814  case ARM::QPRRegClassID:
815  case ARM::QPR_VFP2RegClassID:
816  case ARM::QPR_8RegClassID:
817    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
818      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
819                     .addFrameIndex(FI).addImm(16)
820                     .addMemOperand(MMO));
821    } else {
822      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
823                     .addFrameIndex(FI)
824                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
825                     .addMemOperand(MMO));
826    }
827    break;
828  case ARM::QQPRRegClassID:
829  case ARM::QQPR_VFP2RegClassID:
830    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
831      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
832                     .addFrameIndex(FI).addImm(16)
833                     .addMemOperand(MMO));
834    } else {
835      MachineInstrBuilder MIB =
836        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
837                       .addFrameIndex(FI)
838                       .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
839        .addMemOperand(MMO);
840      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
841      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
842      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
843            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
844    }
845    break;
846  case ARM::QQQQPRRegClassID: {
847    MachineInstrBuilder MIB =
848      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
849                     .addFrameIndex(FI)
850                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
851      .addMemOperand(MMO);
852    MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
853    MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
854    MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
855    MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
856    MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
857    MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
858    MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
859    AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
860    break;
861  }
862  default:
863    llvm_unreachable("Unknown regclass!");
864  }
865}
866
867unsigned
868ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
869                                      int &FrameIndex) const {
870  switch (MI->getOpcode()) {
871  default: break;
872  case ARM::LDR:
873  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
874    if (MI->getOperand(1).isFI() &&
875        MI->getOperand(2).isReg() &&
876        MI->getOperand(3).isImm() &&
877        MI->getOperand(2).getReg() == 0 &&
878        MI->getOperand(3).getImm() == 0) {
879      FrameIndex = MI->getOperand(1).getIndex();
880      return MI->getOperand(0).getReg();
881    }
882    break;
883  case ARM::t2LDRi12:
884  case ARM::tRestore:
885  case ARM::VLDRD:
886  case ARM::VLDRS:
887    if (MI->getOperand(1).isFI() &&
888        MI->getOperand(2).isImm() &&
889        MI->getOperand(2).getImm() == 0) {
890      FrameIndex = MI->getOperand(1).getIndex();
891      return MI->getOperand(0).getReg();
892    }
893    break;
894  case ARM::VLD1q64Pseudo:
895    if (MI->getOperand(1).isFI() &&
896        MI->getOperand(0).getSubReg() == 0) {
897      FrameIndex = MI->getOperand(1).getIndex();
898      return MI->getOperand(0).getReg();
899    }
900    break;
901  case ARM::VLDMQ:
902    if (MI->getOperand(1).isFI() &&
903        MI->getOperand(2).isImm() &&
904        MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
905        MI->getOperand(0).getSubReg() == 0) {
906      FrameIndex = MI->getOperand(1).getIndex();
907      return MI->getOperand(0).getReg();
908    }
909    break;
910  }
911
912  return 0;
913}
914
915MachineInstr*
916ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
917                                           int FrameIx, uint64_t Offset,
918                                           const MDNode *MDPtr,
919                                           DebugLoc DL) const {
920  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
921    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
922  return &*MIB;
923}
924
925/// Create a copy of a const pool value. Update CPI to the new index and return
926/// the label UID.
927static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
928  MachineConstantPool *MCP = MF.getConstantPool();
929  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
930
931  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
932  assert(MCPE.isMachineConstantPoolEntry() &&
933         "Expecting a machine constantpool entry!");
934  ARMConstantPoolValue *ACPV =
935    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
936
937  unsigned PCLabelId = AFI->createConstPoolEntryUId();
938  ARMConstantPoolValue *NewCPV = 0;
939  // FIXME: The below assumes PIC relocation model and that the function
940  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
941  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
942  // instructions, so that's probably OK, but is PIC always correct when
943  // we get here?
944  if (ACPV->isGlobalValue())
945    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
946                                      ARMCP::CPValue, 4);
947  else if (ACPV->isExtSymbol())
948    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
949                                      ACPV->getSymbol(), PCLabelId, 4);
950  else if (ACPV->isBlockAddress())
951    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
952                                      ARMCP::CPBlockAddress, 4);
953  else if (ACPV->isLSDA())
954    NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
955                                      ARMCP::CPLSDA, 4);
956  else
957    llvm_unreachable("Unexpected ARM constantpool value type!!");
958  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
959  return PCLabelId;
960}
961
962void ARMBaseInstrInfo::
963reMaterialize(MachineBasicBlock &MBB,
964              MachineBasicBlock::iterator I,
965              unsigned DestReg, unsigned SubIdx,
966              const MachineInstr *Orig,
967              const TargetRegisterInfo &TRI) const {
968  unsigned Opcode = Orig->getOpcode();
969  switch (Opcode) {
970  default: {
971    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
972    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
973    MBB.insert(I, MI);
974    break;
975  }
976  case ARM::tLDRpci_pic:
977  case ARM::t2LDRpci_pic: {
978    MachineFunction &MF = *MBB.getParent();
979    unsigned CPI = Orig->getOperand(1).getIndex();
980    unsigned PCLabelId = duplicateCPV(MF, CPI);
981    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
982                                      DestReg)
983      .addConstantPoolIndex(CPI).addImm(PCLabelId);
984    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
985    break;
986  }
987  }
988}
989
990MachineInstr *
991ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
992  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
993  switch(Orig->getOpcode()) {
994  case ARM::tLDRpci_pic:
995  case ARM::t2LDRpci_pic: {
996    unsigned CPI = Orig->getOperand(1).getIndex();
997    unsigned PCLabelId = duplicateCPV(MF, CPI);
998    Orig->getOperand(1).setIndex(CPI);
999    Orig->getOperand(2).setImm(PCLabelId);
1000    break;
1001  }
1002  }
1003  return MI;
1004}
1005
1006bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1007                                        const MachineInstr *MI1) const {
1008  int Opcode = MI0->getOpcode();
1009  if (Opcode == ARM::t2LDRpci ||
1010      Opcode == ARM::t2LDRpci_pic ||
1011      Opcode == ARM::tLDRpci ||
1012      Opcode == ARM::tLDRpci_pic) {
1013    if (MI1->getOpcode() != Opcode)
1014      return false;
1015    if (MI0->getNumOperands() != MI1->getNumOperands())
1016      return false;
1017
1018    const MachineOperand &MO0 = MI0->getOperand(1);
1019    const MachineOperand &MO1 = MI1->getOperand(1);
1020    if (MO0.getOffset() != MO1.getOffset())
1021      return false;
1022
1023    const MachineFunction *MF = MI0->getParent()->getParent();
1024    const MachineConstantPool *MCP = MF->getConstantPool();
1025    int CPI0 = MO0.getIndex();
1026    int CPI1 = MO1.getIndex();
1027    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1028    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1029    ARMConstantPoolValue *ACPV0 =
1030      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1031    ARMConstantPoolValue *ACPV1 =
1032      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1033    return ACPV0->hasSameValue(ACPV1);
1034  }
1035
1036  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1037}
1038
1039/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1040/// determine if two loads are loading from the same base address. It should
1041/// only return true if the base pointers are the same and the only differences
1042/// between the two addresses is the offset. It also returns the offsets by
1043/// reference.
1044bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1045                                               int64_t &Offset1,
1046                                               int64_t &Offset2) const {
1047  // Don't worry about Thumb: just ARM and Thumb2.
1048  if (Subtarget.isThumb1Only()) return false;
1049
1050  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1051    return false;
1052
1053  switch (Load1->getMachineOpcode()) {
1054  default:
1055    return false;
1056  case ARM::LDR:
1057  case ARM::LDRB:
1058  case ARM::LDRD:
1059  case ARM::LDRH:
1060  case ARM::LDRSB:
1061  case ARM::LDRSH:
1062  case ARM::VLDRD:
1063  case ARM::VLDRS:
1064  case ARM::t2LDRi8:
1065  case ARM::t2LDRDi8:
1066  case ARM::t2LDRSHi8:
1067  case ARM::t2LDRi12:
1068  case ARM::t2LDRSHi12:
1069    break;
1070  }
1071
1072  switch (Load2->getMachineOpcode()) {
1073  default:
1074    return false;
1075  case ARM::LDR:
1076  case ARM::LDRB:
1077  case ARM::LDRD:
1078  case ARM::LDRH:
1079  case ARM::LDRSB:
1080  case ARM::LDRSH:
1081  case ARM::VLDRD:
1082  case ARM::VLDRS:
1083  case ARM::t2LDRi8:
1084  case ARM::t2LDRDi8:
1085  case ARM::t2LDRSHi8:
1086  case ARM::t2LDRi12:
1087  case ARM::t2LDRSHi12:
1088    break;
1089  }
1090
1091  // Check if base addresses and chain operands match.
1092  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1093      Load1->getOperand(4) != Load2->getOperand(4))
1094    return false;
1095
1096  // Index should be Reg0.
1097  if (Load1->getOperand(3) != Load2->getOperand(3))
1098    return false;
1099
1100  // Determine the offsets.
1101  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1102      isa<ConstantSDNode>(Load2->getOperand(1))) {
1103    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1104    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1105    return true;
1106  }
1107
1108  return false;
1109}
1110
1111/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1112/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1113/// be scheduled togther. On some targets if two loads are loading from
1114/// addresses in the same cache line, it's better if they are scheduled
1115/// together. This function takes two integers that represent the load offsets
1116/// from the common base address. It returns true if it decides it's desirable
1117/// to schedule the two loads together. "NumLoads" is the number of loads that
1118/// have already been scheduled after Load1.
1119bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1120                                               int64_t Offset1, int64_t Offset2,
1121                                               unsigned NumLoads) const {
1122  // Don't worry about Thumb: just ARM and Thumb2.
1123  if (Subtarget.isThumb1Only()) return false;
1124
1125  assert(Offset2 > Offset1);
1126
1127  if ((Offset2 - Offset1) / 8 > 64)
1128    return false;
1129
1130  if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1131    return false;  // FIXME: overly conservative?
1132
1133  // Four loads in a row should be sufficient.
1134  if (NumLoads >= 3)
1135    return false;
1136
1137  return true;
1138}
1139
1140bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1141                                            const MachineBasicBlock *MBB,
1142                                            const MachineFunction &MF) const {
1143  // Debug info is never a scheduling boundary. It's necessary to be explicit
1144  // due to the special treatment of IT instructions below, otherwise a
1145  // dbg_value followed by an IT will result in the IT instruction being
1146  // considered a scheduling hazard, which is wrong. It should be the actual
1147  // instruction preceding the dbg_value instruction(s), just like it is
1148  // when debug info is not present.
1149  if (MI->isDebugValue())
1150    return false;
1151
1152  // Terminators and labels can't be scheduled around.
1153  if (MI->getDesc().isTerminator() || MI->isLabel())
1154    return true;
1155
1156  // Treat the start of the IT block as a scheduling boundary, but schedule
1157  // t2IT along with all instructions following it.
1158  // FIXME: This is a big hammer. But the alternative is to add all potential
1159  // true and anti dependencies to IT block instructions as implicit operands
1160  // to the t2IT instruction. The added compile time and complexity does not
1161  // seem worth it.
1162  MachineBasicBlock::const_iterator I = MI;
1163  // Make sure to skip any dbg_value instructions
1164  while (++I != MBB->end() && I->isDebugValue())
1165    ;
1166  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1167    return true;
1168
1169  // Don't attempt to schedule around any instruction that defines
1170  // a stack-oriented pointer, as it's unlikely to be profitable. This
1171  // saves compile time, because it doesn't require every single
1172  // stack slot reference to depend on the instruction that does the
1173  // modification.
1174  if (MI->definesRegister(ARM::SP))
1175    return true;
1176
1177  return false;
1178}
1179
1180bool ARMBaseInstrInfo::
1181isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
1182  if (!NumInstrs)
1183    return false;
1184  if (Subtarget.getCPUString() == "generic")
1185    // Generic (and overly aggressive) if-conversion limits for testing.
1186    return NumInstrs <= 10;
1187  else if (Subtarget.hasV7Ops())
1188    return NumInstrs <= 3;
1189  return NumInstrs <= 2;
1190}
1191
1192bool ARMBaseInstrInfo::
1193isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1194                    MachineBasicBlock &FMBB, unsigned NumF) const {
1195  return NumT && NumF && NumT <= 2 && NumF <= 2;
1196}
1197
1198/// getInstrPredicate - If instruction is predicated, returns its predicate
1199/// condition, otherwise returns AL. It also returns the condition code
1200/// register by reference.
1201ARMCC::CondCodes
1202llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1203  int PIdx = MI->findFirstPredOperandIdx();
1204  if (PIdx == -1) {
1205    PredReg = 0;
1206    return ARMCC::AL;
1207  }
1208
1209  PredReg = MI->getOperand(PIdx+1).getReg();
1210  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1211}
1212
1213
1214int llvm::getMatchingCondBranchOpcode(int Opc) {
1215  if (Opc == ARM::B)
1216    return ARM::Bcc;
1217  else if (Opc == ARM::tB)
1218    return ARM::tBcc;
1219  else if (Opc == ARM::t2B)
1220      return ARM::t2Bcc;
1221
1222  llvm_unreachable("Unknown unconditional branch opcode!");
1223  return 0;
1224}
1225
1226
1227void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1228                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1229                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1230                               ARMCC::CondCodes Pred, unsigned PredReg,
1231                               const ARMBaseInstrInfo &TII) {
1232  bool isSub = NumBytes < 0;
1233  if (isSub) NumBytes = -NumBytes;
1234
1235  while (NumBytes) {
1236    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1237    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1238    assert(ThisVal && "Didn't extract field correctly");
1239
1240    // We will handle these bits from offset, clear them.
1241    NumBytes &= ~ThisVal;
1242
1243    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1244
1245    // Build the new ADD / SUB.
1246    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1247    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1248      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1249      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1250    BaseReg = DestReg;
1251  }
1252}
1253
1254bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1255                                unsigned FrameReg, int &Offset,
1256                                const ARMBaseInstrInfo &TII) {
1257  unsigned Opcode = MI.getOpcode();
1258  const TargetInstrDesc &Desc = MI.getDesc();
1259  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1260  bool isSub = false;
1261
1262  // Memory operands in inline assembly always use AddrMode2.
1263  if (Opcode == ARM::INLINEASM)
1264    AddrMode = ARMII::AddrMode2;
1265
1266  if (Opcode == ARM::ADDri) {
1267    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1268    if (Offset == 0) {
1269      // Turn it into a move.
1270      MI.setDesc(TII.get(ARM::MOVr));
1271      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1272      MI.RemoveOperand(FrameRegIdx+1);
1273      Offset = 0;
1274      return true;
1275    } else if (Offset < 0) {
1276      Offset = -Offset;
1277      isSub = true;
1278      MI.setDesc(TII.get(ARM::SUBri));
1279    }
1280
1281    // Common case: small offset, fits into instruction.
1282    if (ARM_AM::getSOImmVal(Offset) != -1) {
1283      // Replace the FrameIndex with sp / fp
1284      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1285      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1286      Offset = 0;
1287      return true;
1288    }
1289
1290    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1291    // as possible.
1292    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1293    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1294
1295    // We will handle these bits from offset, clear them.
1296    Offset &= ~ThisImmVal;
1297
1298    // Get the properly encoded SOImmVal field.
1299    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1300           "Bit extraction didn't work?");
1301    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1302 } else {
1303    unsigned ImmIdx = 0;
1304    int InstrOffs = 0;
1305    unsigned NumBits = 0;
1306    unsigned Scale = 1;
1307    switch (AddrMode) {
1308    case ARMII::AddrMode2: {
1309      ImmIdx = FrameRegIdx+2;
1310      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1311      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1312        InstrOffs *= -1;
1313      NumBits = 12;
1314      break;
1315    }
1316    case ARMII::AddrMode3: {
1317      ImmIdx = FrameRegIdx+2;
1318      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1319      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1320        InstrOffs *= -1;
1321      NumBits = 8;
1322      break;
1323    }
1324    case ARMII::AddrMode4:
1325    case ARMII::AddrMode6:
1326      // Can't fold any offset even if it's zero.
1327      return false;
1328    case ARMII::AddrMode5: {
1329      ImmIdx = FrameRegIdx+1;
1330      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1331      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1332        InstrOffs *= -1;
1333      NumBits = 8;
1334      Scale = 4;
1335      break;
1336    }
1337    default:
1338      llvm_unreachable("Unsupported addressing mode!");
1339      break;
1340    }
1341
1342    Offset += InstrOffs * Scale;
1343    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1344    if (Offset < 0) {
1345      Offset = -Offset;
1346      isSub = true;
1347    }
1348
1349    // Attempt to fold address comp. if opcode has offset bits
1350    if (NumBits > 0) {
1351      // Common case: small offset, fits into instruction.
1352      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1353      int ImmedOffset = Offset / Scale;
1354      unsigned Mask = (1 << NumBits) - 1;
1355      if ((unsigned)Offset <= Mask * Scale) {
1356        // Replace the FrameIndex with sp
1357        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1358        if (isSub)
1359          ImmedOffset |= 1 << NumBits;
1360        ImmOp.ChangeToImmediate(ImmedOffset);
1361        Offset = 0;
1362        return true;
1363      }
1364
1365      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1366      ImmedOffset = ImmedOffset & Mask;
1367      if (isSub)
1368        ImmedOffset |= 1 << NumBits;
1369      ImmOp.ChangeToImmediate(ImmedOffset);
1370      Offset &= ~(Mask*Scale);
1371    }
1372  }
1373
1374  Offset = (isSub) ? -Offset : Offset;
1375  return Offset == 0;
1376}
1377
1378bool ARMBaseInstrInfo::
1379AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, int &CmpValue) const {
1380  switch (MI->getOpcode()) {
1381  default: break;
1382  case ARM::CMPri:
1383  case ARM::CMPzri:
1384  case ARM::t2CMPri:
1385  case ARM::t2CMPzri:
1386    SrcReg = MI->getOperand(0).getReg();
1387    CmpMask = ~0;
1388    CmpValue = MI->getOperand(1).getImm();
1389    return true;
1390  case ARM::TSTri:
1391  case ARM::t2TSTri:
1392    SrcReg = MI->getOperand(0).getReg();
1393    CmpMask = MI->getOperand(1).getImm();
1394    CmpValue = 0;
1395    return true;
1396  }
1397
1398  return false;
1399}
1400
1401static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
1402                              int CmpMask) {
1403  switch (MI.getOpcode()) {
1404    case ARM::ANDri:
1405    case ARM::t2ANDri:
1406      if (SrcReg == MI.getOperand(1).getReg() &&
1407          CmpMask == MI.getOperand(2).getImm())
1408        return true;
1409      break;
1410  }
1411
1412  return false;
1413}
1414
1415/// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1416/// comparison into one that sets the zero bit in the flags register. Update the
1417/// iterator *only* if a transformation took place.
1418bool ARMBaseInstrInfo::
1419OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1420                     int CmpValue, MachineBasicBlock::iterator &MII) const {
1421  if (CmpValue != 0)
1422    return false;
1423
1424  MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
1425  MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg);
1426  if (llvm::next(DI) != MRI.def_end())
1427    // Only support one definition.
1428    return false;
1429
1430  MachineInstr *MI = &*DI;
1431
1432  // Masked compares sometimes use the same register as the corresponding 'and'.
1433  if (CmpMask != ~0) {
1434    if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
1435      MI = 0;
1436      for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
1437           UE = MRI.use_end(); UI != UE; ++UI) {
1438        if (UI->getParent() != CmpInstr->getParent()) continue;
1439        MachineInstr &PotentialAND = *UI;
1440        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
1441          continue;
1442        SrcReg = PotentialAND.getOperand(0).getReg();
1443        MI = &PotentialAND;
1444        break;
1445      }
1446      if (!MI) return false;
1447    }
1448  }
1449
1450  // Conservatively refuse to convert an instruction which isn't in the same BB
1451  // as the comparison.
1452  if (MI->getParent() != CmpInstr->getParent())
1453    return false;
1454
1455  // Check that CPSR isn't set between the comparison instruction and the one we
1456  // want to change.
1457  MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
1458  --I;
1459  for (; I != E; --I) {
1460    const MachineInstr &Instr = *I;
1461
1462    for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1463      const MachineOperand &MO = Instr.getOperand(IO);
1464      if (!MO.isReg() || !MO.isDef()) continue;
1465
1466      // This instruction modifies CPSR before the one we want to change. We
1467      // can't do this transformation.
1468      if (MO.getReg() == ARM::CPSR)
1469        return false;
1470    }
1471  }
1472
1473  // Set the "zero" bit in CPSR.
1474  switch (MI->getOpcode()) {
1475  default: break;
1476  case ARM::ADDri:
1477  case ARM::ANDri:
1478  case ARM::t2ANDri:
1479  case ARM::SUBri:
1480  case ARM::t2ADDri:
1481  case ARM::t2SUBri:
1482    MI->RemoveOperand(5);
1483    MachineInstrBuilder(MI)
1484      .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1485    MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
1486    CmpInstr->eraseFromParent();
1487    return true;
1488  }
1489
1490  return false;
1491}
1492
1493unsigned
1494ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI,
1495                                 const InstrItineraryData *ItinData) const {
1496  if (!ItinData || ItinData->isEmpty())
1497    return 1;
1498
1499  const TargetInstrDesc &Desc = MI->getDesc();
1500  unsigned Class = Desc.getSchedClass();
1501  unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1502  if (UOps)
1503    return UOps;
1504
1505  unsigned Opc = MI->getOpcode();
1506  switch (Opc) {
1507  default:
1508    llvm_unreachable("Unexpected multi-uops instruction!");
1509    break;
1510  case ARM::VLDMQ:
1511  case ARM::VSTMQ:
1512    return 2;
1513
1514  // The number of uOps for load / store multiple are determined by the number
1515  // registers.
1516  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1517  // same cycle. The scheduling for the first load / store must be done
1518  // separately by assuming the the address is not 64-bit aligned.
1519  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1520  // is not 64-bit aligned, then AGU would take an extra cycle.
1521  // For VFP / NEON load / store multiple, the formula is
1522  // (#reg / 2) + (#reg % 2) + 1.
1523  case ARM::VLDMD:
1524  case ARM::VLDMS:
1525  case ARM::VLDMD_UPD:
1526  case ARM::VLDMS_UPD:
1527  case ARM::VSTMD:
1528  case ARM::VSTMS:
1529  case ARM::VSTMD_UPD:
1530  case ARM::VSTMS_UPD: {
1531    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1532    return (NumRegs / 2) + (NumRegs % 2) + 1;
1533  }
1534  case ARM::LDM_RET:
1535  case ARM::LDM:
1536  case ARM::LDM_UPD:
1537  case ARM::STM:
1538  case ARM::STM_UPD:
1539  case ARM::tLDM:
1540  case ARM::tLDM_UPD:
1541  case ARM::tSTM_UPD:
1542  case ARM::tPOP_RET:
1543  case ARM::tPOP:
1544  case ARM::tPUSH:
1545  case ARM::t2LDM_RET:
1546  case ARM::t2LDM:
1547  case ARM::t2LDM_UPD:
1548  case ARM::t2STM:
1549  case ARM::t2STM_UPD: {
1550    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1551    if (Subtarget.isCortexA8()) {
1552      // 4 registers would be issued: 1, 2, 1.
1553      // 5 registers would be issued: 1, 2, 2.
1554      return 1 + (NumRegs / 2);
1555    } else if (Subtarget.isCortexA9()) {
1556      UOps = (NumRegs / 2);
1557      // If there are odd number of registers or if it's not 64-bit aligned,
1558      // then it takes an extra AGU (Address Generation Unit) cycle.
1559      if ((NumRegs % 2) ||
1560          !MI->hasOneMemOperand() ||
1561          (*MI->memoperands_begin())->getAlignment() < 8)
1562        ++UOps;
1563      return UOps;
1564    } else {
1565      // Assume the worst.
1566      return NumRegs;
1567    }
1568  }
1569  }
1570}
1571