| 519daf5d2dd80614ac4e529b199e6f3e595bfc80 |
|
10-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't attempt to use flags from predicated instructions.
The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.
Don't do that if the sub is predicated - the flags are not written
unconditionally.
<rdar://problem/12263428>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163535 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 098c6a547fe540b3bbace4c3d4713f400c67b8a9 |
|
06-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7bebddf55ece46995f310d79195afb4e5b239886 |
|
05-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Strip old MachineInstrs *after* we know we can put them back.
Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 89f49808ee79eebbc3267b6c595514d4ca1f3247 |
|
01-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Limit domain conversion to cases where it won't break dep chains.
NEON domain conversion was too heavy-handed with its widened
registers, which could have stripped existing instructions of their
dependency, leaving them vulnerable to scheduling errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c4a32e6596f3974a6c00322db1f5f31ea448bd58 |
|
30-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Add support for moving pure S-register to NEON pipeline if desired
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 20599ea4bced03634a54b52e98d261018366f279 |
|
29-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Refactor setExecutionDomain to be clearer about what it's doing and more robust.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7611a88b58e0a6960cdb5c72dc18a6c93e44cdc2 |
|
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup sloppy code. Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f26e43df26bb7b0c7bf4853477e36611e2c90dea |
|
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARM vector copies of overlapping register tuples.
I have tested the fix, but have not been successfull in generating
a robust unit test. This can only be exposed through particular
register assignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d79dedd458c1de07fbc568ea8c3b4194e94df48e |
|
29-Aug-2012 |
Andrew Trick <atrick@apple.com> |
cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cff9baa95273bc279bf5fadb9e27afbd25cca20b |
|
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| dd364419ee64cd5bb234af006ce0cb285e4a84ca |
|
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 47aa9a2bb521994509d21179b968471531986eed |
|
28-Aug-2012 |
Bill Wendling <isanbard@gmail.com> |
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 53799048071ad5746fcbc2dca55cdcf5c5593870 |
|
21-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a missing def flag.
*** Bad machine code: Explicit definition marked as use ***
- function: test_cos
- basic block: BB#0 L.entry (0x7ff2a2024fd0)
- instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def>
- operand 0: %D11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a7fb3f68047556a7355e1f1080fb3d1ca9eb7078 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid folding ADD instructions with FI operands.
PEI can't handle the pseudo-instructions. This can be removed when the
pseudo-instructions are replaced by normal predicated instructions.
Fixes PR13628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3c8ad92455ff06c8e69085702ef1f13944eab4dd |
|
17-Aug-2012 |
Tim Northover <Tim.Northover@arm.com> |
Implement NEON domain switching for scalar <-> S-register vmovs on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 083b48af14c8bfa0e96f63ebc889704d09655fd4 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ADD and SUB to the predicable ARM instructions.
It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.
Then the pseudo-instructions can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 053b5b0b3c34d4763511b6dcd8e0150f8e9dd083 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle ARM MOVCC optimization in PeepholeOptimizer.
Use the target independent select analysis hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2860b7ea3a1d60213ee7228bd274bc4f8b170772 |
|
16-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.
This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 161474d198d44ab505861c1ec55f022b27314b35 |
|
04-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack stuff
(this corresponds by spilling/reloading regs in DTriple / DQuad reg classes).
No testcase, found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b58d7d03125526c152ade0c75be302b3c9eab997 |
|
04-Aug-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add stack spill / reload instructions for DTriple and DQuad register classes, which
were missed for no reason. This fixes PR13377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
|
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9af64303fa887a3d9b75e715787ba587c3f18139 |
|
12-Jul-2012 |
Manman Ren <mren@apple.com> |
ARM: fix typo in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 45ed19499b8f7025d9acf91cc37fbf6ea63abc4f |
|
12-Jul-2012 |
Manman Ren <mren@apple.com> |
ARM: Fix optimizeCompare to correctly check safe condition.
It is safe if CPSR is killed or re-defined.
When we are done with the basic block, check whether CPSR is live-out.
Do not optimize away cmp if CPSR is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 14ccc7b963861a856b593cc4fff62decd8ce248a |
|
02-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Revert accidental checkin.
My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 218ee74a011c0d350099c452810da0bd57a15047 |
|
02-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 76c6ccbd4cee0637c961e32435177ab89e931fed |
|
30-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: Clean up optimizeCompare in peephole, no functional change.
Use getUniqueVRegDef.
Replace a loop with existing interfaces: modifiesRegister and readsRegister.
Factor out code into inline functions and simplify the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| de7266c611b37ec050efb53b73166081a98cea13 |
|
29-Jun-2012 |
Manman Ren <mren@apple.com> |
Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare
instructions with two register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3e4b3b9043b1ced24e07d8d1174feeee06c6912e |
|
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0d9513c74f3e4c019406273cce49e43508dc4dcf |
|
29-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Make NumMicroOps a variable in the subtarget's instruction itinerary.
The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.
Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d096479f31eb51bcbd418b6e852a34210141d80e |
|
27-Jun-2012 |
Evan Cheng <evan.cheng@apple.com> |
Add a missing check to avoid dereference null. No sensible test case possible. Sorry. rdar://11745134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 540cda34b03388b510ded4546acfc7e276700daa |
|
25-Jun-2012 |
Manman Ren <mren@apple.com> |
ARM: update peephole optimization.
More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".
rdar: 11725965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e2b32bb20ee76f24708b3c9e19b6fbc651c25637 |
|
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM scheduling fix: don't guess at implicit operand latency.
This is a minor drive-by fix with no robust way to unit test.
As an example see neon-div.ll:
SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill>
val SU(1): Latency=2 Reg=%Q8
...should be latency=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ef2d9e59aba381c42e018df9c26f9025c1995a64 |
|
22-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM scheduling fix: compute predicated implicit use properly.
Minor drive by fix to cleanup latency computation. Calling
getOperandLatency with a deliberately incorrect operand index does not
give you the latency you want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 397f4e3583b36b23047fec06b1648f0771cd6fe3 |
|
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 68b16541cc58411c7b0607ca4c0fb497222b668d |
|
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM getOperandLatency rewrite.
Match expectations of the new latency API. Cleanup and make the logic consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f377071bf8393d35797107c753da3e84aea94ebe |
|
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
ARM getOperandLatency should return -1 for unknown, consistent with API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ed7a51e69209af87f3749d5f95740f69a1dc7711 |
|
07-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Fix ARM getInstrLatency logic to work with the current API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b7e0289fb320c8440ba5eed121a8b932dbd806a2 |
|
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cd2859eef83708c00330c94f6842499b48d5ed02 |
|
24-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9cc178726f323fb859acd7f8fc657a939fe96566 |
|
14-May-2012 |
David Blaikie <dblaikie@gmail.com> |
Fix use of uninitialized variable.
Found by GCC's maybe-uninitialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4949e98cccb98abb0ba3f67c22be757d446ab108 |
|
11-May-2012 |
Manman Ren <mren@apple.com> |
Add space before an open parenthesis in control flow statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 247c5ab07c1c136f37f5ad8ade9a1ee086ca452e |
|
11-May-2012 |
Manman Ren <mren@apple.com> |
ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| fe65d98dadbedf2650266ac71c1c093c3b97da1f |
|
10-May-2012 |
Manman Ren <mren@apple.com> |
Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
This commit broke an external linux bot and gave a compile-time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8ae4f062e4aefe60732b3fc135769aaedddf082d |
|
10-May-2012 |
Manman Ren <mren@apple.com> |
ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c5041cac7d3aeaa7350abadf2a7ada92e8da27dc |
|
04-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.
<rdar://problem/11182914>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 85bdf2e76a0351468f231f48069c64bc6938f140 |
|
29-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle register copies for the new ARM register classes.
ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.
No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.
<rdar://problem/11147997>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5b2f9136644c58ae32e00d8317540692a697d1c9 |
|
28-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Spill DPair registers, not just QPR.
The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.
This fixes PR12389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e279f5953e9c3d934248cd4d2f24b6179ad9d2e6 |
|
27-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
ARM has a peephole optimization which looks for a def / use pair. The def
produces a 32-bit immediate which is consumed by the use. It tries to
fold the immediate by breaking it into two parts and fold them into the
immmediate fields of two uses. e.g
movw r2, #40885
movt r3, #46540
add r0, r0, r3
=>
add.w r0, r0, #3019898880
add.w r0, r0, #30146560
;
However, this transformation is incorrect if the user produces a flag. e.g.
movw r2, #40885
movt r3, #46540
adds r0, r0, r3
=>
add.w r0, r0, #3019898880
adds.w r0, r0, #30146560
Note the adds.w may not set the carry flag even if the original sequence
would.
rdar://11116189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0e5233a9e5ee9385c6a940e3985194d77bee0bbb |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3247af294996ff8588077c06505b64966ad41542 |
|
06-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add <imp-def> operands when reloading into physregs.
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register. When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| fce711cb65716f86b4e150f42cbb597bbecf7dbe |
|
04-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use <def,undef> operands when spilling NEON bundles.
MachineOperands that define part of a virtual register must have an
<undef> flag if they are not intended as read-modify-write operands.
The old trick of adding an <imp-def> operand doesn't work any longer.
Fixes PR12177.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c01810eeb7227010f73cb39e3c4fa0197a3c4ef0 |
|
29-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM implement TargetInstrInfo::getNoopForMachoTarget()
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 209600bb8830036f981238494ab0188c25364837 |
|
22-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clarify ARM calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151113 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a1aa8db51715bdd21770fbe4f7d7abf2c5d28829 |
|
22-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Calls don't really change the stack pointer.
Even if a call instruction has %SP<imp-def> operands, it doesn't change
the value of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2420b558de5d291d8503c1339004e5b5bf99a48a |
|
17-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle regmask operands in ARMInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8c3b87cf19df5631125254784d57446b80e12397 |
|
17-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix ARMBaseInstrInfo::getInstrLatency for calls.
Calls always clobber CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| dc7c716a1cfc27a12f3bbfa44bd80904ee782779 |
|
05-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
DefinesPredicate should only look for def operands. Patch by Ludwig Meier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7255a4e1332ccb69918ebe041dff05f9e4e5815d |
|
05-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Reapply r146997, "Heed spill slot alignment on ARM."
Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.
It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.
<rdar://problem/10625436>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6d5b7cc235e284130350045a320426afceb82874 |
|
03-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r146997, "Heed spill slot alignment on ARM."
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.
<rdar://problem/10625436>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 52346e964ff1108729c2b8990b859c10f09a1822 |
|
20-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Heed spill slot alignment on ARM.
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 020f4106f820648fd7e91956859844a80de13974 |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ddfd1377d2e4154d44dc3ad217735adc15af2e3f |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
|
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6fbea43b0b35e2a3f6f91a92edeffa873c5cd794 |
|
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
|
06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d25c27807ef6b3d80ffa218b1fa5441fe40d3ce6 |
|
06-Dec-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 096334e25ea68ac970942ecb680a82fbb8ad206c |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 all lanes, with writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3805d85e38c29d9106c758b63851eb847201f315 |
|
16-Nov-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Enable -widen-vmovs by default.
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 978e0dfe46e481bfb1281e683aa308329e879e95 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 399cdca4d201f7232126c3a0643669971ede780a |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b36e03d987c843ccb731627ffd2b1db17bd72e39 |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 10b90a9bbf7dcae1568c03a03f9606f5395f2144 |
|
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 90b7b12f012d9234488277a323231e0b7a8d12ac |
|
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1c062c24aba08962b4687f56b274f182e5b7a8e5 |
|
12-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix -widen-vmovs liveness issues.
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 142bd1a54e93f3f66d420717ecba53539a556035 |
|
11-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3320f2a3bfd4daec23ba7ceb50525140cc6316da |
|
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the ARMConstantPoolMBB class to handle the MBB values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| fe31e673506ef9a1080eaa684b43b34178c6f447 |
|
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Use the new ARMConstantPoolSymbol class to handle external symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5bb779976a7d8e48408051ec2289fe69206dc072 |
|
01-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Switch over to using ARMConstantPoolConstant for global variables, functions,
and block addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e00897c5a91febe90ba21082fc636be892bf9bf1 |
|
30-Sep-2011 |
Bill Wendling <isanbard@gmail.com> |
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868 |
|
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use ExecutionDepsFix instead of NEONMoveFix.
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 13fd601e0f1c6d8558c4c2b027dacd148f19e6af |
|
28-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement TII::get/setExecutionDomain() for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
|
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e23dc9c0ef50b0a1934c04c1786f3a0478d62f41 |
|
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 112fb73502d54dd7dd61ae2de24c92d4df181294 |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix an ambiguously nested if.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 61545829832ba0375249c42c84843d0b62c8f55f |
|
31-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Put VMOVS widening under a command line option, off by default.
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cefe4c9c483d8a50ff13f36881090ab44ec67f13 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| fea95c6bade86fcfa5bd07efdda9bd902f53be8c |
|
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
Remove the VMOVQQ pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ac3656ed7a67eaacb8d2c62e1841ed4df799f72a |
|
20-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add <imp-def> operands to QQ and QQQQ stack loads.
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e5038e191db82d4d92fdeec1b5bce5cae21f6d8f |
|
20-Aug-2011 |
Chad Rosier <mcrosier@apple.com> |
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e66ef2d5f54391e53d2c0febb1ef854d060716f0 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c70c2cafe19d90ee0230cc4257772fe68567f06e |
|
10-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Promote VMOVS to VMOVD when possible.
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 36ee0e640554b8cc6ad1658fc3049e05d9967160 |
|
08-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
They improve the verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 92a202213bb4c20301abf6ab64e46df3695e60bf |
|
21-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 43967a97cf9a296623e1cf5ed643e2f40b7e5766 |
|
15-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 16884415db751c75f2133bd04921393c792b1158 |
|
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f81b7f6069b27c0a515070dcb392f6828437412f |
|
10-Jul-2011 |
Jakub Staszak <jstaszak@apple.com> |
Use BranchProbability instead of floating points in IfConverter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 74472b4bf963c424da04f42dffdb94c85ef964bc |
|
29-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Refactor away tSpill and tRestore pseudos in ARM backend.
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d7d030a44796adc73a6eaa939cd17e52047734c1 |
|
29-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 75b41f1540f35ef0fd5e4a52c1840f1a19debb03 |
|
19-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1 |
|
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
a case involving EOR, so I only added a test for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b485de5d8c3fe0c62c0b07f63f64bd10f6803c17 |
|
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
The AND instruction leaves the V flag unmodified, so it falls victim to the same
problem as all of the other instructions we fold with CMPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f |
|
15-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add missing register forms of instructions to the ARM CMP-folding code. This
fixes <rdar://problem/9287901>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5 |
|
13-Apr-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| df298c9ea64eb335f63fc075d8ef6306682ffe75 |
|
07-Apr-2011 |
Owen Anderson <resistor@mac.com> |
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 848b0c39b11801614c47e460248b60e8d40eb257 |
|
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d700617193f3d11deb83cd56c4ababbc8e0ea19f |
|
24-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2c339156289d8398bea09c2bb4b735d00d39bdb3 |
|
23-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Cmp peephole optimization isn't always safe for signed arithmetics.
int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.
rdar://9172742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 53519f015e3e84e9f57b677cc8724805a6009b73 |
|
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4 |
|
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.
Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.
Generalized unit tests to work with sched-cycles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d7e3cc840b81b0438e47f05d9664137a198876df |
|
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
|
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 |
|
17-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c9df025e33ac435adb3b3318d237c36ca7cec659 |
|
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 55d42003368c57d3a41c5f464d39b8440050d558 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4711d5cda37fc4a756f83fc1090e85ec9302c52f |
|
14-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 97a884d602538705644e296a57a039959cdb6f6e |
|
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
possible. They were duplicates for everything exception the source pattern
before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b |
|
05-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d092a87ba3f905a6801a0bdf816267329cf0391c |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cd775ceff0b25a0b026f643a7990c2924bd310a3 |
|
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move callee-saved regs spills / reloads to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8b3ca6216d62bf3f729c2e122dcfeb7c4d7500dc |
|
18-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Rewrite stack callee saved spills and restores to use push/pop instructions.
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.
Adjust all testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5c71c7a13715ed6f5bfdd5497172ddec316b68b0 |
|
18-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c4af4638dfdab0dc3b6257276cfad2ee45053060 |
|
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3642e64c114e636548888c72c21ae023ee0121a7 |
|
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Simplify code that toggle optional operand to ARM::CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| eb96a2f6c03c0ec97c56a3493ac38024afacc774 |
|
15-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code clean up. The peephole pass should be the one updating the instruction
iterator, not TII->OptimizeCompareInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6c50119ba33bf22885d2229726c809539a85c247 |
|
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Revert this temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 391f228e7e00f62b79ad483b801f5f58f046b7ea |
|
11-Nov-2010 |
Eric Christopher <echristo@apple.com> |
Change the prologue and epilogue to use push/pop for the low ARM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 40a5eb18b031fa1a5e9697e21e251e613d441cc5 |
|
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e09206d4d7683e2a421104c5cb83f7808ba4b06e |
|
30-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix fpscr <-> GPR latency info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 089751535d6e9adf65842e2ca5867bf9a70e1e95 |
|
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7e2fe9150f905167f6685c9730911c2abc08293c |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9e08ee5d16b596078e20787f0b5f36121f099333 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0104d9de04f5620ad9f837efbd3d82f31c6ff451 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7e3383c007f53b3a00675af225e428cb66ddf404 |
|
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 063efbf569e46776093ddf50099c98fdbb362167 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 77aee8e22c36257716c2df2f275724765704f20c |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c1d30212e911d1e55ff6b25bffefb503708883c3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0ae |
|
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use instruction itinerary to determine what instructions are 'cheap'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 19e57025d458d3cb50804fd821fd89b868a819bd |
|
23-Oct-2010 |
Chandler Carruth <chandlerc@gmail.com> |
Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| dd9dd6f857604abdeb5213648ffe50c10ccc59b9 |
|
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Latency between CPSR def and branch is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2312842de0c641107dd04d7e056d02491cc781ca |
|
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 98694138025fdb0cec0cda5727201ad00ded3d63 |
|
19-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 11e8b74a7ae9ecd59b64180a59143e39bc3b9514 |
|
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b41ee96d76ccf1eec2fd898def4cfd7c16868708 |
|
18-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't recompute MachineRegisterInfo in the Optimize* method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0aa38b9381a5be42abd4f5ca5baa8c2930d148d3 |
|
09-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Check to make sure that the iterator isn't at the beginning of the basic block
before decrementing. <rdar://problem/8529919>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 344d9db97062736cd66da6c07baa9108b6cfa419 |
|
08-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5a50ceeaea980962c1982ad535226c7ab06c971c |
|
07-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3c38f96af2a5443d9f72fd078c2c98dd08746e51 |
|
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a0792de66c8364d47b0a688c7f408efb7b10f31b |
|
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f000a7a212590bfd45e23c05bff5e1b683d25dd6 |
|
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
fix MSVC 2010 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2bbb76909126db5bed6bde84b16d94ab5de4d372 |
|
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Cleanup Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e |
|
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 00d4f48168eae664e1f8fefc17a912c05b878513 |
|
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b3c04ec956247a984b3113a01cfbfad91e5ca5b3 |
|
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Temporarily add a flag to make it easier to compare the new-style ARM if
conversion heuristics to the old-style ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 05642a3eba3f35aa8fdf6aa16d87561560e60af3 |
|
29-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
added some doxygen on the way
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 654d5440a477b1f6c89b051107e041a331f78e27 |
|
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b20b85168c0e9819e6545f08281e9b83c82108f0 |
|
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a99c3e9acd95f5fbfb611e3f807240cd74001142 |
|
28-Sep-2010 |
Eric Christopher <echristo@apple.com> |
80-col fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 676e258366dd17a0b4ee6ac66914237ce181202e |
|
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 108c8724663354050dc09bb1262c3e4511adf82f |
|
23-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
If there are multiple unconditional branches terminating a block, eliminate all
but the first one. Those will never be executed. There was logic to do this
but it was faulty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 691e64a54ce899409abe7c131d15ed75e3c1fef5 |
|
22-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8ff9bb189ce188452e6cae6ed65cb2745814126c |
|
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Fix buglet when the TST instruction directly uses the AND result.
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 04ac81d5db058a3a9492e1aff1f398a8643bfda9 |
|
21-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 06f264e504d75f0426eea55b9f9e36c780d8a4fc |
|
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remember VLDMQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 31bbc51ac9245bc82c933c9db8358ca9bb558ac5 |
|
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d64816a8d04e5b20b7a0628bc1f22607c07e8f69 |
|
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3a951829fef6a2cfca87611e94cf48e0136f81d5 |
|
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7602993f2dc0a33d04cf5582cdf0cf515896ea7c |
|
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 34327856d92d027733524b9418bd188a9e8db5db |
|
15-Sep-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 064312de8641043b084603aa9a6b409bc794eed2 |
|
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 168f382dc67e5940cabdb28dc933c4f91cdd3137 |
|
15-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 308f64a7c847821a4260da673089e7b4af74e56c |
|
15-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| de90bfd14af1a850ec43438d9cfffeb83f50a5a1 |
|
14-Sep-2010 |
Gabor Greif <ggreif@gmail.com> |
Eliminate a 'tst' that immediately follows an 'and'
by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a65568676d0d9d53dd4aae8f1c58271bb4cfff10 |
|
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename ConvertToSetZeroFlag to something more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3665661a5708c8adc2727be38b56d1d87ddeb661 |
|
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
No need to recompute the SrcReg and CmpValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 92ad57f066e9f256e4e3d72febf152e68caa80c7 |
|
11-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Move some of the decision logic for converting an instruction into one that sets
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 220e240bdf3235252c2a1fc8fcc5d4b8e8117918 |
|
10-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
Modify the comparison optimizations in the peephole optimizer to update the
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 51f5b67395780b8421f4aa6ee998ed51b23dae9d |
|
10-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113637 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5f54ce347368105260be2cec497b6a4199dc5789 |
|
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 707fb648d2b7ac8d206a20c9f02d631647e3b0ed |
|
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
remove obsolete comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0cfcf93c95af91e809ef740eb0ab368477226b40 |
|
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
correct spill code to properly determine if dynamic stack realignment is
present in the function and thus whether aligned load/store instructions can
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d4bfd54ec2947e73ab152c3c548e4dd4beb700ba |
|
28-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ad422718f9b3224234f52e84d28d8a57a4e89987 |
|
18-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor simplification. Gets rid of a needless temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 38ae997e63e3e1bb2c8679e01ea74cf8fd0be893 |
|
11-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 75486dbf4e9611f2070bf13b874f78a5587ed7ff |
|
10-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c98af3370f899a0d1570b1dff01a2e36632f884f |
|
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e4ddbdfd3cf031034020671d03626f0373fbd5ca |
|
06-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6ccfc507dc1f7ad8c8964193a2407264ca644f0d |
|
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4dbbe3433f7339ed277af55037ff6847f484e5ab |
|
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
prune #includes a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
|
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
|
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 600f171486708734e2b9c9c617528cfc51c16850 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ac2736670034e8942939b9fccf8e4618a0bda908 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1f32340d95ac480bfc74bcfd00fd5cffbe078652 |
|
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8190173350f4e4d916d2307278955b133fba8a00 |
|
08-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f967ca0eaf30325cabe3c1971bf0dba16cf1b027 |
|
06-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Represent NEON load/store alignments in bytes, not bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a5e82a5748763eba327176def083eec688eb4d6b |
|
06-Jul-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
|
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
|
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 57bb3948034436a458f5ef857eb2e831a47e7401 |
|
25-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
IT instructions are considered to be scheduling hazards, but are scheduled
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4b722108e2cf8e77157e0879a23789cd44829933 |
|
24-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
We are missing opportunites to use ldm. Take code like this:
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ebe99b2c198ec08c5e4a032ec0afb0345c747706 |
|
18-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rewrite chained if's as switches and replace assertions with llvm_unreachable
(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
|
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6470a116f17b70aba0c2e7ee751551a5ac9797f6 |
|
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 14f1d4e74bd52b044a2c2bb6dd8df20b0480e633 |
|
15-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 99405df044f2c584242e711cc9023ec90356da82 |
|
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
|
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
|
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9edf7deb37f0f97664f279040fa15d89f32e23d9 |
|
03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 42d075c4fb21995265961501cec9ff6e3fb497ce |
|
02-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0798eddd07b8dc827a4e6e9028c4c3a8d9444286 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Update the saved stack pointer in the sjlj function context following either
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 558661d2718cf5750907c449d36ff1231924a2d1 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
|
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5eb195153950bc7ebfc30649494a78b2096b5ef8 |
|
22-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 22c687b6421d9cc03351ddb0c7fd3d45382bc01a |
|
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 69b9f9883e10efa266d59a5dd2f4d99de92c6707 |
|
13-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 435d4991779d6a47cadff4ea670b490d8507d6c4 |
|
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 07a6d9391c74117ae79f832fd840deacab737b40 |
|
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c10b5afbe8138b0fdf3af4ed3e1ddf96cf3cb4cb |
|
07-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b63387afc6b10e88631d1ef232c41ab6c18c8581 |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1ef7c821287cd7734efb148aa3044de3e3e377a7 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f865cb5c1f00d5655d981503ed5761b2836fa5a8 |
|
06-May-2010 |
Eric Christopher <echristo@apple.com> |
Revert r103156 since it was breaking the build bots.
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9c35ee2099108c43a02aa1f836c3cbf5a0cd6035 |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4ffc22ae000f207d3c660ebc197d31940025fbfa |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d31c5496d7e1580058b5c6fbc8fd537a641ea590 |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7f2f436267cc9684e11878500e017babd1779db0 |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
storeRegToStackSlot has forgotten about QPR_8 register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
|
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d100755bab38784703f677b8b8eb174b624b346b |
|
28-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
rdar://7895451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 62b50656ceb854eb0be265d63b2a1d46e7400d8a |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 375be7730a6f3dee7a6dc319ee6c355a11ac99ad |
|
07-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 93d6a7e9c21204c52d6efec6c672163e7de79660 |
|
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6b |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c289a0252bba42248d7b11699dda27feca8860b6 |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename some instructions to match the corresponding NEON opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 11d98997590a1d636b04c4f0756eded6b2d037f3 |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VST1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 621f1952430ee8b01b21ac94404e52500d79838b |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLD1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 226036ee731a2041f37f28f958d2b6a50373f4f4 |
|
20-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6755d97a62fd6796f4146833efb1051fc96a61c0 |
|
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a43e6bf69093b9870548e7d782ea148e2ddd6449 |
|
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert 98683. It is breaking something in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| bb6c77e6b9be405fb4d57c8ee4cddc2018df392c |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 506049f29f4f202a8e45feb916cc0264440a7f6d |
|
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 0eb0c7401c34c0b4604f732ce54db995eead14e6 |
|
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle tGPR register class in a few more places. This fixes some llvm-gcc
build failures due to my fix for pr6111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1665b0a2246c83a2c123be105a1a167cf2b423fe |
|
16-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr6111: Avoid using the LR register for the target address of an indirect
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a87ded2695e5bce30dbd0d2d2ac10c571bf1d161 |
|
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c90a153ad04a2f0cc212c5bc7206d655807b90e0 |
|
27-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Adjust setjmp instruction sequence to not need 32-bit alignment padding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b1e803985d3378538ae9cff7eed4102c002d1e22 |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
prep work to support a future where getJumpTableInfo will return
a null pointer for functions with no jump tables. No functionality
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3 |
|
19-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 30ac0467ced4627a9b84d8a1d3ca5e8706ddad63 |
|
07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9bf50f45e7f1ea82b391673b8e0903b5c4e2460c |
|
28-Dec-2009 |
Bill Wendling <isanbard@gmail.com> |
Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 4dc4a61c0c47611fef23e06145ece9f63b2a8dc6 |
|
03-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
remove out of date FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 56856b1f46ec1f073ceef4e826c544b8b1691608 |
|
03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
fix a build problem with VC++, PR5664, patch by Alp Toker!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d122874996a6faa8832569b632fd73a32ace7ae7 |
|
01-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 exception handling setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
|
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f8c4cfb7cc330234112e1378dac6424d9956add0 |
|
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Refactor target hook for tail duplication as requested by Chris.
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d7f0810c934a7d13acb28c42d737ce58ec990ea8 |
|
24-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ac0869dc8a7986855c5557cc67d4709600158ef5 |
|
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 9b82425cb0105fd5704f6b9bcd5e7693b05b1759 |
|
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Also CSE non-pic load from constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 834b08af8d3d8fc6c76ac6ca40674565689e8d7f |
|
18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a44321776ecd96fa0344335d3027758be3386e45 |
|
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6cb6788b79bcec64886880697fc69b82a296f671 |
|
15-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
set the def of the VLD1q64 properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d57cdd5683ea926e489067364fb7ffe5fd5d35ee |
|
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 |
|
09-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 31bc849123011b8eae6bb3c79876d9a3c26a6a1d |
|
08-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| fdc834046efd427d474e3b899ec69354c05071e0 |
|
08-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 31c24bf5b39cc8391d4cfdbf8cf5163975fdb81e |
|
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup of file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d457e6e9a5cd975baf4d1f0578382ab8373e6153 |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5a1cd36019ca3cbae811f2800631b5b56a9ffdc2 |
|
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f6c0bffa8d6308ba0f31df0bb57f194b24aca83f |
|
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Trim unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b4db6a46e0de3283fa70ea0a7d3623f2e4e2d2a3 |
|
03-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7aaf94bb0dde65e70b417208aaf859f7292a31d1 |
|
03-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7baae87d8f188262e07922348d88201f32514b1c |
|
02-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Unbreak ARMBaseRegisterInfo::copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| f95215f551949d5e5adfbf4753aa833b9009b77a |
|
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8d4de5abfa1bcd974554ea14904ebf7af289e84d |
|
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ed3ad212ec34fa2866fb70f9e52ddda31032ea3b |
|
25-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget subreg indices when folding load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5a850beb2e3032e6ff3474ce5317f5454060328c |
|
24-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 491f54f1fd700204db0a19efde0cc2627641d711 |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6553155172a2e74feff1253837daa608123de54a |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| bf125583f8bd8196a34921276add7f304b7c1433 |
|
17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 249fb339ad9d4b921a04de738b9c67d27e328bb7 |
|
07-Oct-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
and register spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 26207e5bf1123a793bd9b38bcda2f569a6b45ef2 |
|
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5adb66a646e2ec32265263739f5b01c3f50c176a |
|
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e56f9085b1e96f0cc302c678f1c00877676e455e |
|
13-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6ca0b9e7220911a6d1fccf34e532e69c7e37cd2f |
|
08-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cdbb3f5d3311e0f46d22bc8daa211b2fab3541cb |
|
27-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 33adcfb4d217f5f23d9bde8ba02b8e48f9605fc5 |
|
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 |
|
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
|
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5aa1684e5da9a85286bf7d29da419d261a70c2f2 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 eh_sjlj_setjmp implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| cdc17ebc2b2e9e18ac516b9d246a5c5a3af227d3 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
fix GetInstSizeInBytes for eh_sjlj_setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 764ab52dd80310a205c9888bf166d09dab858f90 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 19068ba71a480d9b5032fd9f87eb412e8beb09f4 |
|
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support for folding loads / stores into 16-bit moves used by Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 229464564243b24fb12cece515d727673e726994 |
|
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| baf31088f1472f48ea5ae81f0b93636cc44ca444 |
|
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use VLDM / VSTM to spill/reload 128-bit Neon registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 8fb903604e83dfd63659c919042bf2bfed3c940f |
|
08-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Code refactoring. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1d2426c4701650846922d312eb742cc55385c721 |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix support to use NEON for single precision fp math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 7bfdca0206f51132b26094c6f83a5ac97ee0f943 |
|
05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
|
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 25f7cfc3cccba6f569f29f79ea533bae960b93c0 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Workaround a couple of Darwin assembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| a0ee862f2e3a0d202244e02459ddcf0dca0e8607 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2BR_JT is mov pc, it's 2 byte long, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| d26b14c34cbcee1448b86b524578fc51cc979023 |
|
31-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 6495f63945e8dbde81f03a1dc2ab421993b9a495 |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 78703ddafe3d037f75d8ca188e4829d238289ac3 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 83e0e36be8390fee1235783731f6c64aa604b7ee |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5ca53a7ad821613d324e4189ddbb0d468a326146 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of some more getOpcode calls.
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 1f5c9887544ac2cb39d48e35cc6fa7a7b73ed3b0 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5732ca084aaa0cd26149e50dd4b487efff37fe41 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 08b93c6a70ae59af375f205cfcffeaa3517577ab |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 68e3c6ae49ff67cba98403e43b5bd0c2499caa41 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Just use a single isMoveInstr to catch all the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 66ac53165e17b7c76b8c69e57bde623d44ec492e |
|
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 789476240d6b6f8ad9366cadf790a82bd41bb0b3 |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure thumb2 jumptable entries are aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
|
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b74bb1a7a471a77e793d90de158aa4bbc67fe94d |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 5ff58b5c3ab6df332600678798ea5c69c5e943d3 |
|
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcf |
|
17-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| dd6f63209cba0003e67470938830de2cb6917336 |
|
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| ab331504452a833f27a030f13525b964545d768a |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move isPredicated from .cpp to .h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| e7cbe4118b7ddf05032ff8772a98c51e1637bb5c |
|
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|
| 334c26473bba3ad8b88341bb0d25d0ac2008bb8d |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
|