ARMBaseInstrInfo.cpp revision 77aee8e22c36257716c2df2f275724765704f20c 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMRegisterInfo.h"
20#include "ARMGenInstrInfo.inc"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39static cl::opt<bool>
40EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41               cl::desc("Enable ARM 2-addr to 3-addr conv"));
42
43static cl::opt<bool>
44OldARMIfCvt("old-arm-ifcvt", cl::Hidden,
45             cl::desc("Use old-style ARM if-conversion heuristics"));
46
47ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
48  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49    Subtarget(STI) {
50}
51
52MachineInstr *
53ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
54                                        MachineBasicBlock::iterator &MBBI,
55                                        LiveVariables *LV) const {
56  // FIXME: Thumb2 support.
57
58  if (!EnableARM3Addr)
59    return NULL;
60
61  MachineInstr *MI = MBBI;
62  MachineFunction &MF = *MI->getParent()->getParent();
63  uint64_t TSFlags = MI->getDesc().TSFlags;
64  bool isPre = false;
65  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
66  default: return NULL;
67  case ARMII::IndexModePre:
68    isPre = true;
69    break;
70  case ARMII::IndexModePost:
71    break;
72  }
73
74  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
75  // operation.
76  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
77  if (MemOpc == 0)
78    return NULL;
79
80  MachineInstr *UpdateMI = NULL;
81  MachineInstr *MemMI = NULL;
82  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
83  const TargetInstrDesc &TID = MI->getDesc();
84  unsigned NumOps = TID.getNumOperands();
85  bool isLoad = !TID.mayStore();
86  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
87  const MachineOperand &Base = MI->getOperand(2);
88  const MachineOperand &Offset = MI->getOperand(NumOps-3);
89  unsigned WBReg = WB.getReg();
90  unsigned BaseReg = Base.getReg();
91  unsigned OffReg = Offset.getReg();
92  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
93  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
94  switch (AddrMode) {
95  default:
96    assert(false && "Unknown indexed op!");
97    return NULL;
98  case ARMII::AddrMode2: {
99    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
100    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
101    if (OffReg == 0) {
102      if (ARM_AM::getSOImmVal(Amt) == -1)
103        // Can't encode it in a so_imm operand. This transformation will
104        // add more than 1 instruction. Abandon!
105        return NULL;
106      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
107                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
108        .addReg(BaseReg).addImm(Amt)
109        .addImm(Pred).addReg(0).addReg(0);
110    } else if (Amt != 0) {
111      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
112      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
113      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
115        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
116        .addImm(Pred).addReg(0).addReg(0);
117    } else
118      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
119                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
120        .addReg(BaseReg).addReg(OffReg)
121        .addImm(Pred).addReg(0).addReg(0);
122    break;
123  }
124  case ARMII::AddrMode3 : {
125    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
126    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
127    if (OffReg == 0)
128      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
129      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
131        .addReg(BaseReg).addImm(Amt)
132        .addImm(Pred).addReg(0).addReg(0);
133    else
134      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
135                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
136        .addReg(BaseReg).addReg(OffReg)
137        .addImm(Pred).addReg(0).addReg(0);
138    break;
139  }
140  }
141
142  std::vector<MachineInstr*> NewMIs;
143  if (isPre) {
144    if (isLoad)
145      MemMI = BuildMI(MF, MI->getDebugLoc(),
146                      get(MemOpc), MI->getOperand(0).getReg())
147        .addReg(WBReg).addImm(0).addImm(Pred);
148    else
149      MemMI = BuildMI(MF, MI->getDebugLoc(),
150                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
151        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
152    NewMIs.push_back(MemMI);
153    NewMIs.push_back(UpdateMI);
154  } else {
155    if (isLoad)
156      MemMI = BuildMI(MF, MI->getDebugLoc(),
157                      get(MemOpc), MI->getOperand(0).getReg())
158        .addReg(BaseReg).addImm(0).addImm(Pred);
159    else
160      MemMI = BuildMI(MF, MI->getDebugLoc(),
161                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
162        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
163    if (WB.isDead())
164      UpdateMI->getOperand(0).setIsDead();
165    NewMIs.push_back(UpdateMI);
166    NewMIs.push_back(MemMI);
167  }
168
169  // Transfer LiveVariables states, kill / dead info.
170  if (LV) {
171    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
172      MachineOperand &MO = MI->getOperand(i);
173      if (MO.isReg() && MO.getReg() &&
174          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
175        unsigned Reg = MO.getReg();
176
177        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
178        if (MO.isDef()) {
179          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
180          if (MO.isDead())
181            LV->addVirtualRegisterDead(Reg, NewMI);
182        }
183        if (MO.isUse() && MO.isKill()) {
184          for (unsigned j = 0; j < 2; ++j) {
185            // Look at the two new MI's in reverse order.
186            MachineInstr *NewMI = NewMIs[j];
187            if (!NewMI->readsRegister(Reg))
188              continue;
189            LV->addVirtualRegisterKilled(Reg, NewMI);
190            if (VI.removeKill(MI))
191              VI.Kills.push_back(NewMI);
192            break;
193          }
194        }
195      }
196    }
197  }
198
199  MFI->insert(MBBI, NewMIs[1]);
200  MFI->insert(MBBI, NewMIs[0]);
201  return NewMIs[0];
202}
203
204bool
205ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
206                                        MachineBasicBlock::iterator MI,
207                                        const std::vector<CalleeSavedInfo> &CSI,
208                                        const TargetRegisterInfo *TRI) const {
209  if (CSI.empty())
210    return false;
211
212  DebugLoc DL;
213  if (MI != MBB.end()) DL = MI->getDebugLoc();
214
215  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
216    unsigned Reg = CSI[i].getReg();
217    bool isKill = true;
218
219    // Add the callee-saved register as live-in unless it's LR and
220    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
221    // then it's already added to the function and entry block live-in sets.
222    if (Reg == ARM::LR) {
223      MachineFunction &MF = *MBB.getParent();
224      if (MF.getFrameInfo()->isReturnAddressTaken() &&
225          MF.getRegInfo().isLiveIn(Reg))
226        isKill = false;
227    }
228
229    if (isKill)
230      MBB.addLiveIn(Reg);
231
232    // Insert the spill to the stack frame. The register is killed at the spill
233    //
234    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
235    storeRegToStackSlot(MBB, MI, Reg, isKill,
236                        CSI[i].getFrameIdx(), RC, TRI);
237  }
238  return true;
239}
240
241// Branch analysis.
242bool
243ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
244                                MachineBasicBlock *&FBB,
245                                SmallVectorImpl<MachineOperand> &Cond,
246                                bool AllowModify) const {
247  // If the block has no terminators, it just falls into the block after it.
248  MachineBasicBlock::iterator I = MBB.end();
249  if (I == MBB.begin())
250    return false;
251  --I;
252  while (I->isDebugValue()) {
253    if (I == MBB.begin())
254      return false;
255    --I;
256  }
257  if (!isUnpredicatedTerminator(I))
258    return false;
259
260  // Get the last instruction in the block.
261  MachineInstr *LastInst = I;
262
263  // If there is only one terminator instruction, process it.
264  unsigned LastOpc = LastInst->getOpcode();
265  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
266    if (isUncondBranchOpcode(LastOpc)) {
267      TBB = LastInst->getOperand(0).getMBB();
268      return false;
269    }
270    if (isCondBranchOpcode(LastOpc)) {
271      // Block ends with fall-through condbranch.
272      TBB = LastInst->getOperand(0).getMBB();
273      Cond.push_back(LastInst->getOperand(1));
274      Cond.push_back(LastInst->getOperand(2));
275      return false;
276    }
277    return true;  // Can't handle indirect branch.
278  }
279
280  // Get the instruction before it if it is a terminator.
281  MachineInstr *SecondLastInst = I;
282  unsigned SecondLastOpc = SecondLastInst->getOpcode();
283
284  // If AllowModify is true and the block ends with two or more unconditional
285  // branches, delete all but the first unconditional branch.
286  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
287    while (isUncondBranchOpcode(SecondLastOpc)) {
288      LastInst->eraseFromParent();
289      LastInst = SecondLastInst;
290      LastOpc = LastInst->getOpcode();
291      if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
292        // Return now the only terminator is an unconditional branch.
293        TBB = LastInst->getOperand(0).getMBB();
294        return false;
295      } else {
296        SecondLastInst = I;
297        SecondLastOpc = SecondLastInst->getOpcode();
298      }
299    }
300  }
301
302  // If there are three terminators, we don't know what sort of block this is.
303  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
304    return true;
305
306  // If the block ends with a B and a Bcc, handle it.
307  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
308    TBB =  SecondLastInst->getOperand(0).getMBB();
309    Cond.push_back(SecondLastInst->getOperand(1));
310    Cond.push_back(SecondLastInst->getOperand(2));
311    FBB = LastInst->getOperand(0).getMBB();
312    return false;
313  }
314
315  // If the block ends with two unconditional branches, handle it.  The second
316  // one is not executed, so remove it.
317  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
318    TBB = SecondLastInst->getOperand(0).getMBB();
319    I = LastInst;
320    if (AllowModify)
321      I->eraseFromParent();
322    return false;
323  }
324
325  // ...likewise if it ends with a branch table followed by an unconditional
326  // branch. The branch folder can create these, and we must get rid of them for
327  // correctness of Thumb constant islands.
328  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
329       isIndirectBranchOpcode(SecondLastOpc)) &&
330      isUncondBranchOpcode(LastOpc)) {
331    I = LastInst;
332    if (AllowModify)
333      I->eraseFromParent();
334    return true;
335  }
336
337  // Otherwise, can't handle this.
338  return true;
339}
340
341
342unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
343  MachineBasicBlock::iterator I = MBB.end();
344  if (I == MBB.begin()) return 0;
345  --I;
346  while (I->isDebugValue()) {
347    if (I == MBB.begin())
348      return 0;
349    --I;
350  }
351  if (!isUncondBranchOpcode(I->getOpcode()) &&
352      !isCondBranchOpcode(I->getOpcode()))
353    return 0;
354
355  // Remove the branch.
356  I->eraseFromParent();
357
358  I = MBB.end();
359
360  if (I == MBB.begin()) return 1;
361  --I;
362  if (!isCondBranchOpcode(I->getOpcode()))
363    return 1;
364
365  // Remove the branch.
366  I->eraseFromParent();
367  return 2;
368}
369
370unsigned
371ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
372                               MachineBasicBlock *FBB,
373                               const SmallVectorImpl<MachineOperand> &Cond,
374                               DebugLoc DL) const {
375  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
376  int BOpc   = !AFI->isThumbFunction()
377    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
378  int BccOpc = !AFI->isThumbFunction()
379    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
380
381  // Shouldn't be a fall through.
382  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
383  assert((Cond.size() == 2 || Cond.size() == 0) &&
384         "ARM branch conditions have two components!");
385
386  if (FBB == 0) {
387    if (Cond.empty()) // Unconditional branch?
388      BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
389    else
390      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
391        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
392    return 1;
393  }
394
395  // Two-way conditional branch.
396  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
397    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
398  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
399  return 2;
400}
401
402bool ARMBaseInstrInfo::
403ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
404  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
405  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
406  return false;
407}
408
409bool ARMBaseInstrInfo::
410PredicateInstruction(MachineInstr *MI,
411                     const SmallVectorImpl<MachineOperand> &Pred) const {
412  unsigned Opc = MI->getOpcode();
413  if (isUncondBranchOpcode(Opc)) {
414    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
415    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
416    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
417    return true;
418  }
419
420  int PIdx = MI->findFirstPredOperandIdx();
421  if (PIdx != -1) {
422    MachineOperand &PMO = MI->getOperand(PIdx);
423    PMO.setImm(Pred[0].getImm());
424    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
425    return true;
426  }
427  return false;
428}
429
430bool ARMBaseInstrInfo::
431SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
432                  const SmallVectorImpl<MachineOperand> &Pred2) const {
433  if (Pred1.size() > 2 || Pred2.size() > 2)
434    return false;
435
436  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
437  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
438  if (CC1 == CC2)
439    return true;
440
441  switch (CC1) {
442  default:
443    return false;
444  case ARMCC::AL:
445    return true;
446  case ARMCC::HS:
447    return CC2 == ARMCC::HI;
448  case ARMCC::LS:
449    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
450  case ARMCC::GE:
451    return CC2 == ARMCC::GT;
452  case ARMCC::LE:
453    return CC2 == ARMCC::LT;
454  }
455}
456
457bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
458                                    std::vector<MachineOperand> &Pred) const {
459  // FIXME: This confuses implicit_def with optional CPSR def.
460  const TargetInstrDesc &TID = MI->getDesc();
461  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
462    return false;
463
464  bool Found = false;
465  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
466    const MachineOperand &MO = MI->getOperand(i);
467    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
468      Pred.push_back(MO);
469      Found = true;
470    }
471  }
472
473  return Found;
474}
475
476/// isPredicable - Return true if the specified instruction can be predicated.
477/// By default, this returns true for every instruction with a
478/// PredicateOperand.
479bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
480  const TargetInstrDesc &TID = MI->getDesc();
481  if (!TID.isPredicable())
482    return false;
483
484  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
485    ARMFunctionInfo *AFI =
486      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
487    return AFI->isThumb2Function();
488  }
489  return true;
490}
491
492/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
493LLVM_ATTRIBUTE_NOINLINE
494static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
495                                unsigned JTI);
496static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
497                                unsigned JTI) {
498  assert(JTI < JT.size());
499  return JT[JTI].MBBs.size();
500}
501
502/// GetInstSize - Return the size of the specified MachineInstr.
503///
504unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
505  const MachineBasicBlock &MBB = *MI->getParent();
506  const MachineFunction *MF = MBB.getParent();
507  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
508
509  // Basic size info comes from the TSFlags field.
510  const TargetInstrDesc &TID = MI->getDesc();
511  uint64_t TSFlags = TID.TSFlags;
512
513  unsigned Opc = MI->getOpcode();
514  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
515  default: {
516    // If this machine instr is an inline asm, measure it.
517    if (MI->getOpcode() == ARM::INLINEASM)
518      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
519    if (MI->isLabel())
520      return 0;
521    switch (Opc) {
522    default:
523      llvm_unreachable("Unknown or unset size field for instr!");
524    case TargetOpcode::IMPLICIT_DEF:
525    case TargetOpcode::KILL:
526    case TargetOpcode::PROLOG_LABEL:
527    case TargetOpcode::EH_LABEL:
528    case TargetOpcode::DBG_VALUE:
529      return 0;
530    }
531    break;
532  }
533  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
534  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
535  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
536  case ARMII::SizeSpecial: {
537    switch (Opc) {
538    case ARM::MOVi32imm:
539    case ARM::t2MOVi32imm:
540      return 8;
541    case ARM::CONSTPOOL_ENTRY:
542      // If this machine instr is a constant pool entry, its size is recorded as
543      // operand #2.
544      return MI->getOperand(2).getImm();
545    case ARM::Int_eh_sjlj_longjmp:
546      return 16;
547    case ARM::tInt_eh_sjlj_longjmp:
548      return 10;
549    case ARM::Int_eh_sjlj_setjmp:
550    case ARM::Int_eh_sjlj_setjmp_nofp:
551      return 20;
552    case ARM::tInt_eh_sjlj_setjmp:
553    case ARM::t2Int_eh_sjlj_setjmp:
554    case ARM::t2Int_eh_sjlj_setjmp_nofp:
555      return 12;
556    case ARM::BR_JTr:
557    case ARM::BR_JTm:
558    case ARM::BR_JTadd:
559    case ARM::tBR_JTr:
560    case ARM::t2BR_JT:
561    case ARM::t2TBB:
562    case ARM::t2TBH: {
563      // These are jumptable branches, i.e. a branch followed by an inlined
564      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
565      // entry is one byte; TBH two byte each.
566      unsigned EntrySize = (Opc == ARM::t2TBB)
567        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
568      unsigned NumOps = TID.getNumOperands();
569      MachineOperand JTOP =
570        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
571      unsigned JTI = JTOP.getIndex();
572      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
573      assert(MJTI != 0);
574      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
575      assert(JTI < JT.size());
576      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
577      // 4 aligned. The assembler / linker may add 2 byte padding just before
578      // the JT entries.  The size does not include this padding; the
579      // constant islands pass does separate bookkeeping for it.
580      // FIXME: If we know the size of the function is less than (1 << 16) *2
581      // bytes, we can use 16-bit entries instead. Then there won't be an
582      // alignment issue.
583      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
584      unsigned NumEntries = getNumJTEntries(JT, JTI);
585      if (Opc == ARM::t2TBB && (NumEntries & 1))
586        // Make sure the instruction that follows TBB is 2-byte aligned.
587        // FIXME: Constant island pass should insert an "ALIGN" instruction
588        // instead.
589        ++NumEntries;
590      return NumEntries * EntrySize + InstSize;
591    }
592    default:
593      // Otherwise, pseudo-instruction sizes are zero.
594      return 0;
595    }
596  }
597  }
598  return 0; // Not reached
599}
600
601void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
602                                   MachineBasicBlock::iterator I, DebugLoc DL,
603                                   unsigned DestReg, unsigned SrcReg,
604                                   bool KillSrc) const {
605  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
606  bool GPRSrc  = ARM::GPRRegClass.contains(SrcReg);
607
608  if (GPRDest && GPRSrc) {
609    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
610                                  .addReg(SrcReg, getKillRegState(KillSrc))));
611    return;
612  }
613
614  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
615  bool SPRSrc  = ARM::SPRRegClass.contains(SrcReg);
616
617  unsigned Opc;
618  if (SPRDest && SPRSrc)
619    Opc = ARM::VMOVS;
620  else if (GPRDest && SPRSrc)
621    Opc = ARM::VMOVRS;
622  else if (SPRDest && GPRSrc)
623    Opc = ARM::VMOVSR;
624  else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
625    Opc = ARM::VMOVD;
626  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
627    Opc = ARM::VMOVQ;
628  else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
629    Opc = ARM::VMOVQQ;
630  else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
631    Opc = ARM::VMOVQQQQ;
632  else
633    llvm_unreachable("Impossible reg-to-reg copy");
634
635  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
636  MIB.addReg(SrcReg, getKillRegState(KillSrc));
637  if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
638    AddDefaultPred(MIB);
639}
640
641static const
642MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
643                             unsigned Reg, unsigned SubIdx, unsigned State,
644                             const TargetRegisterInfo *TRI) {
645  if (!SubIdx)
646    return MIB.addReg(Reg, State);
647
648  if (TargetRegisterInfo::isPhysicalRegister(Reg))
649    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
650  return MIB.addReg(Reg, State, SubIdx);
651}
652
653void ARMBaseInstrInfo::
654storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
655                    unsigned SrcReg, bool isKill, int FI,
656                    const TargetRegisterClass *RC,
657                    const TargetRegisterInfo *TRI) const {
658  DebugLoc DL;
659  if (I != MBB.end()) DL = I->getDebugLoc();
660  MachineFunction &MF = *MBB.getParent();
661  MachineFrameInfo &MFI = *MF.getFrameInfo();
662  unsigned Align = MFI.getObjectAlignment(FI);
663
664  MachineMemOperand *MMO =
665    MF.getMachineMemOperand(MachinePointerInfo(
666                                         PseudoSourceValue::getFixedStack(FI)),
667                            MachineMemOperand::MOStore,
668                            MFI.getObjectSize(FI),
669                            Align);
670
671  // tGPR is used sometimes in ARM instructions that need to avoid using
672  // certain registers.  Just treat it as GPR here. Likewise, rGPR.
673  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
674      || RC == ARM::rGPRRegisterClass)
675    RC = ARM::GPRRegisterClass;
676
677  switch (RC->getID()) {
678  case ARM::GPRRegClassID:
679    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
680                   .addReg(SrcReg, getKillRegState(isKill))
681                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
682    break;
683  case ARM::SPRRegClassID:
684    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
685                   .addReg(SrcReg, getKillRegState(isKill))
686                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
687    break;
688  case ARM::DPRRegClassID:
689  case ARM::DPR_VFP2RegClassID:
690  case ARM::DPR_8RegClassID:
691    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
692                   .addReg(SrcReg, getKillRegState(isKill))
693                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
694    break;
695  case ARM::QPRRegClassID:
696  case ARM::QPR_VFP2RegClassID:
697  case ARM::QPR_8RegClassID:
698    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
699      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
700                     .addFrameIndex(FI).addImm(16)
701                     .addReg(SrcReg, getKillRegState(isKill))
702                     .addMemOperand(MMO));
703    } else {
704      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
705                     .addReg(SrcReg, getKillRegState(isKill))
706                     .addFrameIndex(FI)
707                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
708                     .addMemOperand(MMO));
709    }
710    break;
711  case ARM::QQPRRegClassID:
712  case ARM::QQPR_VFP2RegClassID:
713    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
714      // FIXME: It's possible to only store part of the QQ register if the
715      // spilled def has a sub-register index.
716      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
717                     .addFrameIndex(FI).addImm(16)
718                     .addReg(SrcReg, getKillRegState(isKill))
719                     .addMemOperand(MMO));
720    } else {
721      MachineInstrBuilder MIB =
722        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
723                       .addFrameIndex(FI)
724                       .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
725        .addMemOperand(MMO);
726      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
727      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
728      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
729            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
730    }
731    break;
732  case ARM::QQQQPRRegClassID: {
733    MachineInstrBuilder MIB =
734      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
735                     .addFrameIndex(FI)
736                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
737      .addMemOperand(MMO);
738    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
739    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
740    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
741    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
742    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
743    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
744    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
745          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
746    break;
747  }
748  default:
749    llvm_unreachable("Unknown regclass!");
750  }
751}
752
753unsigned
754ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
755                                     int &FrameIndex) const {
756  switch (MI->getOpcode()) {
757  default: break;
758  case ARM::STR:
759  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
760    if (MI->getOperand(1).isFI() &&
761        MI->getOperand(2).isReg() &&
762        MI->getOperand(3).isImm() &&
763        MI->getOperand(2).getReg() == 0 &&
764        MI->getOperand(3).getImm() == 0) {
765      FrameIndex = MI->getOperand(1).getIndex();
766      return MI->getOperand(0).getReg();
767    }
768    break;
769  case ARM::t2STRi12:
770  case ARM::tSpill:
771  case ARM::VSTRD:
772  case ARM::VSTRS:
773    if (MI->getOperand(1).isFI() &&
774        MI->getOperand(2).isImm() &&
775        MI->getOperand(2).getImm() == 0) {
776      FrameIndex = MI->getOperand(1).getIndex();
777      return MI->getOperand(0).getReg();
778    }
779    break;
780  case ARM::VST1q64Pseudo:
781    if (MI->getOperand(0).isFI() &&
782        MI->getOperand(2).getSubReg() == 0) {
783      FrameIndex = MI->getOperand(0).getIndex();
784      return MI->getOperand(2).getReg();
785    }
786    break;
787  case ARM::VSTMQ:
788    if (MI->getOperand(1).isFI() &&
789        MI->getOperand(2).isImm() &&
790        MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
791        MI->getOperand(0).getSubReg() == 0) {
792      FrameIndex = MI->getOperand(1).getIndex();
793      return MI->getOperand(0).getReg();
794    }
795    break;
796  }
797
798  return 0;
799}
800
801void ARMBaseInstrInfo::
802loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
803                     unsigned DestReg, int FI,
804                     const TargetRegisterClass *RC,
805                     const TargetRegisterInfo *TRI) const {
806  DebugLoc DL;
807  if (I != MBB.end()) DL = I->getDebugLoc();
808  MachineFunction &MF = *MBB.getParent();
809  MachineFrameInfo &MFI = *MF.getFrameInfo();
810  unsigned Align = MFI.getObjectAlignment(FI);
811  MachineMemOperand *MMO =
812    MF.getMachineMemOperand(
813                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
814                            MachineMemOperand::MOLoad,
815                            MFI.getObjectSize(FI),
816                            Align);
817
818  // tGPR is used sometimes in ARM instructions that need to avoid using
819  // certain registers.  Just treat it as GPR here.
820  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
821      || RC == ARM::rGPRRegisterClass)
822    RC = ARM::GPRRegisterClass;
823
824  switch (RC->getID()) {
825  case ARM::GPRRegClassID:
826    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
827                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
828    break;
829  case ARM::SPRRegClassID:
830    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
831                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
832    break;
833  case ARM::DPRRegClassID:
834  case ARM::DPR_VFP2RegClassID:
835  case ARM::DPR_8RegClassID:
836    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
837                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
838    break;
839  case ARM::QPRRegClassID:
840  case ARM::QPR_VFP2RegClassID:
841  case ARM::QPR_8RegClassID:
842    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
843      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
844                     .addFrameIndex(FI).addImm(16)
845                     .addMemOperand(MMO));
846    } else {
847      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
848                     .addFrameIndex(FI)
849                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
850                     .addMemOperand(MMO));
851    }
852    break;
853  case ARM::QQPRRegClassID:
854  case ARM::QQPR_VFP2RegClassID:
855    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
856      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
857                     .addFrameIndex(FI).addImm(16)
858                     .addMemOperand(MMO));
859    } else {
860      MachineInstrBuilder MIB =
861        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
862                       .addFrameIndex(FI)
863                       .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
864        .addMemOperand(MMO);
865      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
866      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
867      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
868            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
869    }
870    break;
871  case ARM::QQQQPRRegClassID: {
872    MachineInstrBuilder MIB =
873      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
874                     .addFrameIndex(FI)
875                     .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
876      .addMemOperand(MMO);
877    MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
878    MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
879    MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
880    MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
881    MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
882    MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
883    MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
884    AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
885    break;
886  }
887  default:
888    llvm_unreachable("Unknown regclass!");
889  }
890}
891
892unsigned
893ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
894                                      int &FrameIndex) const {
895  switch (MI->getOpcode()) {
896  default: break;
897  case ARM::LDRrs:
898  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
899    if (MI->getOperand(1).isFI() &&
900        MI->getOperand(2).isReg() &&
901        MI->getOperand(3).isImm() &&
902        MI->getOperand(2).getReg() == 0 &&
903        MI->getOperand(3).getImm() == 0) {
904      FrameIndex = MI->getOperand(1).getIndex();
905      return MI->getOperand(0).getReg();
906    }
907    break;
908  case ARM::LDRi12:
909  case ARM::t2LDRi12:
910  case ARM::tRestore:
911  case ARM::VLDRD:
912  case ARM::VLDRS:
913    if (MI->getOperand(1).isFI() &&
914        MI->getOperand(2).isImm() &&
915        MI->getOperand(2).getImm() == 0) {
916      FrameIndex = MI->getOperand(1).getIndex();
917      return MI->getOperand(0).getReg();
918    }
919    break;
920  case ARM::VLD1q64Pseudo:
921    if (MI->getOperand(1).isFI() &&
922        MI->getOperand(0).getSubReg() == 0) {
923      FrameIndex = MI->getOperand(1).getIndex();
924      return MI->getOperand(0).getReg();
925    }
926    break;
927  case ARM::VLDMQ:
928    if (MI->getOperand(1).isFI() &&
929        MI->getOperand(2).isImm() &&
930        MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
931        MI->getOperand(0).getSubReg() == 0) {
932      FrameIndex = MI->getOperand(1).getIndex();
933      return MI->getOperand(0).getReg();
934    }
935    break;
936  }
937
938  return 0;
939}
940
941MachineInstr*
942ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
943                                           int FrameIx, uint64_t Offset,
944                                           const MDNode *MDPtr,
945                                           DebugLoc DL) const {
946  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
947    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
948  return &*MIB;
949}
950
951/// Create a copy of a const pool value. Update CPI to the new index and return
952/// the label UID.
953static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
954  MachineConstantPool *MCP = MF.getConstantPool();
955  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
956
957  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
958  assert(MCPE.isMachineConstantPoolEntry() &&
959         "Expecting a machine constantpool entry!");
960  ARMConstantPoolValue *ACPV =
961    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
962
963  unsigned PCLabelId = AFI->createConstPoolEntryUId();
964  ARMConstantPoolValue *NewCPV = 0;
965  // FIXME: The below assumes PIC relocation model and that the function
966  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
967  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
968  // instructions, so that's probably OK, but is PIC always correct when
969  // we get here?
970  if (ACPV->isGlobalValue())
971    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
972                                      ARMCP::CPValue, 4);
973  else if (ACPV->isExtSymbol())
974    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
975                                      ACPV->getSymbol(), PCLabelId, 4);
976  else if (ACPV->isBlockAddress())
977    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
978                                      ARMCP::CPBlockAddress, 4);
979  else if (ACPV->isLSDA())
980    NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
981                                      ARMCP::CPLSDA, 4);
982  else
983    llvm_unreachable("Unexpected ARM constantpool value type!!");
984  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
985  return PCLabelId;
986}
987
988void ARMBaseInstrInfo::
989reMaterialize(MachineBasicBlock &MBB,
990              MachineBasicBlock::iterator I,
991              unsigned DestReg, unsigned SubIdx,
992              const MachineInstr *Orig,
993              const TargetRegisterInfo &TRI) const {
994  unsigned Opcode = Orig->getOpcode();
995  switch (Opcode) {
996  default: {
997    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
998    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
999    MBB.insert(I, MI);
1000    break;
1001  }
1002  case ARM::tLDRpci_pic:
1003  case ARM::t2LDRpci_pic: {
1004    MachineFunction &MF = *MBB.getParent();
1005    unsigned CPI = Orig->getOperand(1).getIndex();
1006    unsigned PCLabelId = duplicateCPV(MF, CPI);
1007    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1008                                      DestReg)
1009      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1010    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1011    break;
1012  }
1013  }
1014}
1015
1016MachineInstr *
1017ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1018  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1019  switch(Orig->getOpcode()) {
1020  case ARM::tLDRpci_pic:
1021  case ARM::t2LDRpci_pic: {
1022    unsigned CPI = Orig->getOperand(1).getIndex();
1023    unsigned PCLabelId = duplicateCPV(MF, CPI);
1024    Orig->getOperand(1).setIndex(CPI);
1025    Orig->getOperand(2).setImm(PCLabelId);
1026    break;
1027  }
1028  }
1029  return MI;
1030}
1031
1032bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1033                                        const MachineInstr *MI1) const {
1034  int Opcode = MI0->getOpcode();
1035  if (Opcode == ARM::t2LDRpci ||
1036      Opcode == ARM::t2LDRpci_pic ||
1037      Opcode == ARM::tLDRpci ||
1038      Opcode == ARM::tLDRpci_pic) {
1039    if (MI1->getOpcode() != Opcode)
1040      return false;
1041    if (MI0->getNumOperands() != MI1->getNumOperands())
1042      return false;
1043
1044    const MachineOperand &MO0 = MI0->getOperand(1);
1045    const MachineOperand &MO1 = MI1->getOperand(1);
1046    if (MO0.getOffset() != MO1.getOffset())
1047      return false;
1048
1049    const MachineFunction *MF = MI0->getParent()->getParent();
1050    const MachineConstantPool *MCP = MF->getConstantPool();
1051    int CPI0 = MO0.getIndex();
1052    int CPI1 = MO1.getIndex();
1053    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1054    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1055    ARMConstantPoolValue *ACPV0 =
1056      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1057    ARMConstantPoolValue *ACPV1 =
1058      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1059    return ACPV0->hasSameValue(ACPV1);
1060  }
1061
1062  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1063}
1064
1065/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1066/// determine if two loads are loading from the same base address. It should
1067/// only return true if the base pointers are the same and the only differences
1068/// between the two addresses is the offset. It also returns the offsets by
1069/// reference.
1070bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1071                                               int64_t &Offset1,
1072                                               int64_t &Offset2) const {
1073  // Don't worry about Thumb: just ARM and Thumb2.
1074  if (Subtarget.isThumb1Only()) return false;
1075
1076  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1077    return false;
1078
1079  switch (Load1->getMachineOpcode()) {
1080  default:
1081    return false;
1082  case ARM::LDRi12:
1083  case ARM::LDRBi12:
1084  case ARM::LDRD:
1085  case ARM::LDRH:
1086  case ARM::LDRSB:
1087  case ARM::LDRSH:
1088  case ARM::VLDRD:
1089  case ARM::VLDRS:
1090  case ARM::t2LDRi8:
1091  case ARM::t2LDRDi8:
1092  case ARM::t2LDRSHi8:
1093  case ARM::t2LDRi12:
1094  case ARM::t2LDRSHi12:
1095    break;
1096  }
1097
1098  switch (Load2->getMachineOpcode()) {
1099  default:
1100    return false;
1101  case ARM::LDRi12:
1102  case ARM::LDRBi12:
1103  case ARM::LDRD:
1104  case ARM::LDRH:
1105  case ARM::LDRSB:
1106  case ARM::LDRSH:
1107  case ARM::VLDRD:
1108  case ARM::VLDRS:
1109  case ARM::t2LDRi8:
1110  case ARM::t2LDRDi8:
1111  case ARM::t2LDRSHi8:
1112  case ARM::t2LDRi12:
1113  case ARM::t2LDRSHi12:
1114    break;
1115  }
1116
1117  // Check if base addresses and chain operands match.
1118  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1119      Load1->getOperand(4) != Load2->getOperand(4))
1120    return false;
1121
1122  // Index should be Reg0.
1123  if (Load1->getOperand(3) != Load2->getOperand(3))
1124    return false;
1125
1126  // Determine the offsets.
1127  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1128      isa<ConstantSDNode>(Load2->getOperand(1))) {
1129    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1130    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1131    return true;
1132  }
1133
1134  return false;
1135}
1136
1137/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1138/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1139/// be scheduled togther. On some targets if two loads are loading from
1140/// addresses in the same cache line, it's better if they are scheduled
1141/// together. This function takes two integers that represent the load offsets
1142/// from the common base address. It returns true if it decides it's desirable
1143/// to schedule the two loads together. "NumLoads" is the number of loads that
1144/// have already been scheduled after Load1.
1145bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1146                                               int64_t Offset1, int64_t Offset2,
1147                                               unsigned NumLoads) const {
1148  // Don't worry about Thumb: just ARM and Thumb2.
1149  if (Subtarget.isThumb1Only()) return false;
1150
1151  assert(Offset2 > Offset1);
1152
1153  if ((Offset2 - Offset1) / 8 > 64)
1154    return false;
1155
1156  if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1157    return false;  // FIXME: overly conservative?
1158
1159  // Four loads in a row should be sufficient.
1160  if (NumLoads >= 3)
1161    return false;
1162
1163  return true;
1164}
1165
1166bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1167                                            const MachineBasicBlock *MBB,
1168                                            const MachineFunction &MF) const {
1169  // Debug info is never a scheduling boundary. It's necessary to be explicit
1170  // due to the special treatment of IT instructions below, otherwise a
1171  // dbg_value followed by an IT will result in the IT instruction being
1172  // considered a scheduling hazard, which is wrong. It should be the actual
1173  // instruction preceding the dbg_value instruction(s), just like it is
1174  // when debug info is not present.
1175  if (MI->isDebugValue())
1176    return false;
1177
1178  // Terminators and labels can't be scheduled around.
1179  if (MI->getDesc().isTerminator() || MI->isLabel())
1180    return true;
1181
1182  // Treat the start of the IT block as a scheduling boundary, but schedule
1183  // t2IT along with all instructions following it.
1184  // FIXME: This is a big hammer. But the alternative is to add all potential
1185  // true and anti dependencies to IT block instructions as implicit operands
1186  // to the t2IT instruction. The added compile time and complexity does not
1187  // seem worth it.
1188  MachineBasicBlock::const_iterator I = MI;
1189  // Make sure to skip any dbg_value instructions
1190  while (++I != MBB->end() && I->isDebugValue())
1191    ;
1192  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1193    return true;
1194
1195  // Don't attempt to schedule around any instruction that defines
1196  // a stack-oriented pointer, as it's unlikely to be profitable. This
1197  // saves compile time, because it doesn't require every single
1198  // stack slot reference to depend on the instruction that does the
1199  // modification.
1200  if (MI->definesRegister(ARM::SP))
1201    return true;
1202
1203  return false;
1204}
1205
1206bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1207                                           unsigned NumInstrs,
1208                                           float Probability,
1209                                           float Confidence) const {
1210  if (!NumInstrs)
1211    return false;
1212
1213  // Use old-style heuristics
1214  if (OldARMIfCvt) {
1215    if (Subtarget.getCPUString() == "generic")
1216      // Generic (and overly aggressive) if-conversion limits for testing.
1217      return NumInstrs <= 10;
1218    if (Subtarget.hasV7Ops())
1219      return NumInstrs <= 3;
1220    return NumInstrs <= 2;
1221  }
1222
1223  // Attempt to estimate the relative costs of predication versus branching.
1224  float UnpredCost = Probability * NumInstrs;
1225  UnpredCost += 1.0; // The branch itself
1226  UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1227
1228  float PredCost = NumInstrs;
1229
1230  return PredCost < UnpredCost;
1231
1232}
1233
1234bool ARMBaseInstrInfo::
1235isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1236                    MachineBasicBlock &FMBB, unsigned NumF,
1237                    float Probability, float Confidence) const {
1238  // Use old-style if-conversion heuristics
1239  if (OldARMIfCvt) {
1240    return NumT && NumF && NumT <= 2 && NumF <= 2;
1241  }
1242
1243  if (!NumT || !NumF)
1244    return false;
1245
1246  // Attempt to estimate the relative costs of predication versus branching.
1247  float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF;
1248  UnpredCost += 1.0; // The branch itself
1249  UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1250
1251  float PredCost = NumT + NumF;
1252
1253  return PredCost < UnpredCost;
1254}
1255
1256/// getInstrPredicate - If instruction is predicated, returns its predicate
1257/// condition, otherwise returns AL. It also returns the condition code
1258/// register by reference.
1259ARMCC::CondCodes
1260llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1261  int PIdx = MI->findFirstPredOperandIdx();
1262  if (PIdx == -1) {
1263    PredReg = 0;
1264    return ARMCC::AL;
1265  }
1266
1267  PredReg = MI->getOperand(PIdx+1).getReg();
1268  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1269}
1270
1271
1272int llvm::getMatchingCondBranchOpcode(int Opc) {
1273  if (Opc == ARM::B)
1274    return ARM::Bcc;
1275  else if (Opc == ARM::tB)
1276    return ARM::tBcc;
1277  else if (Opc == ARM::t2B)
1278      return ARM::t2Bcc;
1279
1280  llvm_unreachable("Unknown unconditional branch opcode!");
1281  return 0;
1282}
1283
1284
1285void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1286                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1287                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1288                               ARMCC::CondCodes Pred, unsigned PredReg,
1289                               const ARMBaseInstrInfo &TII) {
1290  bool isSub = NumBytes < 0;
1291  if (isSub) NumBytes = -NumBytes;
1292
1293  while (NumBytes) {
1294    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1295    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1296    assert(ThisVal && "Didn't extract field correctly");
1297
1298    // We will handle these bits from offset, clear them.
1299    NumBytes &= ~ThisVal;
1300
1301    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1302
1303    // Build the new ADD / SUB.
1304    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1305    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1306      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1307      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1308    BaseReg = DestReg;
1309  }
1310}
1311
1312bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1313                                unsigned FrameReg, int &Offset,
1314                                const ARMBaseInstrInfo &TII) {
1315  unsigned Opcode = MI.getOpcode();
1316  const TargetInstrDesc &Desc = MI.getDesc();
1317  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1318  bool isSub = false;
1319
1320  // Memory operands in inline assembly always use AddrMode2.
1321  if (Opcode == ARM::INLINEASM)
1322    AddrMode = ARMII::AddrMode2;
1323
1324  if (Opcode == ARM::ADDri) {
1325    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1326    if (Offset == 0) {
1327      // Turn it into a move.
1328      MI.setDesc(TII.get(ARM::MOVr));
1329      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1330      MI.RemoveOperand(FrameRegIdx+1);
1331      Offset = 0;
1332      return true;
1333    } else if (Offset < 0) {
1334      Offset = -Offset;
1335      isSub = true;
1336      MI.setDesc(TII.get(ARM::SUBri));
1337    }
1338
1339    // Common case: small offset, fits into instruction.
1340    if (ARM_AM::getSOImmVal(Offset) != -1) {
1341      // Replace the FrameIndex with sp / fp
1342      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1343      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1344      Offset = 0;
1345      return true;
1346    }
1347
1348    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1349    // as possible.
1350    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1351    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1352
1353    // We will handle these bits from offset, clear them.
1354    Offset &= ~ThisImmVal;
1355
1356    // Get the properly encoded SOImmVal field.
1357    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1358           "Bit extraction didn't work?");
1359    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1360 } else {
1361    unsigned ImmIdx = 0;
1362    int InstrOffs = 0;
1363    unsigned NumBits = 0;
1364    unsigned Scale = 1;
1365    switch (AddrMode) {
1366    case ARMII::AddrMode_i12: {
1367      ImmIdx = FrameRegIdx + 1;
1368      InstrOffs = MI.getOperand(ImmIdx).getImm();
1369      NumBits = 12;
1370      break;
1371    }
1372    case ARMII::AddrMode2: {
1373      ImmIdx = FrameRegIdx+2;
1374      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1375      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1376        InstrOffs *= -1;
1377      NumBits = 12;
1378      break;
1379    }
1380    case ARMII::AddrMode3: {
1381      ImmIdx = FrameRegIdx+2;
1382      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1383      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1384        InstrOffs *= -1;
1385      NumBits = 8;
1386      break;
1387    }
1388    case ARMII::AddrMode4:
1389    case ARMII::AddrMode6:
1390      // Can't fold any offset even if it's zero.
1391      return false;
1392    case ARMII::AddrMode5: {
1393      ImmIdx = FrameRegIdx+1;
1394      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1395      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1396        InstrOffs *= -1;
1397      NumBits = 8;
1398      Scale = 4;
1399      break;
1400    }
1401    default:
1402      llvm_unreachable("Unsupported addressing mode!");
1403      break;
1404    }
1405
1406    Offset += InstrOffs * Scale;
1407    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1408    if (Offset < 0) {
1409      Offset = -Offset;
1410      isSub = true;
1411    }
1412
1413    // Attempt to fold address comp. if opcode has offset bits
1414    if (NumBits > 0) {
1415      // Common case: small offset, fits into instruction.
1416      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1417      int ImmedOffset = Offset / Scale;
1418      unsigned Mask = (1 << NumBits) - 1;
1419      if ((unsigned)Offset <= Mask * Scale) {
1420        // Replace the FrameIndex with sp
1421        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1422        // FIXME: When addrmode2 goes away, this will simplify (like the
1423        // T2 version), as the LDR.i12 versions don't need the encoding
1424        // tricks for the offset value.
1425        if (isSub) {
1426          if (AddrMode == ARMII::AddrMode_i12)
1427            ImmedOffset = -ImmedOffset;
1428          else
1429            ImmedOffset |= 1 << NumBits;
1430        }
1431        ImmOp.ChangeToImmediate(ImmedOffset);
1432        Offset = 0;
1433        return true;
1434      }
1435
1436      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1437      ImmedOffset = ImmedOffset & Mask;
1438      if (isSub)
1439        ImmedOffset |= 1 << NumBits;
1440      ImmOp.ChangeToImmediate(ImmedOffset);
1441      Offset &= ~(Mask*Scale);
1442    }
1443  }
1444
1445  Offset = (isSub) ? -Offset : Offset;
1446  return Offset == 0;
1447}
1448
1449bool ARMBaseInstrInfo::
1450AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1451               int &CmpValue) const {
1452  switch (MI->getOpcode()) {
1453  default: break;
1454  case ARM::CMPri:
1455  case ARM::CMPzri:
1456  case ARM::t2CMPri:
1457  case ARM::t2CMPzri:
1458    SrcReg = MI->getOperand(0).getReg();
1459    CmpMask = ~0;
1460    CmpValue = MI->getOperand(1).getImm();
1461    return true;
1462  case ARM::TSTri:
1463  case ARM::t2TSTri:
1464    SrcReg = MI->getOperand(0).getReg();
1465    CmpMask = MI->getOperand(1).getImm();
1466    CmpValue = 0;
1467    return true;
1468  }
1469
1470  return false;
1471}
1472
1473/// isSuitableForMask - Identify a suitable 'and' instruction that
1474/// operates on the given source register and applies the same mask
1475/// as a 'tst' instruction. Provide a limited look-through for copies.
1476/// When successful, MI will hold the found instruction.
1477static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1478                              int CmpMask, bool CommonUse) {
1479  switch (MI->getOpcode()) {
1480    case ARM::ANDri:
1481    case ARM::t2ANDri:
1482      if (CmpMask != MI->getOperand(2).getImm())
1483        return false;
1484      if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1485        return true;
1486      break;
1487    case ARM::COPY: {
1488      // Walk down one instruction which is potentially an 'and'.
1489      const MachineInstr &Copy = *MI;
1490      MachineBasicBlock::iterator AND(
1491        llvm::next(MachineBasicBlock::iterator(MI)));
1492      if (AND == MI->getParent()->end()) return false;
1493      MI = AND;
1494      return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1495                               CmpMask, true);
1496    }
1497  }
1498
1499  return false;
1500}
1501
1502/// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1503/// comparison into one that sets the zero bit in the flags register. Update the
1504/// iterator *only* if a transformation took place.
1505bool ARMBaseInstrInfo::
1506OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1507                     int CmpValue, const MachineRegisterInfo *MRI,
1508                     MachineBasicBlock::iterator &MII) const {
1509  if (CmpValue != 0)
1510    return false;
1511
1512  MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1513  if (llvm::next(DI) != MRI->def_end())
1514    // Only support one definition.
1515    return false;
1516
1517  MachineInstr *MI = &*DI;
1518
1519  // Masked compares sometimes use the same register as the corresponding 'and'.
1520  if (CmpMask != ~0) {
1521    if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1522      MI = 0;
1523      for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1524           UE = MRI->use_end(); UI != UE; ++UI) {
1525        if (UI->getParent() != CmpInstr->getParent()) continue;
1526        MachineInstr *PotentialAND = &*UI;
1527        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1528          continue;
1529        MI = PotentialAND;
1530        break;
1531      }
1532      if (!MI) return false;
1533    }
1534  }
1535
1536  // Conservatively refuse to convert an instruction which isn't in the same BB
1537  // as the comparison.
1538  if (MI->getParent() != CmpInstr->getParent())
1539    return false;
1540
1541  // Check that CPSR isn't set between the comparison instruction and the one we
1542  // want to change.
1543  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1544    B = MI->getParent()->begin();
1545
1546  // Early exit if CmpInstr is at the beginning of the BB.
1547  if (I == B) return false;
1548
1549  --I;
1550  for (; I != E; --I) {
1551    const MachineInstr &Instr = *I;
1552
1553    for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1554      const MachineOperand &MO = Instr.getOperand(IO);
1555      if (!MO.isReg() || !MO.isDef()) continue;
1556
1557      // This instruction modifies CPSR before the one we want to change. We
1558      // can't do this transformation.
1559      if (MO.getReg() == ARM::CPSR)
1560        return false;
1561    }
1562
1563    if (I == B)
1564      // The 'and' is below the comparison instruction.
1565      return false;
1566  }
1567
1568  // Set the "zero" bit in CPSR.
1569  switch (MI->getOpcode()) {
1570  default: break;
1571  case ARM::ADDri:
1572  case ARM::ANDri:
1573  case ARM::t2ANDri:
1574  case ARM::SUBri:
1575  case ARM::t2ADDri:
1576  case ARM::t2SUBri:
1577    MI->RemoveOperand(5);
1578    MachineInstrBuilder(MI)
1579      .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1580    MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
1581    CmpInstr->eraseFromParent();
1582    return true;
1583  }
1584
1585  return false;
1586}
1587
1588unsigned
1589ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI,
1590                                 const InstrItineraryData *ItinData) const {
1591  if (!ItinData || ItinData->isEmpty())
1592    return 1;
1593
1594  const TargetInstrDesc &Desc = MI->getDesc();
1595  unsigned Class = Desc.getSchedClass();
1596  unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1597  if (UOps)
1598    return UOps;
1599
1600  unsigned Opc = MI->getOpcode();
1601  switch (Opc) {
1602  default:
1603    llvm_unreachable("Unexpected multi-uops instruction!");
1604    break;
1605  case ARM::VLDMQ:
1606  case ARM::VSTMQ:
1607    return 2;
1608
1609  // The number of uOps for load / store multiple are determined by the number
1610  // registers.
1611  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1612  // same cycle. The scheduling for the first load / store must be done
1613  // separately by assuming the the address is not 64-bit aligned.
1614  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1615  // is not 64-bit aligned, then AGU would take an extra cycle.
1616  // For VFP / NEON load / store multiple, the formula is
1617  // (#reg / 2) + (#reg % 2) + 1.
1618  case ARM::VLDMD:
1619  case ARM::VLDMS:
1620  case ARM::VLDMD_UPD:
1621  case ARM::VLDMS_UPD:
1622  case ARM::VSTMD:
1623  case ARM::VSTMS:
1624  case ARM::VSTMD_UPD:
1625  case ARM::VSTMS_UPD: {
1626    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1627    return (NumRegs / 2) + (NumRegs % 2) + 1;
1628  }
1629  case ARM::LDM_RET:
1630  case ARM::LDM:
1631  case ARM::LDM_UPD:
1632  case ARM::STM:
1633  case ARM::STM_UPD:
1634  case ARM::tLDM:
1635  case ARM::tLDM_UPD:
1636  case ARM::tSTM_UPD:
1637  case ARM::tPOP_RET:
1638  case ARM::tPOP:
1639  case ARM::tPUSH:
1640  case ARM::t2LDM_RET:
1641  case ARM::t2LDM:
1642  case ARM::t2LDM_UPD:
1643  case ARM::t2STM:
1644  case ARM::t2STM_UPD: {
1645    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1646    if (Subtarget.isCortexA8()) {
1647      // 4 registers would be issued: 1, 2, 1.
1648      // 5 registers would be issued: 1, 2, 2.
1649      return 1 + (NumRegs / 2);
1650    } else if (Subtarget.isCortexA9()) {
1651      UOps = (NumRegs / 2);
1652      // If there are odd number of registers or if it's not 64-bit aligned,
1653      // then it takes an extra AGU (Address Generation Unit) cycle.
1654      if ((NumRegs % 2) ||
1655          !MI->hasOneMemOperand() ||
1656          (*MI->memoperands_begin())->getAlignment() < 8)
1657        ++UOps;
1658      return UOps;
1659    } else {
1660      // Assume the worst.
1661      return NumRegs;
1662    }
1663  }
1664  }
1665}
1666
1667int
1668ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1669                                  const TargetInstrDesc &DefTID,
1670                                  unsigned DefClass,
1671                                  unsigned DefIdx, unsigned DefAlign) const {
1672  int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1673  if (RegNo <= 0)
1674    // Def is the address writeback.
1675    return ItinData->getOperandCycle(DefClass, DefIdx);
1676
1677  int DefCycle;
1678  if (Subtarget.isCortexA8()) {
1679    // (regno / 2) + (regno % 2) + 1
1680    DefCycle = RegNo / 2 + 1;
1681    if (RegNo % 2)
1682      ++DefCycle;
1683  } else if (Subtarget.isCortexA9()) {
1684    DefCycle = RegNo;
1685    bool isSLoad = false;
1686    switch (DefTID.getOpcode()) {
1687    default: break;
1688    case ARM::VLDMS:
1689    case ARM::VLDMS_UPD:
1690      isSLoad = true;
1691      break;
1692    }
1693    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1694    // then it takes an extra cycle.
1695    if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1696      ++DefCycle;
1697  } else {
1698    // Assume the worst.
1699    DefCycle = RegNo + 2;
1700  }
1701
1702  return DefCycle;
1703}
1704
1705int
1706ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1707                                 const TargetInstrDesc &DefTID,
1708                                 unsigned DefClass,
1709                                 unsigned DefIdx, unsigned DefAlign) const {
1710  int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1711  if (RegNo <= 0)
1712    // Def is the address writeback.
1713    return ItinData->getOperandCycle(DefClass, DefIdx);
1714
1715  int DefCycle;
1716  if (Subtarget.isCortexA8()) {
1717    // 4 registers would be issued: 1, 2, 1.
1718    // 5 registers would be issued: 1, 2, 2.
1719    DefCycle = RegNo / 2;
1720    if (DefCycle < 1)
1721      DefCycle = 1;
1722    // Result latency is issue cycle + 2: E2.
1723    DefCycle += 2;
1724  } else if (Subtarget.isCortexA9()) {
1725    DefCycle = (RegNo / 2);
1726    // If there are odd number of registers or if it's not 64-bit aligned,
1727    // then it takes an extra AGU (Address Generation Unit) cycle.
1728    if ((RegNo % 2) || DefAlign < 8)
1729      ++DefCycle;
1730    // Result latency is AGU cycles + 2.
1731    DefCycle += 2;
1732  } else {
1733    // Assume the worst.
1734    DefCycle = RegNo + 2;
1735  }
1736
1737  return DefCycle;
1738}
1739
1740int
1741ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1742                                  const TargetInstrDesc &UseTID,
1743                                  unsigned UseClass,
1744                                  unsigned UseIdx, unsigned UseAlign) const {
1745  int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1746  if (RegNo <= 0)
1747    return ItinData->getOperandCycle(UseClass, UseIdx);
1748
1749  int UseCycle;
1750  if (Subtarget.isCortexA8()) {
1751    // (regno / 2) + (regno % 2) + 1
1752    UseCycle = RegNo / 2 + 1;
1753    if (RegNo % 2)
1754      ++UseCycle;
1755  } else if (Subtarget.isCortexA9()) {
1756    UseCycle = RegNo;
1757    bool isSStore = false;
1758    switch (UseTID.getOpcode()) {
1759    default: break;
1760    case ARM::VSTMS:
1761    case ARM::VSTMS_UPD:
1762      isSStore = true;
1763      break;
1764    }
1765    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1766    // then it takes an extra cycle.
1767    if ((isSStore && (RegNo % 2)) || UseAlign < 8)
1768      ++UseCycle;
1769  } else {
1770    // Assume the worst.
1771    UseCycle = RegNo + 2;
1772  }
1773
1774  return UseCycle;
1775}
1776
1777int
1778ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
1779                                 const TargetInstrDesc &UseTID,
1780                                 unsigned UseClass,
1781                                 unsigned UseIdx, unsigned UseAlign) const {
1782  int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1783  if (RegNo <= 0)
1784    return ItinData->getOperandCycle(UseClass, UseIdx);
1785
1786  int UseCycle;
1787  if (Subtarget.isCortexA8()) {
1788    UseCycle = RegNo / 2;
1789    if (UseCycle < 2)
1790      UseCycle = 2;
1791    // Read in E3.
1792    UseCycle += 2;
1793  } else if (Subtarget.isCortexA9()) {
1794    UseCycle = (RegNo / 2);
1795    // If there are odd number of registers or if it's not 64-bit aligned,
1796    // then it takes an extra AGU (Address Generation Unit) cycle.
1797    if ((RegNo % 2) || UseAlign < 8)
1798      ++UseCycle;
1799  } else {
1800    // Assume the worst.
1801    UseCycle = 1;
1802  }
1803  return UseCycle;
1804}
1805
1806int
1807ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1808                                    const TargetInstrDesc &DefTID,
1809                                    unsigned DefIdx, unsigned DefAlign,
1810                                    const TargetInstrDesc &UseTID,
1811                                    unsigned UseIdx, unsigned UseAlign) const {
1812  unsigned DefClass = DefTID.getSchedClass();
1813  unsigned UseClass = UseTID.getSchedClass();
1814
1815  if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
1816    return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1817
1818  // This may be a def / use of a variable_ops instruction, the operand
1819  // latency might be determinable dynamically. Let the target try to
1820  // figure it out.
1821  bool LdmBypass = false;
1822  int DefCycle = -1;
1823  switch (DefTID.getOpcode()) {
1824  default:
1825    DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1826    break;
1827  case ARM::VLDMD:
1828  case ARM::VLDMS:
1829  case ARM::VLDMD_UPD:
1830  case ARM::VLDMS_UPD:  {
1831    DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
1832    break;
1833  }
1834  case ARM::LDM_RET:
1835  case ARM::LDM:
1836  case ARM::LDM_UPD:
1837  case ARM::tLDM:
1838  case ARM::tLDM_UPD:
1839  case ARM::tPUSH:
1840  case ARM::t2LDM_RET:
1841  case ARM::t2LDM:
1842  case ARM::t2LDM_UPD: {
1843    LdmBypass = 1;
1844    DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
1845    break;
1846  }
1847  }
1848
1849  if (DefCycle == -1)
1850    // We can't seem to determine the result latency of the def, assume it's 2.
1851    DefCycle = 2;
1852
1853  int UseCycle = -1;
1854  switch (UseTID.getOpcode()) {
1855  default:
1856    UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
1857    break;
1858  case ARM::VSTMD:
1859  case ARM::VSTMS:
1860  case ARM::VSTMD_UPD:
1861  case ARM::VSTMS_UPD: {
1862    UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
1863    break;
1864  }
1865  case ARM::STM:
1866  case ARM::STM_UPD:
1867  case ARM::tSTM_UPD:
1868  case ARM::tPOP_RET:
1869  case ARM::tPOP:
1870  case ARM::t2STM:
1871  case ARM::t2STM_UPD: {
1872    UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
1873    break;
1874  }
1875  }
1876
1877  if (UseCycle == -1)
1878    // Assume it's read in the first stage.
1879    UseCycle = 1;
1880
1881  UseCycle = DefCycle - UseCycle + 1;
1882  if (UseCycle > 0) {
1883    if (LdmBypass) {
1884      // It's a variable_ops instruction so we can't use DefIdx here. Just use
1885      // first def operand.
1886      if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
1887                                          UseClass, UseIdx))
1888        --UseCycle;
1889    } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
1890                                               UseClass, UseIdx))
1891      --UseCycle;
1892  }
1893
1894  return UseCycle;
1895}
1896
1897int
1898ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1899                             const MachineInstr *DefMI, unsigned DefIdx,
1900                             const MachineInstr *UseMI, unsigned UseIdx) const {
1901  if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
1902      DefMI->isRegSequence() || DefMI->isImplicitDef())
1903    return 1;
1904
1905  const TargetInstrDesc &DefTID = DefMI->getDesc();
1906  if (!ItinData || ItinData->isEmpty())
1907    return DefTID.mayLoad() ? 3 : 1;
1908
1909
1910  const TargetInstrDesc &UseTID = UseMI->getDesc();
1911  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
1912  if (DefMO.getReg() == ARM::CPSR && UseTID.isBranch())
1913    // CPSR set and branch can be paired in the same cycle.
1914    return 0;
1915
1916  unsigned DefAlign = DefMI->hasOneMemOperand()
1917    ? (*DefMI->memoperands_begin())->getAlignment() : 0;
1918  unsigned UseAlign = UseMI->hasOneMemOperand()
1919    ? (*UseMI->memoperands_begin())->getAlignment() : 0;
1920  return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
1921                           UseTID, UseIdx, UseAlign);
1922}
1923
1924int
1925ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1926                                    SDNode *DefNode, unsigned DefIdx,
1927                                    SDNode *UseNode, unsigned UseIdx) const {
1928  if (!DefNode->isMachineOpcode())
1929    return 1;
1930
1931  const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
1932  if (!ItinData || ItinData->isEmpty())
1933    return DefTID.mayLoad() ? 3 : 1;
1934
1935  if (!UseNode->isMachineOpcode())
1936    return ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
1937
1938  const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
1939  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
1940  unsigned DefAlign = !DefMN->memoperands_empty()
1941    ? (*DefMN->memoperands_begin())->getAlignment() : 0;
1942  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
1943  unsigned UseAlign = !UseMN->memoperands_empty()
1944    ? (*UseMN->memoperands_begin())->getAlignment() : 0;
1945  return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
1946                           UseTID, UseIdx, UseAlign);
1947}
1948
1949bool ARMBaseInstrInfo::
1950hasHighOperandLatency(const InstrItineraryData *ItinData,
1951                      const MachineRegisterInfo *MRI,
1952                      const MachineInstr *DefMI, unsigned DefIdx,
1953                      const MachineInstr *UseMI, unsigned UseIdx) const {
1954  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
1955  unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
1956  if (Subtarget.isCortexA8() &&
1957      (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
1958    // CortexA8 VFP instructions are not pipelined.
1959    return true;
1960
1961  // Hoist VFP / NEON instructions with 4 or higher latency.
1962  int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
1963  if (Latency <= 3)
1964    return false;
1965  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
1966         UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
1967}
1968
1969bool ARMBaseInstrInfo::
1970hasLowDefLatency(const InstrItineraryData *ItinData,
1971                 const MachineInstr *DefMI, unsigned DefIdx) const {
1972  if (!ItinData || ItinData->isEmpty())
1973    return false;
1974
1975  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
1976  if (DDomain == ARMII::DomainGeneral) {
1977    unsigned DefClass = DefMI->getDesc().getSchedClass();
1978    int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1979    return (DefCycle != -1 && DefCycle <= 2);
1980  }
1981  return false;
1982}
1983