ARMBaseInstrInfo.cpp revision d7d030a44796adc73a6eaa939cd17e52047734c1 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMHazardRecognizer.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMGenInstrInfo.inc"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/GlobalValue.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/ADT/STLExtras.h"
38using namespace llvm;
39
40static cl::opt<bool>
41EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
42               cl::desc("Enable ARM 2-addr to 3-addr conv"));
43
44/// ARM_MLxEntry - Record information about MLA / MLS instructions.
45struct ARM_MLxEntry {
46  unsigned MLxOpc;     // MLA / MLS opcode
47  unsigned MulOpc;     // Expanded multiplication opcode
48  unsigned AddSubOpc;  // Expanded add / sub opcode
49  bool NegAcc;         // True if the acc is negated before the add / sub.
50  bool HasLane;        // True if instruction has an extra "lane" operand.
51};
52
53static const ARM_MLxEntry ARM_MLxTable[] = {
54  // MLxOpc,          MulOpc,           AddSubOpc,       NegAcc, HasLane
55  // fp scalar ops
56  { ARM::VMLAS,       ARM::VMULS,       ARM::VADDS,      false,  false },
57  { ARM::VMLSS,       ARM::VMULS,       ARM::VSUBS,      false,  false },
58  { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
59  { ARM::VMLSD,       ARM::VMULD,       ARM::VSUBD,      false,  false },
60  { ARM::VNMLAS,      ARM::VNMULS,      ARM::VSUBS,      true,   false },
61  { ARM::VNMLSS,      ARM::VMULS,       ARM::VSUBS,      true,   false },
62  { ARM::VNMLAD,      ARM::VNMULD,      ARM::VSUBD,      true,   false },
63  { ARM::VNMLSD,      ARM::VMULD,       ARM::VSUBD,      true,   false },
64
65  // fp SIMD ops
66  { ARM::VMLAfd,      ARM::VMULfd,      ARM::VADDfd,     false,  false },
67  { ARM::VMLSfd,      ARM::VMULfd,      ARM::VSUBfd,     false,  false },
68  { ARM::VMLAfq,      ARM::VMULfq,      ARM::VADDfq,     false,  false },
69  { ARM::VMLSfq,      ARM::VMULfq,      ARM::VSUBfq,     false,  false },
70  { ARM::VMLAslfd,    ARM::VMULslfd,    ARM::VADDfd,     false,  true  },
71  { ARM::VMLSslfd,    ARM::VMULslfd,    ARM::VSUBfd,     false,  true  },
72  { ARM::VMLAslfq,    ARM::VMULslfq,    ARM::VADDfq,     false,  true  },
73  { ARM::VMLSslfq,    ARM::VMULslfq,    ARM::VSUBfq,     false,  true  },
74};
75
76ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
77  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
78    Subtarget(STI) {
79  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
80    if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
81      assert(false && "Duplicated entries?");
82    MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
83    MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
84  }
85}
86
87// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
88// currently defaults to no prepass hazard recognizer.
89ScheduleHazardRecognizer *ARMBaseInstrInfo::
90CreateTargetHazardRecognizer(const TargetMachine *TM,
91                             const ScheduleDAG *DAG) const {
92  if (usePreRAHazardRecognizer()) {
93    const InstrItineraryData *II = TM->getInstrItineraryData();
94    return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
95  }
96  return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
97}
98
99ScheduleHazardRecognizer *ARMBaseInstrInfo::
100CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
101                                   const ScheduleDAG *DAG) const {
102  if (Subtarget.isThumb2() || Subtarget.hasVFP2())
103    return (ScheduleHazardRecognizer *)
104      new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
105  return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
106}
107
108MachineInstr *
109ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
110                                        MachineBasicBlock::iterator &MBBI,
111                                        LiveVariables *LV) const {
112  // FIXME: Thumb2 support.
113
114  if (!EnableARM3Addr)
115    return NULL;
116
117  MachineInstr *MI = MBBI;
118  MachineFunction &MF = *MI->getParent()->getParent();
119  uint64_t TSFlags = MI->getDesc().TSFlags;
120  bool isPre = false;
121  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
122  default: return NULL;
123  case ARMII::IndexModePre:
124    isPre = true;
125    break;
126  case ARMII::IndexModePost:
127    break;
128  }
129
130  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
131  // operation.
132  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
133  if (MemOpc == 0)
134    return NULL;
135
136  MachineInstr *UpdateMI = NULL;
137  MachineInstr *MemMI = NULL;
138  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
139  const TargetInstrDesc &TID = MI->getDesc();
140  unsigned NumOps = TID.getNumOperands();
141  bool isLoad = !TID.mayStore();
142  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
143  const MachineOperand &Base = MI->getOperand(2);
144  const MachineOperand &Offset = MI->getOperand(NumOps-3);
145  unsigned WBReg = WB.getReg();
146  unsigned BaseReg = Base.getReg();
147  unsigned OffReg = Offset.getReg();
148  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
149  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
150  switch (AddrMode) {
151  default:
152    assert(false && "Unknown indexed op!");
153    return NULL;
154  case ARMII::AddrMode2: {
155    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
156    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
157    if (OffReg == 0) {
158      if (ARM_AM::getSOImmVal(Amt) == -1)
159        // Can't encode it in a so_imm operand. This transformation will
160        // add more than 1 instruction. Abandon!
161        return NULL;
162      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
163                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
164        .addReg(BaseReg).addImm(Amt)
165        .addImm(Pred).addReg(0).addReg(0);
166    } else if (Amt != 0) {
167      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
168      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
169      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
170                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
171        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
172        .addImm(Pred).addReg(0).addReg(0);
173    } else
174      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
176        .addReg(BaseReg).addReg(OffReg)
177        .addImm(Pred).addReg(0).addReg(0);
178    break;
179  }
180  case ARMII::AddrMode3 : {
181    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
182    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
183    if (OffReg == 0)
184      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
185      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
187        .addReg(BaseReg).addImm(Amt)
188        .addImm(Pred).addReg(0).addReg(0);
189    else
190      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
192        .addReg(BaseReg).addReg(OffReg)
193        .addImm(Pred).addReg(0).addReg(0);
194    break;
195  }
196  }
197
198  std::vector<MachineInstr*> NewMIs;
199  if (isPre) {
200    if (isLoad)
201      MemMI = BuildMI(MF, MI->getDebugLoc(),
202                      get(MemOpc), MI->getOperand(0).getReg())
203        .addReg(WBReg).addImm(0).addImm(Pred);
204    else
205      MemMI = BuildMI(MF, MI->getDebugLoc(),
206                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
207        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
208    NewMIs.push_back(MemMI);
209    NewMIs.push_back(UpdateMI);
210  } else {
211    if (isLoad)
212      MemMI = BuildMI(MF, MI->getDebugLoc(),
213                      get(MemOpc), MI->getOperand(0).getReg())
214        .addReg(BaseReg).addImm(0).addImm(Pred);
215    else
216      MemMI = BuildMI(MF, MI->getDebugLoc(),
217                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
218        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
219    if (WB.isDead())
220      UpdateMI->getOperand(0).setIsDead();
221    NewMIs.push_back(UpdateMI);
222    NewMIs.push_back(MemMI);
223  }
224
225  // Transfer LiveVariables states, kill / dead info.
226  if (LV) {
227    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228      MachineOperand &MO = MI->getOperand(i);
229      if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
230        unsigned Reg = MO.getReg();
231
232        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
233        if (MO.isDef()) {
234          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
235          if (MO.isDead())
236            LV->addVirtualRegisterDead(Reg, NewMI);
237        }
238        if (MO.isUse() && MO.isKill()) {
239          for (unsigned j = 0; j < 2; ++j) {
240            // Look at the two new MI's in reverse order.
241            MachineInstr *NewMI = NewMIs[j];
242            if (!NewMI->readsRegister(Reg))
243              continue;
244            LV->addVirtualRegisterKilled(Reg, NewMI);
245            if (VI.removeKill(MI))
246              VI.Kills.push_back(NewMI);
247            break;
248          }
249        }
250      }
251    }
252  }
253
254  MFI->insert(MBBI, NewMIs[1]);
255  MFI->insert(MBBI, NewMIs[0]);
256  return NewMIs[0];
257}
258
259// Branch analysis.
260bool
261ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
262                                MachineBasicBlock *&FBB,
263                                SmallVectorImpl<MachineOperand> &Cond,
264                                bool AllowModify) const {
265  // If the block has no terminators, it just falls into the block after it.
266  MachineBasicBlock::iterator I = MBB.end();
267  if (I == MBB.begin())
268    return false;
269  --I;
270  while (I->isDebugValue()) {
271    if (I == MBB.begin())
272      return false;
273    --I;
274  }
275  if (!isUnpredicatedTerminator(I))
276    return false;
277
278  // Get the last instruction in the block.
279  MachineInstr *LastInst = I;
280
281  // If there is only one terminator instruction, process it.
282  unsigned LastOpc = LastInst->getOpcode();
283  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
284    if (isUncondBranchOpcode(LastOpc)) {
285      TBB = LastInst->getOperand(0).getMBB();
286      return false;
287    }
288    if (isCondBranchOpcode(LastOpc)) {
289      // Block ends with fall-through condbranch.
290      TBB = LastInst->getOperand(0).getMBB();
291      Cond.push_back(LastInst->getOperand(1));
292      Cond.push_back(LastInst->getOperand(2));
293      return false;
294    }
295    return true;  // Can't handle indirect branch.
296  }
297
298  // Get the instruction before it if it is a terminator.
299  MachineInstr *SecondLastInst = I;
300  unsigned SecondLastOpc = SecondLastInst->getOpcode();
301
302  // If AllowModify is true and the block ends with two or more unconditional
303  // branches, delete all but the first unconditional branch.
304  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
305    while (isUncondBranchOpcode(SecondLastOpc)) {
306      LastInst->eraseFromParent();
307      LastInst = SecondLastInst;
308      LastOpc = LastInst->getOpcode();
309      if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
310        // Return now the only terminator is an unconditional branch.
311        TBB = LastInst->getOperand(0).getMBB();
312        return false;
313      } else {
314        SecondLastInst = I;
315        SecondLastOpc = SecondLastInst->getOpcode();
316      }
317    }
318  }
319
320  // If there are three terminators, we don't know what sort of block this is.
321  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
322    return true;
323
324  // If the block ends with a B and a Bcc, handle it.
325  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
326    TBB =  SecondLastInst->getOperand(0).getMBB();
327    Cond.push_back(SecondLastInst->getOperand(1));
328    Cond.push_back(SecondLastInst->getOperand(2));
329    FBB = LastInst->getOperand(0).getMBB();
330    return false;
331  }
332
333  // If the block ends with two unconditional branches, handle it.  The second
334  // one is not executed, so remove it.
335  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
336    TBB = SecondLastInst->getOperand(0).getMBB();
337    I = LastInst;
338    if (AllowModify)
339      I->eraseFromParent();
340    return false;
341  }
342
343  // ...likewise if it ends with a branch table followed by an unconditional
344  // branch. The branch folder can create these, and we must get rid of them for
345  // correctness of Thumb constant islands.
346  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
347       isIndirectBranchOpcode(SecondLastOpc)) &&
348      isUncondBranchOpcode(LastOpc)) {
349    I = LastInst;
350    if (AllowModify)
351      I->eraseFromParent();
352    return true;
353  }
354
355  // Otherwise, can't handle this.
356  return true;
357}
358
359
360unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
361  MachineBasicBlock::iterator I = MBB.end();
362  if (I == MBB.begin()) return 0;
363  --I;
364  while (I->isDebugValue()) {
365    if (I == MBB.begin())
366      return 0;
367    --I;
368  }
369  if (!isUncondBranchOpcode(I->getOpcode()) &&
370      !isCondBranchOpcode(I->getOpcode()))
371    return 0;
372
373  // Remove the branch.
374  I->eraseFromParent();
375
376  I = MBB.end();
377
378  if (I == MBB.begin()) return 1;
379  --I;
380  if (!isCondBranchOpcode(I->getOpcode()))
381    return 1;
382
383  // Remove the branch.
384  I->eraseFromParent();
385  return 2;
386}
387
388unsigned
389ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
390                               MachineBasicBlock *FBB,
391                               const SmallVectorImpl<MachineOperand> &Cond,
392                               DebugLoc DL) const {
393  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
394  int BOpc   = !AFI->isThumbFunction()
395    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
396  int BccOpc = !AFI->isThumbFunction()
397    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
398
399  // Shouldn't be a fall through.
400  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
401  assert((Cond.size() == 2 || Cond.size() == 0) &&
402         "ARM branch conditions have two components!");
403
404  if (FBB == 0) {
405    if (Cond.empty()) // Unconditional branch?
406      BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
407    else
408      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
409        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
410    return 1;
411  }
412
413  // Two-way conditional branch.
414  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
415    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
416  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
417  return 2;
418}
419
420bool ARMBaseInstrInfo::
421ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
422  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
423  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
424  return false;
425}
426
427bool ARMBaseInstrInfo::
428PredicateInstruction(MachineInstr *MI,
429                     const SmallVectorImpl<MachineOperand> &Pred) const {
430  unsigned Opc = MI->getOpcode();
431  if (isUncondBranchOpcode(Opc)) {
432    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
433    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
434    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
435    return true;
436  }
437
438  int PIdx = MI->findFirstPredOperandIdx();
439  if (PIdx != -1) {
440    MachineOperand &PMO = MI->getOperand(PIdx);
441    PMO.setImm(Pred[0].getImm());
442    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
443    return true;
444  }
445  return false;
446}
447
448bool ARMBaseInstrInfo::
449SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
450                  const SmallVectorImpl<MachineOperand> &Pred2) const {
451  if (Pred1.size() > 2 || Pred2.size() > 2)
452    return false;
453
454  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
455  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
456  if (CC1 == CC2)
457    return true;
458
459  switch (CC1) {
460  default:
461    return false;
462  case ARMCC::AL:
463    return true;
464  case ARMCC::HS:
465    return CC2 == ARMCC::HI;
466  case ARMCC::LS:
467    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
468  case ARMCC::GE:
469    return CC2 == ARMCC::GT;
470  case ARMCC::LE:
471    return CC2 == ARMCC::LT;
472  }
473}
474
475bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
476                                    std::vector<MachineOperand> &Pred) const {
477  // FIXME: This confuses implicit_def with optional CPSR def.
478  const TargetInstrDesc &TID = MI->getDesc();
479  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
480    return false;
481
482  bool Found = false;
483  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
484    const MachineOperand &MO = MI->getOperand(i);
485    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
486      Pred.push_back(MO);
487      Found = true;
488    }
489  }
490
491  return Found;
492}
493
494/// isPredicable - Return true if the specified instruction can be predicated.
495/// By default, this returns true for every instruction with a
496/// PredicateOperand.
497bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
498  const TargetInstrDesc &TID = MI->getDesc();
499  if (!TID.isPredicable())
500    return false;
501
502  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
503    ARMFunctionInfo *AFI =
504      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
505    return AFI->isThumb2Function();
506  }
507  return true;
508}
509
510/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
511LLVM_ATTRIBUTE_NOINLINE
512static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
513                                unsigned JTI);
514static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
515                                unsigned JTI) {
516  assert(JTI < JT.size());
517  return JT[JTI].MBBs.size();
518}
519
520/// GetInstSize - Return the size of the specified MachineInstr.
521///
522unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
523  const MachineBasicBlock &MBB = *MI->getParent();
524  const MachineFunction *MF = MBB.getParent();
525  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
526
527  // Basic size info comes from the TSFlags field.
528  const TargetInstrDesc &TID = MI->getDesc();
529  uint64_t TSFlags = TID.TSFlags;
530
531  unsigned Opc = MI->getOpcode();
532  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
533  default: {
534    // If this machine instr is an inline asm, measure it.
535    if (MI->getOpcode() == ARM::INLINEASM)
536      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
537    if (MI->isLabel())
538      return 0;
539    switch (Opc) {
540    default:
541      llvm_unreachable("Unknown or unset size field for instr!");
542    case TargetOpcode::IMPLICIT_DEF:
543    case TargetOpcode::KILL:
544    case TargetOpcode::PROLOG_LABEL:
545    case TargetOpcode::EH_LABEL:
546    case TargetOpcode::DBG_VALUE:
547      return 0;
548    }
549    break;
550  }
551  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
552  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
553  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
554  case ARMII::SizeSpecial: {
555    switch (Opc) {
556    case ARM::MOVi16_ga_pcrel:
557    case ARM::MOVTi16_ga_pcrel:
558    case ARM::t2MOVi16_ga_pcrel:
559    case ARM::t2MOVTi16_ga_pcrel:
560      return 4;
561    case ARM::MOVi32imm:
562    case ARM::t2MOVi32imm:
563      return 8;
564    case ARM::CONSTPOOL_ENTRY:
565      // If this machine instr is a constant pool entry, its size is recorded as
566      // operand #2.
567      return MI->getOperand(2).getImm();
568    case ARM::Int_eh_sjlj_longjmp:
569      return 16;
570    case ARM::tInt_eh_sjlj_longjmp:
571      return 10;
572    case ARM::Int_eh_sjlj_setjmp:
573    case ARM::Int_eh_sjlj_setjmp_nofp:
574      return 20;
575    case ARM::tInt_eh_sjlj_setjmp:
576    case ARM::t2Int_eh_sjlj_setjmp:
577    case ARM::t2Int_eh_sjlj_setjmp_nofp:
578      return 12;
579    case ARM::BR_JTr:
580    case ARM::BR_JTm:
581    case ARM::BR_JTadd:
582    case ARM::tBR_JTr:
583    case ARM::t2BR_JT:
584    case ARM::t2TBB_JT:
585    case ARM::t2TBH_JT: {
586      // These are jumptable branches, i.e. a branch followed by an inlined
587      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
588      // entry is one byte; TBH two byte each.
589      unsigned EntrySize = (Opc == ARM::t2TBB_JT)
590        ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
591      unsigned NumOps = TID.getNumOperands();
592      MachineOperand JTOP =
593        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
594      unsigned JTI = JTOP.getIndex();
595      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
596      assert(MJTI != 0);
597      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
598      assert(JTI < JT.size());
599      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
600      // 4 aligned. The assembler / linker may add 2 byte padding just before
601      // the JT entries.  The size does not include this padding; the
602      // constant islands pass does separate bookkeeping for it.
603      // FIXME: If we know the size of the function is less than (1 << 16) *2
604      // bytes, we can use 16-bit entries instead. Then there won't be an
605      // alignment issue.
606      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
607      unsigned NumEntries = getNumJTEntries(JT, JTI);
608      if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
609        // Make sure the instruction that follows TBB is 2-byte aligned.
610        // FIXME: Constant island pass should insert an "ALIGN" instruction
611        // instead.
612        ++NumEntries;
613      return NumEntries * EntrySize + InstSize;
614    }
615    default:
616      // Otherwise, pseudo-instruction sizes are zero.
617      return 0;
618    }
619  }
620  }
621  return 0; // Not reached
622}
623
624void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
625                                   MachineBasicBlock::iterator I, DebugLoc DL,
626                                   unsigned DestReg, unsigned SrcReg,
627                                   bool KillSrc) const {
628  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
629  bool GPRSrc  = ARM::GPRRegClass.contains(SrcReg);
630
631  if (GPRDest && GPRSrc) {
632    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
633                                  .addReg(SrcReg, getKillRegState(KillSrc))));
634    return;
635  }
636
637  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
638  bool SPRSrc  = ARM::SPRRegClass.contains(SrcReg);
639
640  unsigned Opc;
641  if (SPRDest && SPRSrc)
642    Opc = ARM::VMOVS;
643  else if (GPRDest && SPRSrc)
644    Opc = ARM::VMOVRS;
645  else if (SPRDest && GPRSrc)
646    Opc = ARM::VMOVSR;
647  else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
648    Opc = ARM::VMOVD;
649  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
650    Opc = ARM::VMOVQ;
651  else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
652    Opc = ARM::VMOVQQ;
653  else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
654    Opc = ARM::VMOVQQQQ;
655  else
656    llvm_unreachable("Impossible reg-to-reg copy");
657
658  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
659  MIB.addReg(SrcReg, getKillRegState(KillSrc));
660  if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
661    AddDefaultPred(MIB);
662}
663
664static const
665MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
666                             unsigned Reg, unsigned SubIdx, unsigned State,
667                             const TargetRegisterInfo *TRI) {
668  if (!SubIdx)
669    return MIB.addReg(Reg, State);
670
671  if (TargetRegisterInfo::isPhysicalRegister(Reg))
672    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
673  return MIB.addReg(Reg, State, SubIdx);
674}
675
676void ARMBaseInstrInfo::
677storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
678                    unsigned SrcReg, bool isKill, int FI,
679                    const TargetRegisterClass *RC,
680                    const TargetRegisterInfo *TRI) const {
681  DebugLoc DL;
682  if (I != MBB.end()) DL = I->getDebugLoc();
683  MachineFunction &MF = *MBB.getParent();
684  MachineFrameInfo &MFI = *MF.getFrameInfo();
685  unsigned Align = MFI.getObjectAlignment(FI);
686
687  MachineMemOperand *MMO =
688    MF.getMachineMemOperand(MachinePointerInfo(
689                                         PseudoSourceValue::getFixedStack(FI)),
690                            MachineMemOperand::MOStore,
691                            MFI.getObjectSize(FI),
692                            Align);
693
694  // tGPR is used sometimes in ARM instructions that need to avoid using
695  // certain registers.  Just treat it as GPR here. Likewise, rGPR.
696  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
697      || RC == ARM::rGPRRegisterClass)
698    RC = ARM::GPRRegisterClass;
699
700  switch (RC->getID()) {
701  case ARM::GPRRegClassID:
702    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
703                   .addReg(SrcReg, getKillRegState(isKill))
704                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
705    break;
706  case ARM::SPRRegClassID:
707    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
708                   .addReg(SrcReg, getKillRegState(isKill))
709                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
710    break;
711  case ARM::DPRRegClassID:
712  case ARM::DPR_VFP2RegClassID:
713  case ARM::DPR_8RegClassID:
714    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
715                   .addReg(SrcReg, getKillRegState(isKill))
716                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
717    break;
718  case ARM::QPRRegClassID:
719  case ARM::QPR_VFP2RegClassID:
720  case ARM::QPR_8RegClassID:
721    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
722      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
723                     .addFrameIndex(FI).addImm(16)
724                     .addReg(SrcReg, getKillRegState(isKill))
725                     .addMemOperand(MMO));
726    } else {
727      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
728                     .addReg(SrcReg, getKillRegState(isKill))
729                     .addFrameIndex(FI)
730                     .addMemOperand(MMO));
731    }
732    break;
733  case ARM::QQPRRegClassID:
734  case ARM::QQPR_VFP2RegClassID:
735    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
736      // FIXME: It's possible to only store part of the QQ register if the
737      // spilled def has a sub-register index.
738      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
739                     .addFrameIndex(FI).addImm(16)
740                     .addReg(SrcReg, getKillRegState(isKill))
741                     .addMemOperand(MMO));
742    } else {
743      MachineInstrBuilder MIB =
744        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
745                       .addFrameIndex(FI))
746        .addMemOperand(MMO);
747      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
748      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
749      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
750            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
751    }
752    break;
753  case ARM::QQQQPRRegClassID: {
754    MachineInstrBuilder MIB =
755      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
756                     .addFrameIndex(FI))
757      .addMemOperand(MMO);
758    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
759    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
760    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
761    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
762    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
763    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
764    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
765          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
766    break;
767  }
768  default:
769    llvm_unreachable("Unknown regclass!");
770  }
771}
772
773unsigned
774ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
775                                     int &FrameIndex) const {
776  switch (MI->getOpcode()) {
777  default: break;
778  case ARM::STRrs:
779  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
780    if (MI->getOperand(1).isFI() &&
781        MI->getOperand(2).isReg() &&
782        MI->getOperand(3).isImm() &&
783        MI->getOperand(2).getReg() == 0 &&
784        MI->getOperand(3).getImm() == 0) {
785      FrameIndex = MI->getOperand(1).getIndex();
786      return MI->getOperand(0).getReg();
787    }
788    break;
789  case ARM::STRi12:
790  case ARM::t2STRi12:
791  case ARM::tSpill:
792  case ARM::VSTRD:
793  case ARM::VSTRS:
794    if (MI->getOperand(1).isFI() &&
795        MI->getOperand(2).isImm() &&
796        MI->getOperand(2).getImm() == 0) {
797      FrameIndex = MI->getOperand(1).getIndex();
798      return MI->getOperand(0).getReg();
799    }
800    break;
801  case ARM::VST1q64Pseudo:
802    if (MI->getOperand(0).isFI() &&
803        MI->getOperand(2).getSubReg() == 0) {
804      FrameIndex = MI->getOperand(0).getIndex();
805      return MI->getOperand(2).getReg();
806    }
807    break;
808  case ARM::VSTMQIA:
809    if (MI->getOperand(1).isFI() &&
810        MI->getOperand(0).getSubReg() == 0) {
811      FrameIndex = MI->getOperand(1).getIndex();
812      return MI->getOperand(0).getReg();
813    }
814    break;
815  }
816
817  return 0;
818}
819
820void ARMBaseInstrInfo::
821loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
822                     unsigned DestReg, int FI,
823                     const TargetRegisterClass *RC,
824                     const TargetRegisterInfo *TRI) const {
825  DebugLoc DL;
826  if (I != MBB.end()) DL = I->getDebugLoc();
827  MachineFunction &MF = *MBB.getParent();
828  MachineFrameInfo &MFI = *MF.getFrameInfo();
829  unsigned Align = MFI.getObjectAlignment(FI);
830  MachineMemOperand *MMO =
831    MF.getMachineMemOperand(
832                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
833                            MachineMemOperand::MOLoad,
834                            MFI.getObjectSize(FI),
835                            Align);
836
837  // tGPR is used sometimes in ARM instructions that need to avoid using
838  // certain registers.  Just treat it as GPR here.
839  if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
840      || RC == ARM::rGPRRegisterClass)
841    RC = ARM::GPRRegisterClass;
842
843  switch (RC->getID()) {
844  case ARM::GPRRegClassID:
845    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
846                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
847    break;
848  case ARM::SPRRegClassID:
849    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
850                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
851    break;
852  case ARM::DPRRegClassID:
853  case ARM::DPR_VFP2RegClassID:
854  case ARM::DPR_8RegClassID:
855    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
856                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
857    break;
858  case ARM::QPRRegClassID:
859  case ARM::QPR_VFP2RegClassID:
860  case ARM::QPR_8RegClassID:
861    if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
862      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
863                     .addFrameIndex(FI).addImm(16)
864                     .addMemOperand(MMO));
865    } else {
866      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
867                     .addFrameIndex(FI)
868                     .addMemOperand(MMO));
869    }
870    break;
871  case ARM::QQPRRegClassID:
872  case ARM::QQPR_VFP2RegClassID:
873    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
874      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
875                     .addFrameIndex(FI).addImm(16)
876                     .addMemOperand(MMO));
877    } else {
878      MachineInstrBuilder MIB =
879        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
880                       .addFrameIndex(FI))
881        .addMemOperand(MMO);
882      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
883      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
884      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
885            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
886    }
887    break;
888  case ARM::QQQQPRRegClassID: {
889    MachineInstrBuilder MIB =
890      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
891                     .addFrameIndex(FI))
892      .addMemOperand(MMO);
893    MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
894    MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
895    MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
896    MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
897    MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
898    MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
899    MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
900    AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
901    break;
902  }
903  default:
904    llvm_unreachable("Unknown regclass!");
905  }
906}
907
908unsigned
909ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
910                                      int &FrameIndex) const {
911  switch (MI->getOpcode()) {
912  default: break;
913  case ARM::LDRrs:
914  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
915    if (MI->getOperand(1).isFI() &&
916        MI->getOperand(2).isReg() &&
917        MI->getOperand(3).isImm() &&
918        MI->getOperand(2).getReg() == 0 &&
919        MI->getOperand(3).getImm() == 0) {
920      FrameIndex = MI->getOperand(1).getIndex();
921      return MI->getOperand(0).getReg();
922    }
923    break;
924  case ARM::LDRi12:
925  case ARM::t2LDRi12:
926  case ARM::tRestore:
927  case ARM::VLDRD:
928  case ARM::VLDRS:
929    if (MI->getOperand(1).isFI() &&
930        MI->getOperand(2).isImm() &&
931        MI->getOperand(2).getImm() == 0) {
932      FrameIndex = MI->getOperand(1).getIndex();
933      return MI->getOperand(0).getReg();
934    }
935    break;
936  case ARM::VLD1q64Pseudo:
937    if (MI->getOperand(1).isFI() &&
938        MI->getOperand(0).getSubReg() == 0) {
939      FrameIndex = MI->getOperand(1).getIndex();
940      return MI->getOperand(0).getReg();
941    }
942    break;
943  case ARM::VLDMQIA:
944    if (MI->getOperand(1).isFI() &&
945        MI->getOperand(0).getSubReg() == 0) {
946      FrameIndex = MI->getOperand(1).getIndex();
947      return MI->getOperand(0).getReg();
948    }
949    break;
950  }
951
952  return 0;
953}
954
955MachineInstr*
956ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
957                                           int FrameIx, uint64_t Offset,
958                                           const MDNode *MDPtr,
959                                           DebugLoc DL) const {
960  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
961    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
962  return &*MIB;
963}
964
965/// Create a copy of a const pool value. Update CPI to the new index and return
966/// the label UID.
967static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
968  MachineConstantPool *MCP = MF.getConstantPool();
969  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
970
971  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
972  assert(MCPE.isMachineConstantPoolEntry() &&
973         "Expecting a machine constantpool entry!");
974  ARMConstantPoolValue *ACPV =
975    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
976
977  unsigned PCLabelId = AFI->createPICLabelUId();
978  ARMConstantPoolValue *NewCPV = 0;
979  // FIXME: The below assumes PIC relocation model and that the function
980  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
981  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
982  // instructions, so that's probably OK, but is PIC always correct when
983  // we get here?
984  if (ACPV->isGlobalValue())
985    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
986                                      ARMCP::CPValue, 4);
987  else if (ACPV->isExtSymbol())
988    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
989                                      ACPV->getSymbol(), PCLabelId, 4);
990  else if (ACPV->isBlockAddress())
991    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
992                                      ARMCP::CPBlockAddress, 4);
993  else if (ACPV->isLSDA())
994    NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
995                                      ARMCP::CPLSDA, 4);
996  else
997    llvm_unreachable("Unexpected ARM constantpool value type!!");
998  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
999  return PCLabelId;
1000}
1001
1002void ARMBaseInstrInfo::
1003reMaterialize(MachineBasicBlock &MBB,
1004              MachineBasicBlock::iterator I,
1005              unsigned DestReg, unsigned SubIdx,
1006              const MachineInstr *Orig,
1007              const TargetRegisterInfo &TRI) const {
1008  unsigned Opcode = Orig->getOpcode();
1009  switch (Opcode) {
1010  default: {
1011    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1012    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1013    MBB.insert(I, MI);
1014    break;
1015  }
1016  case ARM::tLDRpci_pic:
1017  case ARM::t2LDRpci_pic: {
1018    MachineFunction &MF = *MBB.getParent();
1019    unsigned CPI = Orig->getOperand(1).getIndex();
1020    unsigned PCLabelId = duplicateCPV(MF, CPI);
1021    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1022                                      DestReg)
1023      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1024    MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1025    break;
1026  }
1027  }
1028}
1029
1030MachineInstr *
1031ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1032  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1033  switch(Orig->getOpcode()) {
1034  case ARM::tLDRpci_pic:
1035  case ARM::t2LDRpci_pic: {
1036    unsigned CPI = Orig->getOperand(1).getIndex();
1037    unsigned PCLabelId = duplicateCPV(MF, CPI);
1038    Orig->getOperand(1).setIndex(CPI);
1039    Orig->getOperand(2).setImm(PCLabelId);
1040    break;
1041  }
1042  }
1043  return MI;
1044}
1045
1046bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1047                                        const MachineInstr *MI1,
1048                                        const MachineRegisterInfo *MRI) const {
1049  int Opcode = MI0->getOpcode();
1050  if (Opcode == ARM::t2LDRpci ||
1051      Opcode == ARM::t2LDRpci_pic ||
1052      Opcode == ARM::tLDRpci ||
1053      Opcode == ARM::tLDRpci_pic ||
1054      Opcode == ARM::MOV_ga_dyn ||
1055      Opcode == ARM::MOV_ga_pcrel ||
1056      Opcode == ARM::MOV_ga_pcrel_ldr ||
1057      Opcode == ARM::t2MOV_ga_dyn ||
1058      Opcode == ARM::t2MOV_ga_pcrel) {
1059    if (MI1->getOpcode() != Opcode)
1060      return false;
1061    if (MI0->getNumOperands() != MI1->getNumOperands())
1062      return false;
1063
1064    const MachineOperand &MO0 = MI0->getOperand(1);
1065    const MachineOperand &MO1 = MI1->getOperand(1);
1066    if (MO0.getOffset() != MO1.getOffset())
1067      return false;
1068
1069    if (Opcode == ARM::MOV_ga_dyn ||
1070        Opcode == ARM::MOV_ga_pcrel ||
1071        Opcode == ARM::MOV_ga_pcrel_ldr ||
1072        Opcode == ARM::t2MOV_ga_dyn ||
1073        Opcode == ARM::t2MOV_ga_pcrel)
1074      // Ignore the PC labels.
1075      return MO0.getGlobal() == MO1.getGlobal();
1076
1077    const MachineFunction *MF = MI0->getParent()->getParent();
1078    const MachineConstantPool *MCP = MF->getConstantPool();
1079    int CPI0 = MO0.getIndex();
1080    int CPI1 = MO1.getIndex();
1081    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1082    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1083    bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1084    bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1085    if (isARMCP0 && isARMCP1) {
1086      ARMConstantPoolValue *ACPV0 =
1087        static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1088      ARMConstantPoolValue *ACPV1 =
1089        static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1090      return ACPV0->hasSameValue(ACPV1);
1091    } else if (!isARMCP0 && !isARMCP1) {
1092      return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1093    }
1094    return false;
1095  } else if (Opcode == ARM::PICLDR) {
1096    if (MI1->getOpcode() != Opcode)
1097      return false;
1098    if (MI0->getNumOperands() != MI1->getNumOperands())
1099      return false;
1100
1101    unsigned Addr0 = MI0->getOperand(1).getReg();
1102    unsigned Addr1 = MI1->getOperand(1).getReg();
1103    if (Addr0 != Addr1) {
1104      if (!MRI ||
1105          !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1106          !TargetRegisterInfo::isVirtualRegister(Addr1))
1107        return false;
1108
1109      // This assumes SSA form.
1110      MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1111      MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1112      // Check if the loaded value, e.g. a constantpool of a global address, are
1113      // the same.
1114      if (!produceSameValue(Def0, Def1, MRI))
1115        return false;
1116    }
1117
1118    for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1119      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1120      const MachineOperand &MO0 = MI0->getOperand(i);
1121      const MachineOperand &MO1 = MI1->getOperand(i);
1122      if (!MO0.isIdenticalTo(MO1))
1123        return false;
1124    }
1125    return true;
1126  }
1127
1128  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1129}
1130
1131/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1132/// determine if two loads are loading from the same base address. It should
1133/// only return true if the base pointers are the same and the only differences
1134/// between the two addresses is the offset. It also returns the offsets by
1135/// reference.
1136bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1137                                               int64_t &Offset1,
1138                                               int64_t &Offset2) const {
1139  // Don't worry about Thumb: just ARM and Thumb2.
1140  if (Subtarget.isThumb1Only()) return false;
1141
1142  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1143    return false;
1144
1145  switch (Load1->getMachineOpcode()) {
1146  default:
1147    return false;
1148  case ARM::LDRi12:
1149  case ARM::LDRBi12:
1150  case ARM::LDRD:
1151  case ARM::LDRH:
1152  case ARM::LDRSB:
1153  case ARM::LDRSH:
1154  case ARM::VLDRD:
1155  case ARM::VLDRS:
1156  case ARM::t2LDRi8:
1157  case ARM::t2LDRDi8:
1158  case ARM::t2LDRSHi8:
1159  case ARM::t2LDRi12:
1160  case ARM::t2LDRSHi12:
1161    break;
1162  }
1163
1164  switch (Load2->getMachineOpcode()) {
1165  default:
1166    return false;
1167  case ARM::LDRi12:
1168  case ARM::LDRBi12:
1169  case ARM::LDRD:
1170  case ARM::LDRH:
1171  case ARM::LDRSB:
1172  case ARM::LDRSH:
1173  case ARM::VLDRD:
1174  case ARM::VLDRS:
1175  case ARM::t2LDRi8:
1176  case ARM::t2LDRDi8:
1177  case ARM::t2LDRSHi8:
1178  case ARM::t2LDRi12:
1179  case ARM::t2LDRSHi12:
1180    break;
1181  }
1182
1183  // Check if base addresses and chain operands match.
1184  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1185      Load1->getOperand(4) != Load2->getOperand(4))
1186    return false;
1187
1188  // Index should be Reg0.
1189  if (Load1->getOperand(3) != Load2->getOperand(3))
1190    return false;
1191
1192  // Determine the offsets.
1193  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1194      isa<ConstantSDNode>(Load2->getOperand(1))) {
1195    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1196    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1197    return true;
1198  }
1199
1200  return false;
1201}
1202
1203/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1204/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1205/// be scheduled togther. On some targets if two loads are loading from
1206/// addresses in the same cache line, it's better if they are scheduled
1207/// together. This function takes two integers that represent the load offsets
1208/// from the common base address. It returns true if it decides it's desirable
1209/// to schedule the two loads together. "NumLoads" is the number of loads that
1210/// have already been scheduled after Load1.
1211bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1212                                               int64_t Offset1, int64_t Offset2,
1213                                               unsigned NumLoads) const {
1214  // Don't worry about Thumb: just ARM and Thumb2.
1215  if (Subtarget.isThumb1Only()) return false;
1216
1217  assert(Offset2 > Offset1);
1218
1219  if ((Offset2 - Offset1) / 8 > 64)
1220    return false;
1221
1222  if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1223    return false;  // FIXME: overly conservative?
1224
1225  // Four loads in a row should be sufficient.
1226  if (NumLoads >= 3)
1227    return false;
1228
1229  return true;
1230}
1231
1232bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1233                                            const MachineBasicBlock *MBB,
1234                                            const MachineFunction &MF) const {
1235  // Debug info is never a scheduling boundary. It's necessary to be explicit
1236  // due to the special treatment of IT instructions below, otherwise a
1237  // dbg_value followed by an IT will result in the IT instruction being
1238  // considered a scheduling hazard, which is wrong. It should be the actual
1239  // instruction preceding the dbg_value instruction(s), just like it is
1240  // when debug info is not present.
1241  if (MI->isDebugValue())
1242    return false;
1243
1244  // Terminators and labels can't be scheduled around.
1245  if (MI->getDesc().isTerminator() || MI->isLabel())
1246    return true;
1247
1248  // Treat the start of the IT block as a scheduling boundary, but schedule
1249  // t2IT along with all instructions following it.
1250  // FIXME: This is a big hammer. But the alternative is to add all potential
1251  // true and anti dependencies to IT block instructions as implicit operands
1252  // to the t2IT instruction. The added compile time and complexity does not
1253  // seem worth it.
1254  MachineBasicBlock::const_iterator I = MI;
1255  // Make sure to skip any dbg_value instructions
1256  while (++I != MBB->end() && I->isDebugValue())
1257    ;
1258  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1259    return true;
1260
1261  // Don't attempt to schedule around any instruction that defines
1262  // a stack-oriented pointer, as it's unlikely to be profitable. This
1263  // saves compile time, because it doesn't require every single
1264  // stack slot reference to depend on the instruction that does the
1265  // modification.
1266  if (MI->definesRegister(ARM::SP))
1267    return true;
1268
1269  return false;
1270}
1271
1272bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1273                                           unsigned NumCycles,
1274                                           unsigned ExtraPredCycles,
1275                                           float Probability,
1276                                           float Confidence) const {
1277  if (!NumCycles)
1278    return false;
1279
1280  // Attempt to estimate the relative costs of predication versus branching.
1281  float UnpredCost = Probability * NumCycles;
1282  UnpredCost += 1.0; // The branch itself
1283  UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1284
1285  return (float)(NumCycles + ExtraPredCycles) < UnpredCost;
1286}
1287
1288bool ARMBaseInstrInfo::
1289isProfitableToIfCvt(MachineBasicBlock &TMBB,
1290                    unsigned TCycles, unsigned TExtra,
1291                    MachineBasicBlock &FMBB,
1292                    unsigned FCycles, unsigned FExtra,
1293                    float Probability, float Confidence) const {
1294  if (!TCycles || !FCycles)
1295    return false;
1296
1297  // Attempt to estimate the relative costs of predication versus branching.
1298  float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles;
1299  UnpredCost += 1.0; // The branch itself
1300  UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1301
1302  return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost;
1303}
1304
1305/// getInstrPredicate - If instruction is predicated, returns its predicate
1306/// condition, otherwise returns AL. It also returns the condition code
1307/// register by reference.
1308ARMCC::CondCodes
1309llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1310  int PIdx = MI->findFirstPredOperandIdx();
1311  if (PIdx == -1) {
1312    PredReg = 0;
1313    return ARMCC::AL;
1314  }
1315
1316  PredReg = MI->getOperand(PIdx+1).getReg();
1317  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1318}
1319
1320
1321int llvm::getMatchingCondBranchOpcode(int Opc) {
1322  if (Opc == ARM::B)
1323    return ARM::Bcc;
1324  else if (Opc == ARM::tB)
1325    return ARM::tBcc;
1326  else if (Opc == ARM::t2B)
1327      return ARM::t2Bcc;
1328
1329  llvm_unreachable("Unknown unconditional branch opcode!");
1330  return 0;
1331}
1332
1333
1334void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1335                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1336                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1337                               ARMCC::CondCodes Pred, unsigned PredReg,
1338                               const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1339  bool isSub = NumBytes < 0;
1340  if (isSub) NumBytes = -NumBytes;
1341
1342  while (NumBytes) {
1343    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1344    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1345    assert(ThisVal && "Didn't extract field correctly");
1346
1347    // We will handle these bits from offset, clear them.
1348    NumBytes &= ~ThisVal;
1349
1350    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1351
1352    // Build the new ADD / SUB.
1353    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1354    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1355      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1356      .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1357      .setMIFlags(MIFlags);
1358    BaseReg = DestReg;
1359  }
1360}
1361
1362bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1363                                unsigned FrameReg, int &Offset,
1364                                const ARMBaseInstrInfo &TII) {
1365  unsigned Opcode = MI.getOpcode();
1366  const TargetInstrDesc &Desc = MI.getDesc();
1367  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1368  bool isSub = false;
1369
1370  // Memory operands in inline assembly always use AddrMode2.
1371  if (Opcode == ARM::INLINEASM)
1372    AddrMode = ARMII::AddrMode2;
1373
1374  if (Opcode == ARM::ADDri) {
1375    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1376    if (Offset == 0) {
1377      // Turn it into a move.
1378      MI.setDesc(TII.get(ARM::MOVr));
1379      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1380      MI.RemoveOperand(FrameRegIdx+1);
1381      Offset = 0;
1382      return true;
1383    } else if (Offset < 0) {
1384      Offset = -Offset;
1385      isSub = true;
1386      MI.setDesc(TII.get(ARM::SUBri));
1387    }
1388
1389    // Common case: small offset, fits into instruction.
1390    if (ARM_AM::getSOImmVal(Offset) != -1) {
1391      // Replace the FrameIndex with sp / fp
1392      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1393      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1394      Offset = 0;
1395      return true;
1396    }
1397
1398    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1399    // as possible.
1400    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1401    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1402
1403    // We will handle these bits from offset, clear them.
1404    Offset &= ~ThisImmVal;
1405
1406    // Get the properly encoded SOImmVal field.
1407    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1408           "Bit extraction didn't work?");
1409    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1410 } else {
1411    unsigned ImmIdx = 0;
1412    int InstrOffs = 0;
1413    unsigned NumBits = 0;
1414    unsigned Scale = 1;
1415    switch (AddrMode) {
1416    case ARMII::AddrMode_i12: {
1417      ImmIdx = FrameRegIdx + 1;
1418      InstrOffs = MI.getOperand(ImmIdx).getImm();
1419      NumBits = 12;
1420      break;
1421    }
1422    case ARMII::AddrMode2: {
1423      ImmIdx = FrameRegIdx+2;
1424      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1425      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1426        InstrOffs *= -1;
1427      NumBits = 12;
1428      break;
1429    }
1430    case ARMII::AddrMode3: {
1431      ImmIdx = FrameRegIdx+2;
1432      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1433      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1434        InstrOffs *= -1;
1435      NumBits = 8;
1436      break;
1437    }
1438    case ARMII::AddrMode4:
1439    case ARMII::AddrMode6:
1440      // Can't fold any offset even if it's zero.
1441      return false;
1442    case ARMII::AddrMode5: {
1443      ImmIdx = FrameRegIdx+1;
1444      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1445      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1446        InstrOffs *= -1;
1447      NumBits = 8;
1448      Scale = 4;
1449      break;
1450    }
1451    default:
1452      llvm_unreachable("Unsupported addressing mode!");
1453      break;
1454    }
1455
1456    Offset += InstrOffs * Scale;
1457    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1458    if (Offset < 0) {
1459      Offset = -Offset;
1460      isSub = true;
1461    }
1462
1463    // Attempt to fold address comp. if opcode has offset bits
1464    if (NumBits > 0) {
1465      // Common case: small offset, fits into instruction.
1466      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1467      int ImmedOffset = Offset / Scale;
1468      unsigned Mask = (1 << NumBits) - 1;
1469      if ((unsigned)Offset <= Mask * Scale) {
1470        // Replace the FrameIndex with sp
1471        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1472        // FIXME: When addrmode2 goes away, this will simplify (like the
1473        // T2 version), as the LDR.i12 versions don't need the encoding
1474        // tricks for the offset value.
1475        if (isSub) {
1476          if (AddrMode == ARMII::AddrMode_i12)
1477            ImmedOffset = -ImmedOffset;
1478          else
1479            ImmedOffset |= 1 << NumBits;
1480        }
1481        ImmOp.ChangeToImmediate(ImmedOffset);
1482        Offset = 0;
1483        return true;
1484      }
1485
1486      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1487      ImmedOffset = ImmedOffset & Mask;
1488      if (isSub) {
1489        if (AddrMode == ARMII::AddrMode_i12)
1490          ImmedOffset = -ImmedOffset;
1491        else
1492          ImmedOffset |= 1 << NumBits;
1493      }
1494      ImmOp.ChangeToImmediate(ImmedOffset);
1495      Offset &= ~(Mask*Scale);
1496    }
1497  }
1498
1499  Offset = (isSub) ? -Offset : Offset;
1500  return Offset == 0;
1501}
1502
1503bool ARMBaseInstrInfo::
1504AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1505               int &CmpValue) const {
1506  switch (MI->getOpcode()) {
1507  default: break;
1508  case ARM::CMPri:
1509  case ARM::t2CMPri:
1510    SrcReg = MI->getOperand(0).getReg();
1511    CmpMask = ~0;
1512    CmpValue = MI->getOperand(1).getImm();
1513    return true;
1514  case ARM::TSTri:
1515  case ARM::t2TSTri:
1516    SrcReg = MI->getOperand(0).getReg();
1517    CmpMask = MI->getOperand(1).getImm();
1518    CmpValue = 0;
1519    return true;
1520  }
1521
1522  return false;
1523}
1524
1525/// isSuitableForMask - Identify a suitable 'and' instruction that
1526/// operates on the given source register and applies the same mask
1527/// as a 'tst' instruction. Provide a limited look-through for copies.
1528/// When successful, MI will hold the found instruction.
1529static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1530                              int CmpMask, bool CommonUse) {
1531  switch (MI->getOpcode()) {
1532    case ARM::ANDri:
1533    case ARM::t2ANDri:
1534      if (CmpMask != MI->getOperand(2).getImm())
1535        return false;
1536      if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1537        return true;
1538      break;
1539    case ARM::COPY: {
1540      // Walk down one instruction which is potentially an 'and'.
1541      const MachineInstr &Copy = *MI;
1542      MachineBasicBlock::iterator AND(
1543        llvm::next(MachineBasicBlock::iterator(MI)));
1544      if (AND == MI->getParent()->end()) return false;
1545      MI = AND;
1546      return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1547                               CmpMask, true);
1548    }
1549  }
1550
1551  return false;
1552}
1553
1554/// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1555/// comparison into one that sets the zero bit in the flags register.
1556bool ARMBaseInstrInfo::
1557OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1558                     int CmpValue, const MachineRegisterInfo *MRI) const {
1559  if (CmpValue != 0)
1560    return false;
1561
1562  MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1563  if (llvm::next(DI) != MRI->def_end())
1564    // Only support one definition.
1565    return false;
1566
1567  MachineInstr *MI = &*DI;
1568
1569  // Masked compares sometimes use the same register as the corresponding 'and'.
1570  if (CmpMask != ~0) {
1571    if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1572      MI = 0;
1573      for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1574           UE = MRI->use_end(); UI != UE; ++UI) {
1575        if (UI->getParent() != CmpInstr->getParent()) continue;
1576        MachineInstr *PotentialAND = &*UI;
1577        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1578          continue;
1579        MI = PotentialAND;
1580        break;
1581      }
1582      if (!MI) return false;
1583    }
1584  }
1585
1586  // Conservatively refuse to convert an instruction which isn't in the same BB
1587  // as the comparison.
1588  if (MI->getParent() != CmpInstr->getParent())
1589    return false;
1590
1591  // Check that CPSR isn't set between the comparison instruction and the one we
1592  // want to change.
1593  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1594    B = MI->getParent()->begin();
1595
1596  // Early exit if CmpInstr is at the beginning of the BB.
1597  if (I == B) return false;
1598
1599  --I;
1600  for (; I != E; --I) {
1601    const MachineInstr &Instr = *I;
1602
1603    for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1604      const MachineOperand &MO = Instr.getOperand(IO);
1605      if (!MO.isReg()) continue;
1606
1607      // This instruction modifies or uses CPSR after the one we want to
1608      // change. We can't do this transformation.
1609      if (MO.getReg() == ARM::CPSR)
1610        return false;
1611    }
1612
1613    if (I == B)
1614      // The 'and' is below the comparison instruction.
1615      return false;
1616  }
1617
1618  // Set the "zero" bit in CPSR.
1619  switch (MI->getOpcode()) {
1620  default: break;
1621  case ARM::RSBrr:
1622  case ARM::RSBri:
1623  case ARM::RSCrr:
1624  case ARM::RSCri:
1625  case ARM::ADDrr:
1626  case ARM::ADDri:
1627  case ARM::ADCrr:
1628  case ARM::ADCri:
1629  case ARM::SUBrr:
1630  case ARM::SUBri:
1631  case ARM::SBCrr:
1632  case ARM::SBCri:
1633  case ARM::t2RSBri:
1634  case ARM::t2ADDrr:
1635  case ARM::t2ADDri:
1636  case ARM::t2ADCrr:
1637  case ARM::t2ADCri:
1638  case ARM::t2SUBrr:
1639  case ARM::t2SUBri:
1640  case ARM::t2SBCrr:
1641  case ARM::t2SBCri:
1642  case ARM::ANDrr:
1643  case ARM::ANDri:
1644  case ARM::t2ANDrr:
1645  case ARM::t2ANDri:
1646  case ARM::ORRrr:
1647  case ARM::ORRri:
1648  case ARM::t2ORRrr:
1649  case ARM::t2ORRri:
1650  case ARM::EORrr:
1651  case ARM::EORri:
1652  case ARM::t2EORrr:
1653  case ARM::t2EORri: {
1654    // Scan forward for the use of CPSR, if it's a conditional code requires
1655    // checking of V bit, then this is not safe to do. If we can't find the
1656    // CPSR use (i.e. used in another block), then it's not safe to perform
1657    // the optimization.
1658    bool isSafe = false;
1659    I = CmpInstr;
1660    E = MI->getParent()->end();
1661    while (!isSafe && ++I != E) {
1662      const MachineInstr &Instr = *I;
1663      for (unsigned IO = 0, EO = Instr.getNumOperands();
1664           !isSafe && IO != EO; ++IO) {
1665        const MachineOperand &MO = Instr.getOperand(IO);
1666        if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1667          continue;
1668        if (MO.isDef()) {
1669          isSafe = true;
1670          break;
1671        }
1672        // Condition code is after the operand before CPSR.
1673        ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1674        switch (CC) {
1675        default:
1676          isSafe = true;
1677          break;
1678        case ARMCC::VS:
1679        case ARMCC::VC:
1680        case ARMCC::GE:
1681        case ARMCC::LT:
1682        case ARMCC::GT:
1683        case ARMCC::LE:
1684          return false;
1685        }
1686      }
1687    }
1688
1689    if (!isSafe)
1690      return false;
1691
1692    // Toggle the optional operand to CPSR.
1693    MI->getOperand(5).setReg(ARM::CPSR);
1694    MI->getOperand(5).setIsDef(true);
1695    CmpInstr->eraseFromParent();
1696    return true;
1697  }
1698  }
1699
1700  return false;
1701}
1702
1703bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1704                                     MachineInstr *DefMI, unsigned Reg,
1705                                     MachineRegisterInfo *MRI) const {
1706  // Fold large immediates into add, sub, or, xor.
1707  unsigned DefOpc = DefMI->getOpcode();
1708  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1709    return false;
1710  if (!DefMI->getOperand(1).isImm())
1711    // Could be t2MOVi32imm <ga:xx>
1712    return false;
1713
1714  if (!MRI->hasOneNonDBGUse(Reg))
1715    return false;
1716
1717  unsigned UseOpc = UseMI->getOpcode();
1718  unsigned NewUseOpc = 0;
1719  uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1720  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1721  bool Commute = false;
1722  switch (UseOpc) {
1723  default: return false;
1724  case ARM::SUBrr:
1725  case ARM::ADDrr:
1726  case ARM::ORRrr:
1727  case ARM::EORrr:
1728  case ARM::t2SUBrr:
1729  case ARM::t2ADDrr:
1730  case ARM::t2ORRrr:
1731  case ARM::t2EORrr: {
1732    Commute = UseMI->getOperand(2).getReg() != Reg;
1733    switch (UseOpc) {
1734    default: break;
1735    case ARM::SUBrr: {
1736      if (Commute)
1737        return false;
1738      ImmVal = -ImmVal;
1739      NewUseOpc = ARM::SUBri;
1740      // Fallthrough
1741    }
1742    case ARM::ADDrr:
1743    case ARM::ORRrr:
1744    case ARM::EORrr: {
1745      if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1746        return false;
1747      SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1748      SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1749      switch (UseOpc) {
1750      default: break;
1751      case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1752      case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1753      case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1754      }
1755      break;
1756    }
1757    case ARM::t2SUBrr: {
1758      if (Commute)
1759        return false;
1760      ImmVal = -ImmVal;
1761      NewUseOpc = ARM::t2SUBri;
1762      // Fallthrough
1763    }
1764    case ARM::t2ADDrr:
1765    case ARM::t2ORRrr:
1766    case ARM::t2EORrr: {
1767      if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1768        return false;
1769      SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1770      SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1771      switch (UseOpc) {
1772      default: break;
1773      case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1774      case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1775      case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1776      }
1777      break;
1778    }
1779    }
1780  }
1781  }
1782
1783  unsigned OpIdx = Commute ? 2 : 1;
1784  unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1785  bool isKill = UseMI->getOperand(OpIdx).isKill();
1786  unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1787  AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1788                                      *UseMI, UseMI->getDebugLoc(),
1789                                      get(NewUseOpc), NewReg)
1790                              .addReg(Reg1, getKillRegState(isKill))
1791                              .addImm(SOImmValV1)));
1792  UseMI->setDesc(get(NewUseOpc));
1793  UseMI->getOperand(1).setReg(NewReg);
1794  UseMI->getOperand(1).setIsKill();
1795  UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1796  DefMI->eraseFromParent();
1797  return true;
1798}
1799
1800unsigned
1801ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1802                                 const MachineInstr *MI) const {
1803  if (!ItinData || ItinData->isEmpty())
1804    return 1;
1805
1806  const TargetInstrDesc &Desc = MI->getDesc();
1807  unsigned Class = Desc.getSchedClass();
1808  unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1809  if (UOps)
1810    return UOps;
1811
1812  unsigned Opc = MI->getOpcode();
1813  switch (Opc) {
1814  default:
1815    llvm_unreachable("Unexpected multi-uops instruction!");
1816    break;
1817  case ARM::VLDMQIA:
1818  case ARM::VSTMQIA:
1819    return 2;
1820
1821  // The number of uOps for load / store multiple are determined by the number
1822  // registers.
1823  //
1824  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1825  // same cycle. The scheduling for the first load / store must be done
1826  // separately by assuming the the address is not 64-bit aligned.
1827  //
1828  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1829  // is not 64-bit aligned, then AGU would take an extra cycle.  For VFP / NEON
1830  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1831  case ARM::VLDMDIA:
1832  case ARM::VLDMDIA_UPD:
1833  case ARM::VLDMDDB_UPD:
1834  case ARM::VLDMSIA:
1835  case ARM::VLDMSIA_UPD:
1836  case ARM::VLDMSDB_UPD:
1837  case ARM::VSTMDIA:
1838  case ARM::VSTMDIA_UPD:
1839  case ARM::VSTMDDB_UPD:
1840  case ARM::VSTMSIA:
1841  case ARM::VSTMSIA_UPD:
1842  case ARM::VSTMSDB_UPD: {
1843    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1844    return (NumRegs / 2) + (NumRegs % 2) + 1;
1845  }
1846
1847  case ARM::LDMIA_RET:
1848  case ARM::LDMIA:
1849  case ARM::LDMDA:
1850  case ARM::LDMDB:
1851  case ARM::LDMIB:
1852  case ARM::LDMIA_UPD:
1853  case ARM::LDMDA_UPD:
1854  case ARM::LDMDB_UPD:
1855  case ARM::LDMIB_UPD:
1856  case ARM::STMIA:
1857  case ARM::STMDA:
1858  case ARM::STMDB:
1859  case ARM::STMIB:
1860  case ARM::STMIA_UPD:
1861  case ARM::STMDA_UPD:
1862  case ARM::STMDB_UPD:
1863  case ARM::STMIB_UPD:
1864  case ARM::tLDMIA:
1865  case ARM::tLDMIA_UPD:
1866  case ARM::tSTMIA:
1867  case ARM::tSTMIA_UPD:
1868  case ARM::tPOP_RET:
1869  case ARM::tPOP:
1870  case ARM::tPUSH:
1871  case ARM::t2LDMIA_RET:
1872  case ARM::t2LDMIA:
1873  case ARM::t2LDMDB:
1874  case ARM::t2LDMIA_UPD:
1875  case ARM::t2LDMDB_UPD:
1876  case ARM::t2STMIA:
1877  case ARM::t2STMDB:
1878  case ARM::t2STMIA_UPD:
1879  case ARM::t2STMDB_UPD: {
1880    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1881    if (Subtarget.isCortexA8()) {
1882      if (NumRegs < 4)
1883        return 2;
1884      // 4 registers would be issued: 2, 2.
1885      // 5 registers would be issued: 2, 2, 1.
1886      UOps = (NumRegs / 2);
1887      if (NumRegs % 2)
1888        ++UOps;
1889      return UOps;
1890    } else if (Subtarget.isCortexA9()) {
1891      UOps = (NumRegs / 2);
1892      // If there are odd number of registers or if it's not 64-bit aligned,
1893      // then it takes an extra AGU (Address Generation Unit) cycle.
1894      if ((NumRegs % 2) ||
1895          !MI->hasOneMemOperand() ||
1896          (*MI->memoperands_begin())->getAlignment() < 8)
1897        ++UOps;
1898      return UOps;
1899    } else {
1900      // Assume the worst.
1901      return NumRegs;
1902    }
1903  }
1904  }
1905}
1906
1907int
1908ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1909                                  const TargetInstrDesc &DefTID,
1910                                  unsigned DefClass,
1911                                  unsigned DefIdx, unsigned DefAlign) const {
1912  int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1913  if (RegNo <= 0)
1914    // Def is the address writeback.
1915    return ItinData->getOperandCycle(DefClass, DefIdx);
1916
1917  int DefCycle;
1918  if (Subtarget.isCortexA8()) {
1919    // (regno / 2) + (regno % 2) + 1
1920    DefCycle = RegNo / 2 + 1;
1921    if (RegNo % 2)
1922      ++DefCycle;
1923  } else if (Subtarget.isCortexA9()) {
1924    DefCycle = RegNo;
1925    bool isSLoad = false;
1926
1927    switch (DefTID.getOpcode()) {
1928    default: break;
1929    case ARM::VLDMSIA:
1930    case ARM::VLDMSIA_UPD:
1931    case ARM::VLDMSDB_UPD:
1932      isSLoad = true;
1933      break;
1934    }
1935
1936    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1937    // then it takes an extra cycle.
1938    if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1939      ++DefCycle;
1940  } else {
1941    // Assume the worst.
1942    DefCycle = RegNo + 2;
1943  }
1944
1945  return DefCycle;
1946}
1947
1948int
1949ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1950                                 const TargetInstrDesc &DefTID,
1951                                 unsigned DefClass,
1952                                 unsigned DefIdx, unsigned DefAlign) const {
1953  int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1954  if (RegNo <= 0)
1955    // Def is the address writeback.
1956    return ItinData->getOperandCycle(DefClass, DefIdx);
1957
1958  int DefCycle;
1959  if (Subtarget.isCortexA8()) {
1960    // 4 registers would be issued: 1, 2, 1.
1961    // 5 registers would be issued: 1, 2, 2.
1962    DefCycle = RegNo / 2;
1963    if (DefCycle < 1)
1964      DefCycle = 1;
1965    // Result latency is issue cycle + 2: E2.
1966    DefCycle += 2;
1967  } else if (Subtarget.isCortexA9()) {
1968    DefCycle = (RegNo / 2);
1969    // If there are odd number of registers or if it's not 64-bit aligned,
1970    // then it takes an extra AGU (Address Generation Unit) cycle.
1971    if ((RegNo % 2) || DefAlign < 8)
1972      ++DefCycle;
1973    // Result latency is AGU cycles + 2.
1974    DefCycle += 2;
1975  } else {
1976    // Assume the worst.
1977    DefCycle = RegNo + 2;
1978  }
1979
1980  return DefCycle;
1981}
1982
1983int
1984ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1985                                  const TargetInstrDesc &UseTID,
1986                                  unsigned UseClass,
1987                                  unsigned UseIdx, unsigned UseAlign) const {
1988  int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1989  if (RegNo <= 0)
1990    return ItinData->getOperandCycle(UseClass, UseIdx);
1991
1992  int UseCycle;
1993  if (Subtarget.isCortexA8()) {
1994    // (regno / 2) + (regno % 2) + 1
1995    UseCycle = RegNo / 2 + 1;
1996    if (RegNo % 2)
1997      ++UseCycle;
1998  } else if (Subtarget.isCortexA9()) {
1999    UseCycle = RegNo;
2000    bool isSStore = false;
2001
2002    switch (UseTID.getOpcode()) {
2003    default: break;
2004    case ARM::VSTMSIA:
2005    case ARM::VSTMSIA_UPD:
2006    case ARM::VSTMSDB_UPD:
2007      isSStore = true;
2008      break;
2009    }
2010
2011    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2012    // then it takes an extra cycle.
2013    if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2014      ++UseCycle;
2015  } else {
2016    // Assume the worst.
2017    UseCycle = RegNo + 2;
2018  }
2019
2020  return UseCycle;
2021}
2022
2023int
2024ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2025                                 const TargetInstrDesc &UseTID,
2026                                 unsigned UseClass,
2027                                 unsigned UseIdx, unsigned UseAlign) const {
2028  int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
2029  if (RegNo <= 0)
2030    return ItinData->getOperandCycle(UseClass, UseIdx);
2031
2032  int UseCycle;
2033  if (Subtarget.isCortexA8()) {
2034    UseCycle = RegNo / 2;
2035    if (UseCycle < 2)
2036      UseCycle = 2;
2037    // Read in E3.
2038    UseCycle += 2;
2039  } else if (Subtarget.isCortexA9()) {
2040    UseCycle = (RegNo / 2);
2041    // If there are odd number of registers or if it's not 64-bit aligned,
2042    // then it takes an extra AGU (Address Generation Unit) cycle.
2043    if ((RegNo % 2) || UseAlign < 8)
2044      ++UseCycle;
2045  } else {
2046    // Assume the worst.
2047    UseCycle = 1;
2048  }
2049  return UseCycle;
2050}
2051
2052int
2053ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2054                                    const TargetInstrDesc &DefTID,
2055                                    unsigned DefIdx, unsigned DefAlign,
2056                                    const TargetInstrDesc &UseTID,
2057                                    unsigned UseIdx, unsigned UseAlign) const {
2058  unsigned DefClass = DefTID.getSchedClass();
2059  unsigned UseClass = UseTID.getSchedClass();
2060
2061  if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
2062    return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2063
2064  // This may be a def / use of a variable_ops instruction, the operand
2065  // latency might be determinable dynamically. Let the target try to
2066  // figure it out.
2067  int DefCycle = -1;
2068  bool LdmBypass = false;
2069  switch (DefTID.getOpcode()) {
2070  default:
2071    DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2072    break;
2073
2074  case ARM::VLDMDIA:
2075  case ARM::VLDMDIA_UPD:
2076  case ARM::VLDMDDB_UPD:
2077  case ARM::VLDMSIA:
2078  case ARM::VLDMSIA_UPD:
2079  case ARM::VLDMSDB_UPD:
2080    DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2081    break;
2082
2083  case ARM::LDMIA_RET:
2084  case ARM::LDMIA:
2085  case ARM::LDMDA:
2086  case ARM::LDMDB:
2087  case ARM::LDMIB:
2088  case ARM::LDMIA_UPD:
2089  case ARM::LDMDA_UPD:
2090  case ARM::LDMDB_UPD:
2091  case ARM::LDMIB_UPD:
2092  case ARM::tLDMIA:
2093  case ARM::tLDMIA_UPD:
2094  case ARM::tPUSH:
2095  case ARM::t2LDMIA_RET:
2096  case ARM::t2LDMIA:
2097  case ARM::t2LDMDB:
2098  case ARM::t2LDMIA_UPD:
2099  case ARM::t2LDMDB_UPD:
2100    LdmBypass = 1;
2101    DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2102    break;
2103  }
2104
2105  if (DefCycle == -1)
2106    // We can't seem to determine the result latency of the def, assume it's 2.
2107    DefCycle = 2;
2108
2109  int UseCycle = -1;
2110  switch (UseTID.getOpcode()) {
2111  default:
2112    UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2113    break;
2114
2115  case ARM::VSTMDIA:
2116  case ARM::VSTMDIA_UPD:
2117  case ARM::VSTMDDB_UPD:
2118  case ARM::VSTMSIA:
2119  case ARM::VSTMSIA_UPD:
2120  case ARM::VSTMSDB_UPD:
2121    UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2122    break;
2123
2124  case ARM::STMIA:
2125  case ARM::STMDA:
2126  case ARM::STMDB:
2127  case ARM::STMIB:
2128  case ARM::STMIA_UPD:
2129  case ARM::STMDA_UPD:
2130  case ARM::STMDB_UPD:
2131  case ARM::STMIB_UPD:
2132  case ARM::tSTMIA:
2133  case ARM::tSTMIA_UPD:
2134  case ARM::tPOP_RET:
2135  case ARM::tPOP:
2136  case ARM::t2STMIA:
2137  case ARM::t2STMDB:
2138  case ARM::t2STMIA_UPD:
2139  case ARM::t2STMDB_UPD:
2140    UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2141    break;
2142  }
2143
2144  if (UseCycle == -1)
2145    // Assume it's read in the first stage.
2146    UseCycle = 1;
2147
2148  UseCycle = DefCycle - UseCycle + 1;
2149  if (UseCycle > 0) {
2150    if (LdmBypass) {
2151      // It's a variable_ops instruction so we can't use DefIdx here. Just use
2152      // first def operand.
2153      if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
2154                                          UseClass, UseIdx))
2155        --UseCycle;
2156    } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2157                                               UseClass, UseIdx)) {
2158      --UseCycle;
2159    }
2160  }
2161
2162  return UseCycle;
2163}
2164
2165int
2166ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2167                             const MachineInstr *DefMI, unsigned DefIdx,
2168                             const MachineInstr *UseMI, unsigned UseIdx) const {
2169  if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2170      DefMI->isRegSequence() || DefMI->isImplicitDef())
2171    return 1;
2172
2173  const TargetInstrDesc &DefTID = DefMI->getDesc();
2174  if (!ItinData || ItinData->isEmpty())
2175    return DefTID.mayLoad() ? 3 : 1;
2176
2177  const TargetInstrDesc &UseTID = UseMI->getDesc();
2178  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2179  if (DefMO.getReg() == ARM::CPSR) {
2180    if (DefMI->getOpcode() == ARM::FMSTAT) {
2181      // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2182      return Subtarget.isCortexA9() ? 1 : 20;
2183    }
2184
2185    // CPSR set and branch can be paired in the same cycle.
2186    if (UseTID.isBranch())
2187      return 0;
2188  }
2189
2190  unsigned DefAlign = DefMI->hasOneMemOperand()
2191    ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2192  unsigned UseAlign = UseMI->hasOneMemOperand()
2193    ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2194  int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2195                                  UseTID, UseIdx, UseAlign);
2196
2197  if (Latency > 1 &&
2198      (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2199    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2200    // variants are one cycle cheaper.
2201    switch (DefTID.getOpcode()) {
2202    default: break;
2203    case ARM::LDRrs:
2204    case ARM::LDRBrs: {
2205      unsigned ShOpVal = DefMI->getOperand(3).getImm();
2206      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2207      if (ShImm == 0 ||
2208          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2209        --Latency;
2210      break;
2211    }
2212    case ARM::t2LDRs:
2213    case ARM::t2LDRBs:
2214    case ARM::t2LDRHs:
2215    case ARM::t2LDRSHs: {
2216      // Thumb2 mode: lsl only.
2217      unsigned ShAmt = DefMI->getOperand(3).getImm();
2218      if (ShAmt == 0 || ShAmt == 2)
2219        --Latency;
2220      break;
2221    }
2222    }
2223  }
2224
2225  if (DefAlign < 8 && Subtarget.isCortexA9())
2226    switch (DefTID.getOpcode()) {
2227    default: break;
2228    case ARM::VLD1q8:
2229    case ARM::VLD1q16:
2230    case ARM::VLD1q32:
2231    case ARM::VLD1q64:
2232    case ARM::VLD1q8_UPD:
2233    case ARM::VLD1q16_UPD:
2234    case ARM::VLD1q32_UPD:
2235    case ARM::VLD1q64_UPD:
2236    case ARM::VLD2d8:
2237    case ARM::VLD2d16:
2238    case ARM::VLD2d32:
2239    case ARM::VLD2q8:
2240    case ARM::VLD2q16:
2241    case ARM::VLD2q32:
2242    case ARM::VLD2d8_UPD:
2243    case ARM::VLD2d16_UPD:
2244    case ARM::VLD2d32_UPD:
2245    case ARM::VLD2q8_UPD:
2246    case ARM::VLD2q16_UPD:
2247    case ARM::VLD2q32_UPD:
2248    case ARM::VLD3d8:
2249    case ARM::VLD3d16:
2250    case ARM::VLD3d32:
2251    case ARM::VLD1d64T:
2252    case ARM::VLD3d8_UPD:
2253    case ARM::VLD3d16_UPD:
2254    case ARM::VLD3d32_UPD:
2255    case ARM::VLD1d64T_UPD:
2256    case ARM::VLD3q8_UPD:
2257    case ARM::VLD3q16_UPD:
2258    case ARM::VLD3q32_UPD:
2259    case ARM::VLD4d8:
2260    case ARM::VLD4d16:
2261    case ARM::VLD4d32:
2262    case ARM::VLD1d64Q:
2263    case ARM::VLD4d8_UPD:
2264    case ARM::VLD4d16_UPD:
2265    case ARM::VLD4d32_UPD:
2266    case ARM::VLD1d64Q_UPD:
2267    case ARM::VLD4q8_UPD:
2268    case ARM::VLD4q16_UPD:
2269    case ARM::VLD4q32_UPD:
2270    case ARM::VLD1DUPq8:
2271    case ARM::VLD1DUPq16:
2272    case ARM::VLD1DUPq32:
2273    case ARM::VLD1DUPq8_UPD:
2274    case ARM::VLD1DUPq16_UPD:
2275    case ARM::VLD1DUPq32_UPD:
2276    case ARM::VLD2DUPd8:
2277    case ARM::VLD2DUPd16:
2278    case ARM::VLD2DUPd32:
2279    case ARM::VLD2DUPd8_UPD:
2280    case ARM::VLD2DUPd16_UPD:
2281    case ARM::VLD2DUPd32_UPD:
2282    case ARM::VLD4DUPd8:
2283    case ARM::VLD4DUPd16:
2284    case ARM::VLD4DUPd32:
2285    case ARM::VLD4DUPd8_UPD:
2286    case ARM::VLD4DUPd16_UPD:
2287    case ARM::VLD4DUPd32_UPD:
2288    case ARM::VLD1LNd8:
2289    case ARM::VLD1LNd16:
2290    case ARM::VLD1LNd32:
2291    case ARM::VLD1LNd8_UPD:
2292    case ARM::VLD1LNd16_UPD:
2293    case ARM::VLD1LNd32_UPD:
2294    case ARM::VLD2LNd8:
2295    case ARM::VLD2LNd16:
2296    case ARM::VLD2LNd32:
2297    case ARM::VLD2LNq16:
2298    case ARM::VLD2LNq32:
2299    case ARM::VLD2LNd8_UPD:
2300    case ARM::VLD2LNd16_UPD:
2301    case ARM::VLD2LNd32_UPD:
2302    case ARM::VLD2LNq16_UPD:
2303    case ARM::VLD2LNq32_UPD:
2304    case ARM::VLD4LNd8:
2305    case ARM::VLD4LNd16:
2306    case ARM::VLD4LNd32:
2307    case ARM::VLD4LNq16:
2308    case ARM::VLD4LNq32:
2309    case ARM::VLD4LNd8_UPD:
2310    case ARM::VLD4LNd16_UPD:
2311    case ARM::VLD4LNd32_UPD:
2312    case ARM::VLD4LNq16_UPD:
2313    case ARM::VLD4LNq32_UPD:
2314      // If the address is not 64-bit aligned, the latencies of these
2315      // instructions increases by one.
2316      ++Latency;
2317      break;
2318    }
2319
2320  return Latency;
2321}
2322
2323int
2324ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2325                                    SDNode *DefNode, unsigned DefIdx,
2326                                    SDNode *UseNode, unsigned UseIdx) const {
2327  if (!DefNode->isMachineOpcode())
2328    return 1;
2329
2330  const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
2331
2332  if (isZeroCost(DefTID.Opcode))
2333    return 0;
2334
2335  if (!ItinData || ItinData->isEmpty())
2336    return DefTID.mayLoad() ? 3 : 1;
2337
2338  if (!UseNode->isMachineOpcode()) {
2339    int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
2340    if (Subtarget.isCortexA9())
2341      return Latency <= 2 ? 1 : Latency - 1;
2342    else
2343      return Latency <= 3 ? 1 : Latency - 2;
2344  }
2345
2346  const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
2347  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2348  unsigned DefAlign = !DefMN->memoperands_empty()
2349    ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2350  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2351  unsigned UseAlign = !UseMN->memoperands_empty()
2352    ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2353  int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2354                                  UseTID, UseIdx, UseAlign);
2355
2356  if (Latency > 1 &&
2357      (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2358    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2359    // variants are one cycle cheaper.
2360    switch (DefTID.getOpcode()) {
2361    default: break;
2362    case ARM::LDRrs:
2363    case ARM::LDRBrs: {
2364      unsigned ShOpVal =
2365        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2366      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2367      if (ShImm == 0 ||
2368          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2369        --Latency;
2370      break;
2371    }
2372    case ARM::t2LDRs:
2373    case ARM::t2LDRBs:
2374    case ARM::t2LDRHs:
2375    case ARM::t2LDRSHs: {
2376      // Thumb2 mode: lsl only.
2377      unsigned ShAmt =
2378        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2379      if (ShAmt == 0 || ShAmt == 2)
2380        --Latency;
2381      break;
2382    }
2383    }
2384  }
2385
2386  if (DefAlign < 8 && Subtarget.isCortexA9())
2387    switch (DefTID.getOpcode()) {
2388    default: break;
2389    case ARM::VLD1q8Pseudo:
2390    case ARM::VLD1q16Pseudo:
2391    case ARM::VLD1q32Pseudo:
2392    case ARM::VLD1q64Pseudo:
2393    case ARM::VLD1q8Pseudo_UPD:
2394    case ARM::VLD1q16Pseudo_UPD:
2395    case ARM::VLD1q32Pseudo_UPD:
2396    case ARM::VLD1q64Pseudo_UPD:
2397    case ARM::VLD2d8Pseudo:
2398    case ARM::VLD2d16Pseudo:
2399    case ARM::VLD2d32Pseudo:
2400    case ARM::VLD2q8Pseudo:
2401    case ARM::VLD2q16Pseudo:
2402    case ARM::VLD2q32Pseudo:
2403    case ARM::VLD2d8Pseudo_UPD:
2404    case ARM::VLD2d16Pseudo_UPD:
2405    case ARM::VLD2d32Pseudo_UPD:
2406    case ARM::VLD2q8Pseudo_UPD:
2407    case ARM::VLD2q16Pseudo_UPD:
2408    case ARM::VLD2q32Pseudo_UPD:
2409    case ARM::VLD3d8Pseudo:
2410    case ARM::VLD3d16Pseudo:
2411    case ARM::VLD3d32Pseudo:
2412    case ARM::VLD1d64TPseudo:
2413    case ARM::VLD3d8Pseudo_UPD:
2414    case ARM::VLD3d16Pseudo_UPD:
2415    case ARM::VLD3d32Pseudo_UPD:
2416    case ARM::VLD1d64TPseudo_UPD:
2417    case ARM::VLD3q8Pseudo_UPD:
2418    case ARM::VLD3q16Pseudo_UPD:
2419    case ARM::VLD3q32Pseudo_UPD:
2420    case ARM::VLD3q8oddPseudo:
2421    case ARM::VLD3q16oddPseudo:
2422    case ARM::VLD3q32oddPseudo:
2423    case ARM::VLD3q8oddPseudo_UPD:
2424    case ARM::VLD3q16oddPseudo_UPD:
2425    case ARM::VLD3q32oddPseudo_UPD:
2426    case ARM::VLD4d8Pseudo:
2427    case ARM::VLD4d16Pseudo:
2428    case ARM::VLD4d32Pseudo:
2429    case ARM::VLD1d64QPseudo:
2430    case ARM::VLD4d8Pseudo_UPD:
2431    case ARM::VLD4d16Pseudo_UPD:
2432    case ARM::VLD4d32Pseudo_UPD:
2433    case ARM::VLD1d64QPseudo_UPD:
2434    case ARM::VLD4q8Pseudo_UPD:
2435    case ARM::VLD4q16Pseudo_UPD:
2436    case ARM::VLD4q32Pseudo_UPD:
2437    case ARM::VLD4q8oddPseudo:
2438    case ARM::VLD4q16oddPseudo:
2439    case ARM::VLD4q32oddPseudo:
2440    case ARM::VLD4q8oddPseudo_UPD:
2441    case ARM::VLD4q16oddPseudo_UPD:
2442    case ARM::VLD4q32oddPseudo_UPD:
2443    case ARM::VLD1DUPq8Pseudo:
2444    case ARM::VLD1DUPq16Pseudo:
2445    case ARM::VLD1DUPq32Pseudo:
2446    case ARM::VLD1DUPq8Pseudo_UPD:
2447    case ARM::VLD1DUPq16Pseudo_UPD:
2448    case ARM::VLD1DUPq32Pseudo_UPD:
2449    case ARM::VLD2DUPd8Pseudo:
2450    case ARM::VLD2DUPd16Pseudo:
2451    case ARM::VLD2DUPd32Pseudo:
2452    case ARM::VLD2DUPd8Pseudo_UPD:
2453    case ARM::VLD2DUPd16Pseudo_UPD:
2454    case ARM::VLD2DUPd32Pseudo_UPD:
2455    case ARM::VLD4DUPd8Pseudo:
2456    case ARM::VLD4DUPd16Pseudo:
2457    case ARM::VLD4DUPd32Pseudo:
2458    case ARM::VLD4DUPd8Pseudo_UPD:
2459    case ARM::VLD4DUPd16Pseudo_UPD:
2460    case ARM::VLD4DUPd32Pseudo_UPD:
2461    case ARM::VLD1LNq8Pseudo:
2462    case ARM::VLD1LNq16Pseudo:
2463    case ARM::VLD1LNq32Pseudo:
2464    case ARM::VLD1LNq8Pseudo_UPD:
2465    case ARM::VLD1LNq16Pseudo_UPD:
2466    case ARM::VLD1LNq32Pseudo_UPD:
2467    case ARM::VLD2LNd8Pseudo:
2468    case ARM::VLD2LNd16Pseudo:
2469    case ARM::VLD2LNd32Pseudo:
2470    case ARM::VLD2LNq16Pseudo:
2471    case ARM::VLD2LNq32Pseudo:
2472    case ARM::VLD2LNd8Pseudo_UPD:
2473    case ARM::VLD2LNd16Pseudo_UPD:
2474    case ARM::VLD2LNd32Pseudo_UPD:
2475    case ARM::VLD2LNq16Pseudo_UPD:
2476    case ARM::VLD2LNq32Pseudo_UPD:
2477    case ARM::VLD4LNd8Pseudo:
2478    case ARM::VLD4LNd16Pseudo:
2479    case ARM::VLD4LNd32Pseudo:
2480    case ARM::VLD4LNq16Pseudo:
2481    case ARM::VLD4LNq32Pseudo:
2482    case ARM::VLD4LNd8Pseudo_UPD:
2483    case ARM::VLD4LNd16Pseudo_UPD:
2484    case ARM::VLD4LNd32Pseudo_UPD:
2485    case ARM::VLD4LNq16Pseudo_UPD:
2486    case ARM::VLD4LNq32Pseudo_UPD:
2487      // If the address is not 64-bit aligned, the latencies of these
2488      // instructions increases by one.
2489      ++Latency;
2490      break;
2491    }
2492
2493  return Latency;
2494}
2495
2496int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2497                                      const MachineInstr *MI,
2498                                      unsigned *PredCost) const {
2499  if (MI->isCopyLike() || MI->isInsertSubreg() ||
2500      MI->isRegSequence() || MI->isImplicitDef())
2501    return 1;
2502
2503  if (!ItinData || ItinData->isEmpty())
2504    return 1;
2505
2506  const TargetInstrDesc &TID = MI->getDesc();
2507  unsigned Class = TID.getSchedClass();
2508  unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2509  if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR))
2510    // When predicated, CPSR is an additional source operand for CPSR updating
2511    // instructions, this apparently increases their latencies.
2512    *PredCost = 1;
2513  if (UOps)
2514    return ItinData->getStageLatency(Class);
2515  return getNumMicroOps(ItinData, MI);
2516}
2517
2518int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2519                                      SDNode *Node) const {
2520  if (!Node->isMachineOpcode())
2521    return 1;
2522
2523  if (!ItinData || ItinData->isEmpty())
2524    return 1;
2525
2526  unsigned Opcode = Node->getMachineOpcode();
2527  switch (Opcode) {
2528  default:
2529    return ItinData->getStageLatency(get(Opcode).getSchedClass());
2530  case ARM::VLDMQIA:
2531  case ARM::VSTMQIA:
2532    return 2;
2533  }
2534}
2535
2536bool ARMBaseInstrInfo::
2537hasHighOperandLatency(const InstrItineraryData *ItinData,
2538                      const MachineRegisterInfo *MRI,
2539                      const MachineInstr *DefMI, unsigned DefIdx,
2540                      const MachineInstr *UseMI, unsigned UseIdx) const {
2541  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2542  unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2543  if (Subtarget.isCortexA8() &&
2544      (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2545    // CortexA8 VFP instructions are not pipelined.
2546    return true;
2547
2548  // Hoist VFP / NEON instructions with 4 or higher latency.
2549  int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2550  if (Latency <= 3)
2551    return false;
2552  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2553         UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2554}
2555
2556bool ARMBaseInstrInfo::
2557hasLowDefLatency(const InstrItineraryData *ItinData,
2558                 const MachineInstr *DefMI, unsigned DefIdx) const {
2559  if (!ItinData || ItinData->isEmpty())
2560    return false;
2561
2562  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2563  if (DDomain == ARMII::DomainGeneral) {
2564    unsigned DefClass = DefMI->getDesc().getSchedClass();
2565    int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2566    return (DefCycle != -1 && DefCycle <= 2);
2567  }
2568  return false;
2569}
2570
2571bool
2572ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2573                                     unsigned &AddSubOpc,
2574                                     bool &NegAcc, bool &HasLane) const {
2575  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2576  if (I == MLxEntryMap.end())
2577    return false;
2578
2579  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2580  MulOpc = Entry.MulOpc;
2581  AddSubOpc = Entry.AddSubOpc;
2582  NegAcc = Entry.NegAcc;
2583  HasLane = Entry.HasLane;
2584  return true;
2585}
2586