ARMSubtarget.h revision 29402132f3e890a2771818f44987ede213297431
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtarget. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetSubtarget.h" 20#include "ARMBaseRegisterInfo.h" 21#include <string> 22 23namespace llvm { 24class GlobalValue; 25 26class ARMSubtarget : public TargetSubtarget { 27protected: 28 enum ARMArchEnum { 29 V4, V4T, V5T, V5TE, V6, V6T2, V7A, V7M 30 }; 31 32 enum ARMFPEnum { 33 None, VFPv2, VFPv3, NEON 34 }; 35 36 enum ThumbTypeEnum { 37 Thumb1, 38 Thumb2 39 }; 40 41 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, 42 /// V6, V6T2, V7A, V7M. 43 ARMArchEnum ARMArchVersion; 44 45 /// ARMFPUType - Floating Point Unit type. 46 ARMFPEnum ARMFPUType; 47 48 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 49 /// specified. Use the method useNEONForSinglePrecisionFP() to 50 /// determine if NEON should actually be used. 51 bool UseNEONForSinglePrecisionFP; 52 53 /// SlowVMLx - If the VFP2 instructions are available, indicates whether 54 /// the VML[AS] instructions are slow (if so, don't use them). 55 bool SlowVMLx; 56 57 /// IsThumb - True if we are in thumb mode, false if in ARM mode. 58 bool IsThumb; 59 60 /// ThumbMode - Indicates supported Thumb version. 61 ThumbTypeEnum ThumbMode; 62 63 /// PostRAScheduler - True if using post-register-allocation scheduler. 64 bool PostRAScheduler; 65 66 /// IsR9Reserved - True if R9 is a not available as general purpose register. 67 bool IsR9Reserved; 68 69 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 70 /// imms (including global addresses). 71 bool UseMovt; 72 73 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 74 /// only so far) 75 bool HasFP16; 76 77 /// HasHardwareDivide - True if subtarget supports [su]div 78 bool HasHardwareDivide; 79 80 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 81 /// instructions. 82 bool HasT2ExtractPack; 83 84 /// stackAlignment - The minimum alignment known to hold of the stack frame on 85 /// entry to the function and which must be maintained by every function. 86 unsigned stackAlignment; 87 88 /// CPUString - String name of used CPU. 89 std::string CPUString; 90 91 /// Selected instruction itineraries (one entry per itinerary class.) 92 InstrItineraryData InstrItins; 93 94 public: 95 enum { 96 isELF, isDarwin 97 } TargetType; 98 99 enum { 100 ARM_ABI_APCS, 101 ARM_ABI_AAPCS // ARM EABI 102 } TargetABI; 103 104 /// This constructor initializes the data members to match that 105 /// of the specified triple. 106 /// 107 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb); 108 109 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 110 /// that still makes it profitable to inline the call. 111 unsigned getMaxInlineSizeThreshold() const { 112 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 113 // Change this once Thumb1 ldmia / stmia support is added. 114 return isThumb1Only() ? 0 : 64; 115 } 116 /// ParseSubtargetFeatures - Parses features string setting specified 117 /// subtarget options. Definition of function is auto generated by tblgen. 118 std::string ParseSubtargetFeatures(const std::string &FS, 119 const std::string &CPU); 120 121 bool hasV4TOps() const { return ARMArchVersion >= V4T; } 122 bool hasV5TOps() const { return ARMArchVersion >= V5T; } 123 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } 124 bool hasV6Ops() const { return ARMArchVersion >= V6; } 125 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } 126 bool hasV7Ops() const { return ARMArchVersion >= V7A; } 127 128 bool hasVFP2() const { return ARMFPUType >= VFPv2; } 129 bool hasVFP3() const { return ARMFPUType >= VFPv3; } 130 bool hasNEON() const { return ARMFPUType >= NEON; } 131 bool useNEONForSinglePrecisionFP() const { 132 return hasNEON() && UseNEONForSinglePrecisionFP; } 133 bool hasDivide() const { return HasHardwareDivide; }; 134 bool hasT2ExtractPack() const { return HasT2ExtractPack; }; 135 bool useVMLx() const {return hasVFP2() && !SlowVMLx; } 136 137 bool hasFP16() const { return HasFP16; } 138 139 bool isTargetDarwin() const { return TargetType == isDarwin; } 140 bool isTargetELF() const { return TargetType == isELF; } 141 142 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 143 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 144 145 bool isThumb() const { return IsThumb; } 146 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } 147 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } 148 bool hasThumb2() const { return ThumbMode >= Thumb2; } 149 150 bool isR9Reserved() const { return IsR9Reserved; } 151 152 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 153 154 const std::string & getCPUString() const { return CPUString; } 155 156 /// enablePostRAScheduler - True at 'More' optimization. 157 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 158 TargetSubtarget::AntiDepBreakMode& Mode, 159 RegClassVector& CriticalPathRCs) const; 160 161 /// getInstrItins - Return the instruction itineraies based on subtarget 162 /// selection. 163 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 164 165 /// getStackAlignment - Returns the minimum alignment known to hold of the 166 /// stack frame on entry to the function and which must be maintained by every 167 /// function for this subtarget. 168 unsigned getStackAlignment() const { return stackAlignment; } 169 170 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 171 /// symbol. 172 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 173}; 174} // End llvm namespace 175 176#endif // ARMSUBTARGET_H 177