History log of /external/llvm/lib/Target/ARM/ARMSubtarget.h
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
d43b5c97cff06d7840b974ca84fa0639d2567968 08-Aug-2012 Andrew Trick <atrick@apple.com> Added MispredictPenalty to SchedMachineModel.

This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
d598bd3aeea64fb0d2d3bd18de739a8a59cf043d 08-Aug-2012 Andrew Trick <atrick@apple.com> whitespace

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
bee78fe5fcd8464f58bc729dede1a87d763ac3ae 11-Apr-2012 Evan Cheng <evan.cheng@apple.com> Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
82509e5c62a99912c636b22e227b810eaf6eda78 11-Apr-2012 Evan Cheng <evan.cheng@apple.com> Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
74bebde7c4e2d1cfd4a16c19ce3c87521df67639 05-Mar-2012 Sebastian Pop <spop@codeaurora.org> updated patch for the ARM fused multiply add/sub

In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 28-Feb-2012 Evan Cheng <evan.cheng@apple.com> Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
20bd5296cec8d8d597ab9db2aca7346a88e580c8 28-Feb-2012 Daniel Dunbar <daniel@zuster.org> Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.

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ec52aaa12f57896fc806e849fa21a61603050ac4 28-Feb-2012 Evan Cheng <evan.cheng@apple.com> Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
4b4e62219be91839091f9e35d8accf877f925d81 22-Jan-2012 Anton Korobeynikov <asl@math.spbu.ru> Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!


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afff941211526a31f931aa9fcac84ae42ff60ef0 20-Dec-2011 Evan Cheng <evan.cheng@apple.com> ARM target code clean up. Check for iOS, not Darwin where it makes sense.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
44ee4714a8c245d4fdfd03840efcf58c3f66c6bc 09-Nov-2011 Evan Cheng <evan.cheng@apple.com> Hide cpu name checking in ARMSubtarget.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
928698b14e4bcd0f231dc28e246920a242d81fc1 18-Oct-2011 David Meyer <pdox@google.com> Remove NaClMode

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
6d2f9cec715c50bca44816d9bdea97f8b63bf2a0 07-Oct-2011 Bob Wilson <bob.wilson@apple.com> Reenable tail calls for iOS 5.0 and later.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
acad68da50581de905a994ed3c6b9c197bcea687 28-Sep-2011 James Molloy <james.molloy@arm.com> Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
1fac6b50ea720d75fc2bf01a288e99f239869e90 05-Sep-2011 Nick Lewycky <nicholas@mxc.ca> Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
4761a8d6549125e21d84371a9783bd41de2f55fa 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rewrite comment in English.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
963b03c1a9f6a9742671459f103ee9a566c6de58 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename attribute 'thumb' to a more descriptive 'thumb-mode'.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Compute feature bits at time of MCSubtargetInfo initialization.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

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94ca42ff0407d71bacc41de4032d8dbe6358d33d 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
385e930d55f3ecd3c9538823dfa5896a12461845 02-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

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a7603982dbf9e240ecc7ed6eddcd1cdb868107ac 01-Jul-2011 Jim Grosbach <grosbach@apple.com> ARMv7M vs. ARMv7E-M support.

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992



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5b1b4489cf3a0f56f8be0673fc5cc380a32d277b 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename TargetSubtarget to TargetSubtargetInfo for consistency.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
94214703d97d8d9dfca88174ffc7e94820a85e62 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
276365dd4bc0c2160f91fd8062ae1fc90c86c324 30-Jun-2011 Evan Cheng <evan.cheng@apple.com> Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
ab8be96fd30ca9396e6b84fdddf1ac6208984cad 29-Jun-2011 Evan Cheng <evan.cheng@apple.com> Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
0b65599015f0b51304d941ba4a14aaf0d1734341 20-May-2011 Evan Cheng <evan.cheng@apple.com> Revert accidental commit.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
2e6496026f41d2c05ff038d14df9972f8a27fb94 20-May-2011 Evan Cheng <evan.cheng@apple.com> Revert r131664 and fix it in instcombine instead. rdar://9467055

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
c8578948c9b35080dedd6527abf4f48fc4de43d3 21-Apr-2011 Evan Cheng <evan.cheng@apple.com> Remove -use-divmod-libcall. Let targets opt in when they are available.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
912225e18559a73228099330a4c253fdccf9fa3d 19-Apr-2011 Daniel Dunbar <daniel@zuster.org> ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
5dde893c2bac9e1569c38429f756c1d723e8edf2 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
463d358f1dfdd28a6900f2f109a160be71d2a8ef 31-Mar-2011 Evan Cheng <evan.cheng@apple.com> Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
b72d2a92b75daa9cbac7338aff0cd8ae04c2b4bd 11-Jan-2011 Evan Cheng <evan.cheng@apple.com> Clean up ARM subtarget code by using Triple ADT.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
2da8bc8a5f7705ac131184cd247f48500da0d74e 24-Dec-2010 Andrew Trick <atrick@apple.com> Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
6e8f4c404825b79f9b9176483653f1aa927dfbde 24-Dec-2010 Andrew Trick <atrick@apple.com> whitespace


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48575f6ea7d5cd21ab29ca370f58fcf9ca31400b 05-Dec-2010 Evan Cheng <evan.cheng@apple.com> Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
dfed19fe2c34c1209108afa58e8ab014ffd894e2 03-Nov-2010 Evan Cheng <evan.cheng@apple.com> Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
77f42b52781b6923924a93b8ab338d183887a592 12-Oct-2010 Bob Wilson <bob.wilson@apple.com> PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
0febc4657b0edbf16b55ca5365d2b6aab45be7c5 03-Oct-2010 Rafael Espindola <rafael.espindola@gmail.com> Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
so and also change X86 for consistency.

Investigating if this can be improved a bit.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
7122ba7efb5430d724ed3a0ac86fa7f7185b43ba 29-Sep-2010 Bob Wilson <bob.wilson@apple.com> Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
654d5440a477b1f6c89b051107e041a331f78e27 28-Sep-2010 Owen Anderson <resistor@mac.com> Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
02aba73a9ec04d0de9424422249af3948ca9573a 28-Sep-2010 Bob Wilson <bob.wilson@apple.com> Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it. Radar 8465431.


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3b9569e70db0b5a0d1389384a07fecbea8dc7dc2 27-Sep-2010 Daniel Dunbar <daniel@zuster.org> Hard to imagine there are still people using inferior compilers.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
fd9493d74e5429eab44638cd9badbad9090cd713 27-Sep-2010 Rafael Espindola <rafael.espindola@gmail.com> Odd additional stub framework for the ARM MC ELF emission.
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm

Patch by Jason Kim.

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/external/llvm/lib/Target/ARM/ARMSubtarget.h
3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 10-Sep-2010 Evan Cheng <evan.cheng@apple.com> Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
fcba5e6b645df89ae6b93911fe0f80b08fa6b44c 11-Aug-2010 Jim Grosbach <grosbach@apple.com> cortex m4 has floating point support, but only single precision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
7b4d31176efe6894bcfaa05257dd5783acda5ddc 11-Aug-2010 Evan Cheng <evan.cheng@apple.com> Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
d6b463225674c10511b00f8f631a89b6da5afc54 11-Aug-2010 Evan Cheng <evan.cheng@apple.com> Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
11db068721d44fd5f9b0c2a3a4c90f813d2eae9c 11-Aug-2010 Evan Cheng <evan.cheng@apple.com> - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
e44be6381609d31b2d8879dbd5107e01404fa475 09-Aug-2010 Evan Cheng <evan.cheng@apple.com> Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
7a415999625f9791a8a7eea2027e628e29de15c0 13-Jul-2010 Evan Cheng <evan.cheng@apple.com> Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
eae216c6d3d29cb9024ddf436a8f2ce222bb9ec8 06-May-2010 Shantonu Sen <ssen@apple.com> Fix "warning: extra ';' inside a struct or union" when building llvm with clang


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
29402132f3e890a2771818f44987ede213297431 06-May-2010 Jim Grosbach <grosbach@apple.com> Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
b1dc393bd56365ad8fabb51f22c2f3ace707c39a 05-May-2010 Jim Grosbach <grosbach@apple.com> Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
46510a73e977273ec67747eb34cbdb43f815e451 15-Apr-2010 Dan Gohman <gohman@apple.com> Add const qualifiers to CodeGen's use of LLVM IR constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
6b2e8dc9a0e4ebda645ee4eba95711eb630b4edf 26-Mar-2010 Jim Grosbach <grosbach@apple.com> switch the use-vml[as] instructions flag to a subtarget 'feature'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
2676737e5ed3e4b5c89b4d06b60d998e9318eb73 24-Mar-2010 Jim Grosbach <grosbach@apple.com> Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
631379e79c0971c5bac13629b8caf8912ed4c35c 14-Mar-2010 Anton Korobeynikov <asl@math.spbu.ru> Add substarget feature for FP16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
4d6113ee0699ac1eff46971881179de53e2eb810 11-Mar-2010 Bob Wilson <bob.wilson@apple.com> Lower small memcpys to load/stores on Thumb2.
Radar 7686922.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
ce7bf1c55f5238870bae2909cd368151f1d813d1 06-Mar-2010 Anton Korobeynikov <asl@math.spbu.ru> Initial bits of ARMv4-only support.
Patch by John Tytgat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
15217e63bce6c161b355b63d6496c7c327d15817 30-Nov-2009 Bob Wilson <bob.wilson@apple.com> Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
5cdc3a949af0cef7f2163f8a7acbf3049c226321 24-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
834b08af8d3d8fc6c76ac6ca40674565689e8d7f 18-Nov-2009 Bob Wilson <bob.wilson@apple.com> Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 13-Nov-2009 David Goodwin <david_goodwin@apple.com> Allow target to specify regclass for which antideps will only be broken along the critical path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 10-Nov-2009 David Goodwin <david_goodwin@apple.com> Fixed to address code review. No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
0855dee564f80160abf95497475306af38ab7f84 10-Nov-2009 David Goodwin <david_goodwin@apple.com> Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
2e7be612d5d0eb42ee3ae08194dbb03b750cc6bf 26-Oct-2009 David Goodwin <david_goodwin@apple.com> Break anti-dependence breaking out into its own class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
4c3715c2e5e17d7216a96ac2baf9720630f04408 23-Oct-2009 David Goodwin <david_goodwin@apple.com> Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
fa16354e0370fe884830286923352268b036737d 16-Oct-2009 Evan Cheng <evan.cheng@apple.com> Change createPostRAScheduler so it can be turned off at llc -O1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
0dad89fa94536284d51f60868326294b725a0c61 30-Sep-2009 David Goodwin <david_goodwin@apple.com> Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
63476a80404125e5196b6c09113c1d4796da0604 03-Sep-2009 Evan Cheng <evan.cheng@apple.com> Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c 29-Aug-2009 Evan Cheng <evan.cheng@apple.com> Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
764ab52dd80310a205c9888bf166d09dab858f90 11-Aug-2009 Jim Grosbach <grosbach@apple.com> Whitespace cleanup. Remove trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
1f0e404c87675ce75e34bcd91395c660fe1d4ac1 05-Aug-2009 David Goodwin <david_goodwin@apple.com> By default, for cortex-a8 use NEON for single-precision FP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
42a83f2d15cbbc08f5be19856198e3c885221e9c 04-Aug-2009 David Goodwin <david_goodwin@apple.com> Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
3be03406c9c3b2075d5ae416499af2f15f703d6f 03-Aug-2009 Daniel Dunbar <daniel@zuster.org> Normalize Subtarget constructors to take a target triple string instead of
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
3147fb2cff9ca0d258f8ab20ff23b9c447024df1 07-Jul-2009 Evan Cheng <evan.cheng@apple.com> isThumb2 really should mean thumb2 only, not thumb2+.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
d770d9e7d1f5c65b185897dcf226b3fc64598683 02-Jul-2009 Evan Cheng <evan.cheng@apple.com> Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
e481f127497b20d3abe625ca4c086f85bf8b126f 25-Jun-2009 Bob Wilson <bob.wilson@apple.com> Revert 74164. We'll want to use this method later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
c9028e69f11246a051c3de1457cd89d46e82ca60 25-Jun-2009 Bob Wilson <bob.wilson@apple.com> Remove unused hasV6T2Ops method. We already have a separate feature to
identify Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
8557c2bcb8002169d890eb8485e9a1d7219e4343 19-Jun-2009 Evan Cheng <evan.cheng@apple.com> Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
cd828618b8c6ec58df94aec0f5546f009f2fd0d5 19-Jun-2009 Evan Cheng <evan.cheng@apple.com> Remove UseThumbBacktraces. Just check if subtarget is darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
bb6296234238aab74a531b382d92342269bea902 15-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Rename methods for the sake of consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
fbbf1eeccf0cf469f0d8962b1341c8ba22a9dadb 08-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Separate V6 from V6T2 since the latter has some extra nice instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
a7b0ded2a26003d91db6c58d6ad945a39f70585c 08-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Add helper for checking of Thumb1 mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
70459bef9ccd73b3a2a44fdd62f2509861112745 01-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Implement review feedback. Make thumb2 'normal' subtarget feature

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
d4022c3fbb0705abdc8eddc3ee4a5059f5ef8094 30-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Add placeholder for thumb2 stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
6d7d2aa38a247426e2ccf53e3c6ad0315c9a4d8c 23-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Add ARMv7 architecture, Cortex processors and different FPU modes handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
41a024385f1220eadc48b48cb4c044a5fbc1b361 23-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Propagate CPU string out of SubtargetFeatures

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
707e0184233f27e0e9f9aee0309f2daab8cfe7f8 12-Apr-2008 Dan Gohman <gohman@apple.com> Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.


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/external/llvm/lib/Target/ARM/ARMSubtarget.h
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
e0703c84ddeb1a1276de4e38210c1127ef5df130 31-Oct-2007 Rafael Espindola <rafael.espindola@gmail.com> Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.

New I just have to move this to a common place :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
fc05f402ea22e8a9ae465d209b65be7e857a89ff 31-Oct-2007 Rafael Espindola <rafael.espindola@gmail.com> Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
04321f70f5075673934d5b1ed3353dd15d911183 23-Feb-2007 Evan Cheng <evan.cheng@apple.com> Added -march=thumb; removed -enable-thumb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
3630e78db9268dbe81a9369a33e49b857804f2ec 13-Feb-2007 Lauro Ramos Venancio <lauro.venancio@gmail.com> Add ABI information to ARM subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
1a3771e30e48b9cc21ccdc79fc9cf37ec4104b17 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> Introduce TargetType's ELF and Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
a8e2989ece6dc46df59b0768184028257f913843 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> ARM backend contribution from Apple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h