ARMSubtarget.h revision 0855dee564f80160abf95497475306af38ab7f84
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtarget. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetSubtarget.h" 20#include "ARMBaseRegisterInfo.h" 21#include <string> 22 23namespace llvm { 24class GlobalValue; 25 26class ARMSubtarget : public TargetSubtarget { 27protected: 28 enum ARMArchEnum { 29 V4T, V5T, V5TE, V6, V6T2, V7A 30 }; 31 32 enum ARMFPEnum { 33 None, VFPv2, VFPv3, NEON 34 }; 35 36 enum ThumbTypeEnum { 37 Thumb1, 38 Thumb2 39 }; 40 41 /// ARMArchVersion - ARM architecture version: V4T (base), V5T, V5TE, 42 /// V6, V6T2, V7A. 43 ARMArchEnum ARMArchVersion; 44 45 /// ARMFPUType - Floating Point Unit type. 46 ARMFPEnum ARMFPUType; 47 48 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 49 /// specified. Use the method useNEONForSinglePrecisionFP() to 50 /// determine if NEON should actually be used. 51 bool UseNEONForSinglePrecisionFP; 52 53 /// IsThumb - True if we are in thumb mode, false if in ARM mode. 54 bool IsThumb; 55 56 /// ThumbMode - Indicates supported Thumb version. 57 ThumbTypeEnum ThumbMode; 58 59 /// PostRAScheduler - True if using post-register-allocation scheduler. 60 bool PostRAScheduler; 61 62 /// IsR9Reserved - True if R9 is a not available as general purpose register. 63 bool IsR9Reserved; 64 65 /// stackAlignment - The minimum alignment known to hold of the stack frame on 66 /// entry to the function and which must be maintained by every function. 67 unsigned stackAlignment; 68 69 /// CPUString - String name of used CPU. 70 std::string CPUString; 71 72 /// Selected instruction itineraries (one entry per itinerary class.) 73 InstrItineraryData InstrItins; 74 75 public: 76 enum { 77 isELF, isDarwin 78 } TargetType; 79 80 enum { 81 ARM_ABI_APCS, 82 ARM_ABI_AAPCS // ARM EABI 83 } TargetABI; 84 85 /// This constructor initializes the data members to match that 86 /// of the specified triple. 87 /// 88 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb); 89 90 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 91 /// that still makes it profitable to inline the call. 92 unsigned getMaxInlineSizeThreshold() const { 93 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb. 94 // Change this once Thumb ldmia / stmia support is added. 95 return isThumb() ? 0 : 64; 96 } 97 /// ParseSubtargetFeatures - Parses features string setting specified 98 /// subtarget options. Definition of function is auto generated by tblgen. 99 std::string ParseSubtargetFeatures(const std::string &FS, 100 const std::string &CPU); 101 102 bool hasV4TOps() const { return ARMArchVersion >= V4T; } 103 bool hasV5TOps() const { return ARMArchVersion >= V5T; } 104 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } 105 bool hasV6Ops() const { return ARMArchVersion >= V6; } 106 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } 107 bool hasV7Ops() const { return ARMArchVersion >= V7A; } 108 109 bool hasVFP2() const { return ARMFPUType >= VFPv2; } 110 bool hasVFP3() const { return ARMFPUType >= VFPv3; } 111 bool hasNEON() const { return ARMFPUType >= NEON; } 112 bool useNEONForSinglePrecisionFP() const { 113 return hasNEON() && UseNEONForSinglePrecisionFP; } 114 115 bool isTargetDarwin() const { return TargetType == isDarwin; } 116 bool isTargetELF() const { return TargetType == isELF; } 117 118 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 119 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 120 121 bool isThumb() const { return IsThumb; } 122 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } 123 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } 124 bool hasThumb2() const { return ThumbMode >= Thumb2; } 125 126 bool isR9Reserved() const { return IsR9Reserved; } 127 128 const std::string & getCPUString() const { return CPUString; } 129 130 /// enablePostRAScheduler - True at 'More' optimization except 131 /// for Thumb1. 132 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 133 TargetSubtarget::AntiDepBreakMode& Mode, 134 ExcludedRCVector& ExcludedRCs) const { 135 Mode = TargetSubtarget::ANTIDEP_CRITICAL; 136 ExcludedRCs.clear(); 137 ExcludedRCs.push_back(&ARM::GPRRegClass); 138 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 139 } 140 141 /// getInstrItins - Return the instruction itineraies based on subtarget 142 /// selection. 143 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 144 145 /// getStackAlignment - Returns the minimum alignment known to hold of the 146 /// stack frame on entry to the function and which must be maintained by every 147 /// function for this subtarget. 148 unsigned getStackAlignment() const { return stackAlignment; } 149 150 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 151 /// symbol. 152 bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const; 153}; 154} // End llvm namespace 155 156#endif // ARMSUBTARGET_H 157