ARMSubtarget.h revision 4b4e62219be91839091f9e35d8accf877f925d81
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "MCTargetDesc/ARMMCTargetDesc.h" 18#include "llvm/Target/TargetSubtargetInfo.h" 19#include "llvm/MC/MCInstrItineraries.h" 20#include "llvm/ADT/Triple.h" 21#include <string> 22 23#define GET_SUBTARGETINFO_HEADER 24#include "ARMGenSubtargetInfo.inc" 25 26namespace llvm { 27class GlobalValue; 28class StringRef; 29 30class ARMSubtarget : public ARMGenSubtargetInfo { 31protected: 32 enum ARMProcFamilyEnum { 33 Others, CortexA8, CortexA9 34 }; 35 36 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 37 ARMProcFamilyEnum ARMProcFamily; 38 39 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops - 40 /// Specify whether target support specific ARM ISA variants. 41 bool HasV4TOps; 42 bool HasV5TOps; 43 bool HasV5TEOps; 44 bool HasV6Ops; 45 bool HasV6T2Ops; 46 bool HasV7Ops; 47 48 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON, HasNEONVFPv4 - Specify what 49 /// floating point ISAs are supported. 50 bool HasVFPv2; 51 bool HasVFPv3; 52 bool HasVFPv4; 53 bool HasNEON; 54 bool HasNEONVFPv4; 55 56 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 57 /// specified. Use the method useNEONForSinglePrecisionFP() to 58 /// determine if NEON should actually be used. 59 bool UseNEONForSinglePrecisionFP; 60 61 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 62 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 63 bool SlowFPVMLx; 64 65 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 66 /// forwarding to allow mul + mla being issued back to back. 67 bool HasVMLxForwarding; 68 69 /// SlowFPBrcc - True if floating point compare + branch is slow. 70 bool SlowFPBrcc; 71 72 /// InThumbMode - True if compiling for Thumb, false for ARM. 73 bool InThumbMode; 74 75 /// HasThumb2 - True if Thumb2 instructions are supported. 76 bool HasThumb2; 77 78 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs - 79 /// v6m, v7m for example. 80 bool IsMClass; 81 82 /// NoARM - True if subtarget does not support ARM mode execution. 83 bool NoARM; 84 85 /// PostRAScheduler - True if using post-register-allocation scheduler. 86 bool PostRAScheduler; 87 88 /// IsR9Reserved - True if R9 is a not available as general purpose register. 89 bool IsR9Reserved; 90 91 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 92 /// imms (including global addresses). 93 bool UseMovt; 94 95 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 96 /// must be able to synthesize call stubs for interworking between ARM and 97 /// Thumb. 98 bool SupportsTailCall; 99 100 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 101 /// only so far) 102 bool HasFP16; 103 104 /// HasD16 - True if subtarget is limited to 16 double precision 105 /// FP registers for VFPv3. 106 bool HasD16; 107 108 /// HasHardwareDivide - True if subtarget supports [su]div 109 bool HasHardwareDivide; 110 111 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 112 /// instructions. 113 bool HasT2ExtractPack; 114 115 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 116 /// instructions. 117 bool HasDataBarrier; 118 119 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 120 /// over 16-bit ones. 121 bool Pref32BitThumb; 122 123 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 124 /// that partially update CPSR and add false dependency on the previous 125 /// CPSR setting instruction. 126 bool AvoidCPSRPartialUpdate; 127 128 /// HasMPExtension - True if the subtarget supports Multiprocessing 129 /// extension (ARMv7 only). 130 bool HasMPExtension; 131 132 /// FPOnlySP - If true, the floating point unit only supports single 133 /// precision. 134 bool FPOnlySP; 135 136 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 137 /// accesses for some types. For details, see 138 /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). 139 bool AllowsUnalignedMem; 140 141 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith 142 /// and such) instructions in Thumb2 code. 143 bool Thumb2DSP; 144 145 /// stackAlignment - The minimum alignment known to hold of the stack frame on 146 /// entry to the function and which must be maintained by every function. 147 unsigned stackAlignment; 148 149 /// CPUString - String name of used CPU. 150 std::string CPUString; 151 152 /// TargetTriple - What processor and OS we're targeting. 153 Triple TargetTriple; 154 155 /// Selected instruction itineraries (one entry per itinerary class.) 156 InstrItineraryData InstrItins; 157 158 public: 159 enum { 160 isELF, isDarwin 161 } TargetType; 162 163 enum { 164 ARM_ABI_APCS, 165 ARM_ABI_AAPCS // ARM EABI 166 } TargetABI; 167 168 /// This constructor initializes the data members to match that 169 /// of the specified triple. 170 /// 171 ARMSubtarget(const std::string &TT, const std::string &CPU, 172 const std::string &FS); 173 174 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 175 /// that still makes it profitable to inline the call. 176 unsigned getMaxInlineSizeThreshold() const { 177 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 178 // Change this once Thumb1 ldmia / stmia support is added. 179 return isThumb1Only() ? 0 : 64; 180 } 181 /// ParseSubtargetFeatures - Parses features string setting specified 182 /// subtarget options. Definition of function is auto generated by tblgen. 183 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 184 185 void computeIssueWidth(); 186 187 bool hasV4TOps() const { return HasV4TOps; } 188 bool hasV5TOps() const { return HasV5TOps; } 189 bool hasV5TEOps() const { return HasV5TEOps; } 190 bool hasV6Ops() const { return HasV6Ops; } 191 bool hasV6T2Ops() const { return HasV6T2Ops; } 192 bool hasV7Ops() const { return HasV7Ops; } 193 194 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 195 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 196 bool isCortexM3() const { return CPUString == "cortex-m3"; } 197 198 bool hasARMOps() const { return !NoARM; } 199 200 bool hasVFP2() const { return HasVFPv2; } 201 bool hasVFP3() const { return HasVFPv3; } 202 bool hasVFP4() const { return HasVFPv4; } 203 bool hasNEON() const { return HasNEON; } 204 bool hasNEONVFP4() const { return HasNEONVFPv4; } 205 bool useNEONForSinglePrecisionFP() const { 206 return hasNEON() && UseNEONForSinglePrecisionFP; } 207 208 bool hasDivide() const { return HasHardwareDivide; } 209 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 210 bool hasDataBarrier() const { return HasDataBarrier; } 211 bool useFPVMLx() const { return !SlowFPVMLx; } 212 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 213 bool isFPBrccSlow() const { return SlowFPBrcc; } 214 bool isFPOnlySP() const { return FPOnlySP; } 215 bool prefers32BitThumb() const { return Pref32BitThumb; } 216 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 217 bool hasMPExtension() const { return HasMPExtension; } 218 bool hasThumb2DSP() const { return Thumb2DSP; } 219 220 bool hasFP16() const { return HasFP16; } 221 bool hasD16() const { return HasD16; } 222 223 const Triple &getTargetTriple() const { return TargetTriple; } 224 225 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; } 226 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 227 bool isTargetNaCl() const { 228 return TargetTriple.getOS() == Triple::NativeClient; 229 } 230 bool isTargetELF() const { return !isTargetDarwin(); } 231 232 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 233 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 234 235 bool isThumb() const { return InThumbMode; } 236 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } 237 bool isThumb2() const { return InThumbMode && HasThumb2; } 238 bool hasThumb2() const { return HasThumb2; } 239 bool isMClass() const { return IsMClass; } 240 bool isARClass() const { return !IsMClass; } 241 242 bool isR9Reserved() const { return IsR9Reserved; } 243 244 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 245 bool supportsTailCall() const { return SupportsTailCall; } 246 247 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 248 249 const std::string & getCPUString() const { return CPUString; } 250 251 unsigned getMispredictionPenalty() const; 252 253 /// enablePostRAScheduler - True at 'More' optimization. 254 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 255 TargetSubtargetInfo::AntiDepBreakMode& Mode, 256 RegClassVector& CriticalPathRCs) const; 257 258 /// getInstrItins - Return the instruction itineraies based on subtarget 259 /// selection. 260 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 261 262 /// getStackAlignment - Returns the minimum alignment known to hold of the 263 /// stack frame on entry to the function and which must be maintained by every 264 /// function for this subtarget. 265 unsigned getStackAlignment() const { return stackAlignment; } 266 267 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 268 /// symbol. 269 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 270}; 271} // End llvm namespace 272 273#endif // ARMSUBTARGET_H 274