ARMSubtarget.h revision a7603982dbf9e240ecc7ed6eddcd1cdb868107ac
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "llvm/Target/TargetSubtargetInfo.h" 18#include "llvm/MC/MCInstrItineraries.h" 19#include "llvm/ADT/Triple.h" 20#include <string> 21 22#define GET_SUBTARGETINFO_HEADER 23#include "ARMGenSubtarget.inc" 24 25namespace llvm { 26class GlobalValue; 27 28class ARMSubtarget : public ARMGenSubtargetInfo { 29protected: 30 enum ARMArchEnum { 31 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM 32 }; 33 34 enum ARMProcFamilyEnum { 35 Others, CortexA8, CortexA9 36 }; 37 38 enum ARMFPEnum { 39 None, VFPv2, VFPv3, NEON 40 }; 41 42 enum ThumbTypeEnum { 43 Thumb1, 44 Thumb2 45 }; 46 47 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, 48 /// V6, V6T2, V7A, V7M, V7EM. 49 ARMArchEnum ARMArchVersion; 50 51 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 52 ARMProcFamilyEnum ARMProcFamily; 53 54 /// ARMFPUType - Floating Point Unit type. 55 ARMFPEnum ARMFPUType; 56 57 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 58 /// specified. Use the method useNEONForSinglePrecisionFP() to 59 /// determine if NEON should actually be used. 60 bool UseNEONForSinglePrecisionFP; 61 62 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 63 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 64 bool SlowFPVMLx; 65 66 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 67 /// forwarding to allow mul + mla being issued back to back. 68 bool HasVMLxForwarding; 69 70 /// SlowFPBrcc - True if floating point compare + branch is slow. 71 bool SlowFPBrcc; 72 73 /// IsThumb - True if we are in thumb mode, false if in ARM mode. 74 bool IsThumb; 75 76 /// ThumbMode - Indicates supported Thumb version. 77 ThumbTypeEnum ThumbMode; 78 79 /// NoARM - True if subtarget does not support ARM mode execution. 80 bool NoARM; 81 82 /// PostRAScheduler - True if using post-register-allocation scheduler. 83 bool PostRAScheduler; 84 85 /// IsR9Reserved - True if R9 is a not available as general purpose register. 86 bool IsR9Reserved; 87 88 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 89 /// imms (including global addresses). 90 bool UseMovt; 91 92 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 93 /// only so far) 94 bool HasFP16; 95 96 /// HasD16 - True if subtarget is limited to 16 double precision 97 /// FP registers for VFPv3. 98 bool HasD16; 99 100 /// HasHardwareDivide - True if subtarget supports [su]div 101 bool HasHardwareDivide; 102 103 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 104 /// instructions. 105 bool HasT2ExtractPack; 106 107 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 108 /// instructions. 109 bool HasDataBarrier; 110 111 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 112 /// over 16-bit ones. 113 bool Pref32BitThumb; 114 115 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 116 /// that partially update CPSR and add false dependency on the previous 117 /// CPSR setting instruction. 118 bool AvoidCPSRPartialUpdate; 119 120 /// HasMPExtension - True if the subtarget supports Multiprocessing 121 /// extension (ARMv7 only). 122 bool HasMPExtension; 123 124 /// FPOnlySP - If true, the floating point unit only supports single 125 /// precision. 126 bool FPOnlySP; 127 128 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 129 /// accesses for some types. For details, see 130 /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). 131 bool AllowsUnalignedMem; 132 133 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith 134 /// and such) instructions in Thumb2 code. 135 bool Thumb2DSP; 136 137 /// stackAlignment - The minimum alignment known to hold of the stack frame on 138 /// entry to the function and which must be maintained by every function. 139 unsigned stackAlignment; 140 141 /// CPUString - String name of used CPU. 142 std::string CPUString; 143 144 /// TargetTriple - What processor and OS we're targeting. 145 Triple TargetTriple; 146 147 /// Selected instruction itineraries (one entry per itinerary class.) 148 InstrItineraryData InstrItins; 149 150 public: 151 enum { 152 isELF, isDarwin 153 } TargetType; 154 155 enum { 156 ARM_ABI_APCS, 157 ARM_ABI_AAPCS // ARM EABI 158 } TargetABI; 159 160 /// This constructor initializes the data members to match that 161 /// of the specified triple. 162 /// 163 ARMSubtarget(const std::string &TT, const std::string &CPU, 164 const std::string &FS, bool isThumb); 165 166 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 167 /// that still makes it profitable to inline the call. 168 unsigned getMaxInlineSizeThreshold() const { 169 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 170 // Change this once Thumb1 ldmia / stmia support is added. 171 return isThumb1Only() ? 0 : 64; 172 } 173 /// ParseSubtargetFeatures - Parses features string setting specified 174 /// subtarget options. Definition of function is auto generated by tblgen. 175 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); 176 177 void computeIssueWidth(); 178 179 bool hasV4TOps() const { return ARMArchVersion >= V4T; } 180 bool hasV5TOps() const { return ARMArchVersion >= V5T; } 181 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } 182 bool hasV6Ops() const { return ARMArchVersion >= V6; } 183 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } 184 bool hasV7Ops() const { return ARMArchVersion >= V7A; } 185 186 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 187 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 188 189 bool hasARMOps() const { return !NoARM; } 190 191 bool hasVFP2() const { return ARMFPUType >= VFPv2; } 192 bool hasVFP3() const { return ARMFPUType >= VFPv3; } 193 bool hasNEON() const { return ARMFPUType >= NEON; } 194 bool useNEONForSinglePrecisionFP() const { 195 return hasNEON() && UseNEONForSinglePrecisionFP; } 196 bool hasDivide() const { return HasHardwareDivide; } 197 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 198 bool hasDataBarrier() const { return HasDataBarrier; } 199 bool useFPVMLx() const { return !SlowFPVMLx; } 200 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 201 bool isFPBrccSlow() const { return SlowFPBrcc; } 202 bool isFPOnlySP() const { return FPOnlySP; } 203 bool prefers32BitThumb() const { return Pref32BitThumb; } 204 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 205 bool hasMPExtension() const { return HasMPExtension; } 206 bool hasThumb2DSP() const { return Thumb2DSP; } 207 208 bool hasFP16() const { return HasFP16; } 209 bool hasD16() const { return HasD16; } 210 211 const Triple &getTargetTriple() const { return TargetTriple; } 212 213 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 214 bool isTargetELF() const { return !isTargetDarwin(); } 215 216 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 217 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 218 219 bool isThumb() const { return IsThumb; } 220 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } 221 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } 222 bool hasThumb2() const { return ThumbMode >= Thumb2; } 223 224 bool isR9Reserved() const { return IsR9Reserved; } 225 226 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 227 228 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 229 230 const std::string & getCPUString() const { return CPUString; } 231 232 unsigned getMispredictionPenalty() const; 233 234 /// enablePostRAScheduler - True at 'More' optimization. 235 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 236 TargetSubtargetInfo::AntiDepBreakMode& Mode, 237 RegClassVector& CriticalPathRCs) const; 238 239 /// getInstrItins - Return the instruction itineraies based on subtarget 240 /// selection. 241 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 242 243 /// getStackAlignment - Returns the minimum alignment known to hold of the 244 /// stack frame on entry to the function and which must be maintained by every 245 /// function for this subtarget. 246 unsigned getStackAlignment() const { return stackAlignment; } 247 248 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 249 /// symbol. 250 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 251}; 252} // End llvm namespace 253 254#endif // ARMSUBTARGET_H 255