ARMSubtarget.h revision 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 
1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "MCTargetDesc/ARMMCTargetDesc.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/MC/MCInstrItineraries.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23#define GET_SUBTARGETINFO_HEADER
24#include "ARMGenSubtargetInfo.inc"
25
26namespace llvm {
27class GlobalValue;
28class StringRef;
29
30class ARMSubtarget : public ARMGenSubtargetInfo {
31protected:
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37  ARMProcFamilyEnum ARMProcFamily;
38
39  /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40  /// Specify whether target support specific ARM ISA variants.
41  bool HasV4TOps;
42  bool HasV5TOps;
43  bool HasV5TEOps;
44  bool HasV6Ops;
45  bool HasV6T2Ops;
46  bool HasV7Ops;
47
48  /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON, HasNEONVFPv4 - Specify what
49  /// floating point ISAs are supported.
50  bool HasVFPv2;
51  bool HasVFPv3;
52  bool HasVFPv4;
53  bool HasNEON;
54  bool HasNEONVFPv4;
55
56  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
57  /// specified. Use the method useNEONForSinglePrecisionFP() to
58  /// determine if NEON should actually be used.
59  bool UseNEONForSinglePrecisionFP;
60
61  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
62  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
63  bool SlowFPVMLx;
64
65  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
66  /// forwarding to allow mul + mla being issued back to back.
67  bool HasVMLxForwarding;
68
69  /// SlowFPBrcc - True if floating point compare + branch is slow.
70  bool SlowFPBrcc;
71
72  /// InThumbMode - True if compiling for Thumb, false for ARM.
73  bool InThumbMode;
74
75  /// HasThumb2 - True if Thumb2 instructions are supported.
76  bool HasThumb2;
77
78  /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
79  /// v6m, v7m for example.
80  bool IsMClass;
81
82  /// NoARM - True if subtarget does not support ARM mode execution.
83  bool NoARM;
84
85  /// PostRAScheduler - True if using post-register-allocation scheduler.
86  bool PostRAScheduler;
87
88  /// IsR9Reserved - True if R9 is a not available as general purpose register.
89  bool IsR9Reserved;
90
91  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
92  /// imms (including global addresses).
93  bool UseMovt;
94
95  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
96  /// must be able to synthesize call stubs for interworking between ARM and
97  /// Thumb.
98  bool SupportsTailCall;
99
100  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
101  /// only so far)
102  bool HasFP16;
103
104  /// HasD16 - True if subtarget is limited to 16 double precision
105  /// FP registers for VFPv3.
106  bool HasD16;
107
108  /// HasHardwareDivide - True if subtarget supports [su]div
109  bool HasHardwareDivide;
110
111  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
112  /// instructions.
113  bool HasT2ExtractPack;
114
115  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
116  /// instructions.
117  bool HasDataBarrier;
118
119  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
120  /// over 16-bit ones.
121  bool Pref32BitThumb;
122
123  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
124  /// that partially update CPSR and add false dependency on the previous
125  /// CPSR setting instruction.
126  bool AvoidCPSRPartialUpdate;
127
128  /// HasRAS - Some processors perform return stack prediction. CodeGen should
129  /// avoid issue "normal" call instructions to callees which do not return.
130  bool HasRAS;
131
132  /// HasMPExtension - True if the subtarget supports Multiprocessing
133  /// extension (ARMv7 only).
134  bool HasMPExtension;
135
136  /// FPOnlySP - If true, the floating point unit only supports single
137  /// precision.
138  bool FPOnlySP;
139
140  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
141  /// accesses for some types.  For details, see
142  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
143  bool AllowsUnalignedMem;
144
145  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
146  /// and such) instructions in Thumb2 code.
147  bool Thumb2DSP;
148
149  /// stackAlignment - The minimum alignment known to hold of the stack frame on
150  /// entry to the function and which must be maintained by every function.
151  unsigned stackAlignment;
152
153  /// CPUString - String name of used CPU.
154  std::string CPUString;
155
156  /// TargetTriple - What processor and OS we're targeting.
157  Triple TargetTriple;
158
159  /// Selected instruction itineraries (one entry per itinerary class.)
160  InstrItineraryData InstrItins;
161
162 public:
163  enum {
164    isELF, isDarwin
165  } TargetType;
166
167  enum {
168    ARM_ABI_APCS,
169    ARM_ABI_AAPCS // ARM EABI
170  } TargetABI;
171
172  /// This constructor initializes the data members to match that
173  /// of the specified triple.
174  ///
175  ARMSubtarget(const std::string &TT, const std::string &CPU,
176               const std::string &FS);
177
178  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
179  /// that still makes it profitable to inline the call.
180  unsigned getMaxInlineSizeThreshold() const {
181    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
182    // Change this once Thumb1 ldmia / stmia support is added.
183    return isThumb1Only() ? 0 : 64;
184  }
185  /// ParseSubtargetFeatures - Parses features string setting specified
186  /// subtarget options.  Definition of function is auto generated by tblgen.
187  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
188
189  void computeIssueWidth();
190
191  bool hasV4TOps()  const { return HasV4TOps;  }
192  bool hasV5TOps()  const { return HasV5TOps;  }
193  bool hasV5TEOps() const { return HasV5TEOps; }
194  bool hasV6Ops()   const { return HasV6Ops;   }
195  bool hasV6T2Ops() const { return HasV6T2Ops; }
196  bool hasV7Ops()   const { return HasV7Ops;  }
197
198  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
199  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
200  bool isCortexM3() const { return CPUString == "cortex-m3"; }
201
202  bool hasARMOps() const { return !NoARM; }
203
204  bool hasVFP2() const { return HasVFPv2; }
205  bool hasVFP3() const { return HasVFPv3; }
206  bool hasVFP4() const { return HasVFPv4; }
207  bool hasNEON() const { return HasNEON;  }
208  bool hasNEONVFP4() const { return HasNEONVFPv4;  }
209  bool useNEONForSinglePrecisionFP() const {
210    return hasNEON() && UseNEONForSinglePrecisionFP; }
211
212  bool hasDivide() const { return HasHardwareDivide; }
213  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
214  bool hasDataBarrier() const { return HasDataBarrier; }
215  bool useFPVMLx() const { return !SlowFPVMLx; }
216  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
217  bool isFPBrccSlow() const { return SlowFPBrcc; }
218  bool isFPOnlySP() const { return FPOnlySP; }
219  bool prefers32BitThumb() const { return Pref32BitThumb; }
220  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
221  bool hasRAS() const { return HasRAS; }
222  bool hasMPExtension() const { return HasMPExtension; }
223  bool hasThumb2DSP() const { return Thumb2DSP; }
224
225  bool hasFP16() const { return HasFP16; }
226  bool hasD16() const { return HasD16; }
227
228  const Triple &getTargetTriple() const { return TargetTriple; }
229
230  bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
231  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
232  bool isTargetNaCl() const {
233    return TargetTriple.getOS() == Triple::NativeClient;
234  }
235  bool isTargetELF() const { return !isTargetDarwin(); }
236
237  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
238  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
239
240  bool isThumb() const { return InThumbMode; }
241  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
242  bool isThumb2() const { return InThumbMode && HasThumb2; }
243  bool hasThumb2() const { return HasThumb2; }
244  bool isMClass() const { return IsMClass; }
245  bool isARClass() const { return !IsMClass; }
246
247  bool isR9Reserved() const { return IsR9Reserved; }
248
249  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
250  bool supportsTailCall() const { return SupportsTailCall; }
251
252  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
253
254  const std::string & getCPUString() const { return CPUString; }
255
256  unsigned getMispredictionPenalty() const;
257
258  /// enablePostRAScheduler - True at 'More' optimization.
259  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
260                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
261                             RegClassVector& CriticalPathRCs) const;
262
263  /// getInstrItins - Return the instruction itineraies based on subtarget
264  /// selection.
265  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
266
267  /// getStackAlignment - Returns the minimum alignment known to hold of the
268  /// stack frame on entry to the function and which must be maintained by every
269  /// function for this subtarget.
270  unsigned getStackAlignment() const { return stackAlignment; }
271
272  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
273  /// symbol.
274  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
275};
276} // End llvm namespace
277
278#endif  // ARMSUBTARGET_H
279