ARMSubtarget.h revision 4761a8d6549125e21d84371a9783bd41de2f55fa 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "MCTargetDesc/ARMMCTargetDesc.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/MC/MCInstrItineraries.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23#define GET_SUBTARGETINFO_HEADER
24#include "ARMGenSubtargetInfo.inc"
25
26namespace llvm {
27class GlobalValue;
28class StringRef;
29
30class ARMSubtarget : public ARMGenSubtargetInfo {
31protected:
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37  ARMProcFamilyEnum ARMProcFamily;
38
39  /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40  /// Specify whether target support specific ARM ISA variants.
41  bool HasV4TOps;
42  bool HasV5TOps;
43  bool HasV5TEOps;
44  bool HasV6Ops;
45  bool HasV6T2Ops;
46  bool HasV7Ops;
47
48  /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
49  /// supported.
50  bool HasVFPv2;
51  bool HasVFPv3;
52  bool HasNEON;
53
54  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
55  /// specified. Use the method useNEONForSinglePrecisionFP() to
56  /// determine if NEON should actually be used.
57  bool UseNEONForSinglePrecisionFP;
58
59  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
60  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
61  bool SlowFPVMLx;
62
63  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
64  /// forwarding to allow mul + mla being issued back to back.
65  bool HasVMLxForwarding;
66
67  /// SlowFPBrcc - True if floating point compare + branch is slow.
68  bool SlowFPBrcc;
69
70  /// InThumbMode - True if compiling for Thumb, false for ARM.
71  bool InThumbMode;
72
73  /// HasThumb2 - True if Thumb2 instructions are supported.
74  bool HasThumb2;
75
76  /// NoARM - True if subtarget does not support ARM mode execution.
77  bool NoARM;
78
79  /// PostRAScheduler - True if using post-register-allocation scheduler.
80  bool PostRAScheduler;
81
82  /// IsR9Reserved - True if R9 is a not available as general purpose register.
83  bool IsR9Reserved;
84
85  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
86  /// imms (including global addresses).
87  bool UseMovt;
88
89  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
90  /// only so far)
91  bool HasFP16;
92
93  /// HasD16 - True if subtarget is limited to 16 double precision
94  /// FP registers for VFPv3.
95  bool HasD16;
96
97  /// HasHardwareDivide - True if subtarget supports [su]div
98  bool HasHardwareDivide;
99
100  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
101  /// instructions.
102  bool HasT2ExtractPack;
103
104  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
105  /// instructions.
106  bool HasDataBarrier;
107
108  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
109  /// over 16-bit ones.
110  bool Pref32BitThumb;
111
112  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
113  /// that partially update CPSR and add false dependency on the previous
114  /// CPSR setting instruction.
115  bool AvoidCPSRPartialUpdate;
116
117  /// HasMPExtension - True if the subtarget supports Multiprocessing
118  /// extension (ARMv7 only).
119  bool HasMPExtension;
120
121  /// FPOnlySP - If true, the floating point unit only supports single
122  /// precision.
123  bool FPOnlySP;
124
125  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
126  /// accesses for some types.  For details, see
127  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
128  bool AllowsUnalignedMem;
129
130  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
131  /// and such) instructions in Thumb2 code.
132  bool Thumb2DSP;
133
134  /// stackAlignment - The minimum alignment known to hold of the stack frame on
135  /// entry to the function and which must be maintained by every function.
136  unsigned stackAlignment;
137
138  /// CPUString - String name of used CPU.
139  std::string CPUString;
140
141  /// TargetTriple - What processor and OS we're targeting.
142  Triple TargetTriple;
143
144  /// Selected instruction itineraries (one entry per itinerary class.)
145  InstrItineraryData InstrItins;
146
147 public:
148  enum {
149    isELF, isDarwin
150  } TargetType;
151
152  enum {
153    ARM_ABI_APCS,
154    ARM_ABI_AAPCS // ARM EABI
155  } TargetABI;
156
157  /// This constructor initializes the data members to match that
158  /// of the specified triple.
159  ///
160  ARMSubtarget(const std::string &TT, const std::string &CPU,
161               const std::string &FS);
162
163  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
164  /// that still makes it profitable to inline the call.
165  unsigned getMaxInlineSizeThreshold() const {
166    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
167    // Change this once Thumb1 ldmia / stmia support is added.
168    return isThumb1Only() ? 0 : 64;
169  }
170  /// ParseSubtargetFeatures - Parses features string setting specified
171  /// subtarget options.  Definition of function is auto generated by tblgen.
172  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
173
174  void computeIssueWidth();
175
176  bool hasV4TOps()  const { return HasV4TOps;  }
177  bool hasV5TOps()  const { return HasV5TOps;  }
178  bool hasV5TEOps() const { return HasV5TEOps; }
179  bool hasV6Ops()   const { return HasV6Ops;   }
180  bool hasV6T2Ops() const { return HasV6T2Ops; }
181  bool hasV7Ops()   const { return HasV7Ops;  }
182
183  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
184  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
185
186  bool hasARMOps() const { return !NoARM; }
187
188  bool hasVFP2() const { return HasVFPv2; }
189  bool hasVFP3() const { return HasVFPv3; }
190  bool hasNEON() const { return HasNEON;  }
191  bool useNEONForSinglePrecisionFP() const {
192    return hasNEON() && UseNEONForSinglePrecisionFP; }
193
194  bool hasDivide() const { return HasHardwareDivide; }
195  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
196  bool hasDataBarrier() const { return HasDataBarrier; }
197  bool useFPVMLx() const { return !SlowFPVMLx; }
198  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
199  bool isFPBrccSlow() const { return SlowFPBrcc; }
200  bool isFPOnlySP() const { return FPOnlySP; }
201  bool prefers32BitThumb() const { return Pref32BitThumb; }
202  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
203  bool hasMPExtension() const { return HasMPExtension; }
204  bool hasThumb2DSP() const { return Thumb2DSP; }
205
206  bool hasFP16() const { return HasFP16; }
207  bool hasD16() const { return HasD16; }
208
209  const Triple &getTargetTriple() const { return TargetTriple; }
210
211  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
212  bool isTargetELF() const { return !isTargetDarwin(); }
213
214  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
215  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
216
217  bool isThumb() const { return InThumbMode; }
218  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
219  bool isThumb2() const { return InThumbMode && HasThumb2; }
220  bool hasThumb2() const { return HasThumb2; }
221
222  bool isR9Reserved() const { return IsR9Reserved; }
223
224  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
225
226  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
227
228  const std::string & getCPUString() const { return CPUString; }
229
230  unsigned getMispredictionPenalty() const;
231
232  /// enablePostRAScheduler - True at 'More' optimization.
233  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
234                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
235                             RegClassVector& CriticalPathRCs) const;
236
237  /// getInstrItins - Return the instruction itineraies based on subtarget
238  /// selection.
239  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
240
241  /// getStackAlignment - Returns the minimum alignment known to hold of the
242  /// stack frame on entry to the function and which must be maintained by every
243  /// function for this subtarget.
244  unsigned getStackAlignment() const { return stackAlignment; }
245
246  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
247  /// symbol.
248  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
249};
250} // End llvm namespace
251
252#endif  // ARMSUBTARGET_H
253