ARMSubtarget.h revision 3b9569e70db0b5a0d1389384a07fecbea8dc7dc2 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
30  };
31
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  enum ARMFPEnum {
37    None, VFPv2, VFPv3, NEON
38  };
39
40  enum ThumbTypeEnum {
41    Thumb1,
42    Thumb2
43  };
44
45  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46  /// V6, V6T2, V7A, V7M.
47  ARMArchEnum ARMArchVersion;
48
49  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50  ARMProcFamilyEnum ARMProcFamily;
51
52  /// ARMFPUType - Floating Point Unit type.
53  ARMFPEnum ARMFPUType;
54
55  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56  /// specified. Use the method useNEONForSinglePrecisionFP() to
57  /// determine if NEON should actually be used.
58  bool UseNEONForSinglePrecisionFP;
59
60  /// SlowVMLx - If the VFP2 instructions are available, indicates whether
61  /// the VML[AS] instructions are slow (if so, don't use them).
62  bool SlowVMLx;
63
64  /// SlowFPBrcc - True if floating point compare + branch is slow.
65  bool SlowFPBrcc;
66
67  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
68  bool IsThumb;
69
70  /// ThumbMode - Indicates supported Thumb version.
71  ThumbTypeEnum ThumbMode;
72
73  /// NoARM - True if subtarget does not support ARM mode execution.
74  bool NoARM;
75
76  /// PostRAScheduler - True if using post-register-allocation scheduler.
77  bool PostRAScheduler;
78
79  /// IsR9Reserved - True if R9 is a not available as general purpose register.
80  bool IsR9Reserved;
81
82  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
83  /// imms (including global addresses).
84  bool UseMovt;
85
86  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
87  /// only so far)
88  bool HasFP16;
89
90  /// HasHardwareDivide - True if subtarget supports [su]div
91  bool HasHardwareDivide;
92
93  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
94  /// instructions.
95  bool HasT2ExtractPack;
96
97  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
98  /// instructions.
99  bool HasDataBarrier;
100
101  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
102  /// over 16-bit ones.
103  bool Pref32BitThumb;
104
105  /// FPOnlySP - If true, the floating point unit only supports single
106  /// precision.
107  bool FPOnlySP;
108
109  /// stackAlignment - The minimum alignment known to hold of the stack frame on
110  /// entry to the function and which must be maintained by every function.
111  unsigned stackAlignment;
112
113  /// CPUString - String name of used CPU.
114  std::string CPUString;
115
116  /// Selected instruction itineraries (one entry per itinerary class.)
117  InstrItineraryData InstrItins;
118
119 public:
120  enum {
121    isELF, isDarwin
122  } TargetType;
123
124  enum {
125    ARM_ABI_APCS,
126    ARM_ABI_AAPCS // ARM EABI
127  } TargetABI;
128
129  /// This constructor initializes the data members to match that
130  /// of the specified triple.
131  ///
132  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
133
134  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
135  /// that still makes it profitable to inline the call.
136  unsigned getMaxInlineSizeThreshold() const {
137    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
138    // Change this once Thumb1 ldmia / stmia support is added.
139    return isThumb1Only() ? 0 : 64;
140  }
141  /// ParseSubtargetFeatures - Parses features string setting specified
142  /// subtarget options.  Definition of function is auto generated by tblgen.
143  std::string ParseSubtargetFeatures(const std::string &FS,
144                                     const std::string &CPU);
145
146  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
147  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
148  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
149  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
150  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
151  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
152
153  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
154  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
155
156  bool hasARMOps() const { return !NoARM; }
157
158  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
159  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
160  bool hasNEON() const { return ARMFPUType >= NEON;  }
161  bool useNEONForSinglePrecisionFP() const {
162    return hasNEON() && UseNEONForSinglePrecisionFP; }
163  bool hasDivide() const { return HasHardwareDivide; }
164  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
165  bool hasDataBarrier() const { return HasDataBarrier; }
166  bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
167  bool isFPBrccSlow() const { return SlowFPBrcc; }
168  bool isFPOnlySP() const { return FPOnlySP; }
169  bool prefers32BitThumb() const { return Pref32BitThumb; }
170
171  bool hasFP16() const { return HasFP16; }
172
173  bool isTargetDarwin() const { return TargetType == isDarwin; }
174  bool isTargetELF() const { return TargetType == isELF; }
175
176  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
177  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
178
179  bool isThumb() const { return IsThumb; }
180  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
181  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
182  bool hasThumb2() const { return ThumbMode >= Thumb2; }
183
184  bool isR9Reserved() const { return IsR9Reserved; }
185
186  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
187
188  const std::string & getCPUString() const { return CPUString; }
189
190  /// enablePostRAScheduler - True at 'More' optimization.
191  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
192                             TargetSubtarget::AntiDepBreakMode& Mode,
193                             RegClassVector& CriticalPathRCs) const;
194
195  /// getInstrItins - Return the instruction itineraies based on subtarget
196  /// selection.
197  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
198
199  /// getStackAlignment - Returns the minimum alignment known to hold of the
200  /// stack frame on entry to the function and which must be maintained by every
201  /// function for this subtarget.
202  unsigned getStackAlignment() const { return stackAlignment; }
203
204  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
205  /// symbol.
206  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
207
208  /// getDataLayout() - returns the ARM/Thumb specific TargetLayout string
209  std::string getDataLayout() const {
210    if (isThumb()) {
211      if (isAPCS_ABI()) {
212        return std::string("e-p:32:32-f64:32:32-i64:32:32-"
213                           "i16:16:32-i8:8:32-i1:8:32-"
214                           "v128:32:128-v64:32:64-a:0:32-n32");
215      } else {
216        return std::string("e-p:32:32-f64:64:64-i64:64:64-"
217                           "i16:16:32-i8:8:32-i1:8:32-"
218                           "v128:64:128-v64:64:64-a:0:32-n32");
219      }
220    } else {
221      if (isAPCS_ABI()) {
222        return std::string("e-p:32:32-f64:32:32-i64:32:32-"
223                           "v128:32:128-v64:32:64-n32");
224      } else {
225        return std::string("e-p:32:32-f64:64:64-i64:64:64-"
226                           "v128:64:128-v64:64:64-n32");
227      }
228    }
229  }
230};
231} // End llvm namespace
232
233#endif  // ARMSUBTARGET_H
234