ARMSubtarget.h revision 46510a73e977273ec67747eb34cbdb43f815e451 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6T2, V7A
30  };
31
32  enum ARMFPEnum {
33    None, VFPv2, VFPv3, NEON
34  };
35
36  enum ThumbTypeEnum {
37    Thumb1,
38    Thumb2
39  };
40
41  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
42  /// V6, V6T2, V7A.
43  ARMArchEnum ARMArchVersion;
44
45  /// ARMFPUType - Floating Point Unit type.
46  ARMFPEnum ARMFPUType;
47
48  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49  /// specified. Use the method useNEONForSinglePrecisionFP() to
50  /// determine if NEON should actually be used.
51  bool UseNEONForSinglePrecisionFP;
52
53  /// SlowVMLx - If the VFP2 instructions are available, indicates whether
54  /// the VML[AS] instructions are slow (if so, don't use them).
55  bool SlowVMLx;
56
57  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
58  bool IsThumb;
59
60  /// ThumbMode - Indicates supported Thumb version.
61  ThumbTypeEnum ThumbMode;
62
63  /// PostRAScheduler - True if using post-register-allocation scheduler.
64  bool PostRAScheduler;
65
66  /// IsR9Reserved - True if R9 is a not available as general purpose register.
67  bool IsR9Reserved;
68
69  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
70  /// imms (including global addresses).
71  bool UseMovt;
72
73  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
74  /// only so far)
75  bool HasFP16;
76
77  /// stackAlignment - The minimum alignment known to hold of the stack frame on
78  /// entry to the function and which must be maintained by every function.
79  unsigned stackAlignment;
80
81  /// CPUString - String name of used CPU.
82  std::string CPUString;
83
84  /// Selected instruction itineraries (one entry per itinerary class.)
85  InstrItineraryData InstrItins;
86
87 public:
88  enum {
89    isELF, isDarwin
90  } TargetType;
91
92  enum {
93    ARM_ABI_APCS,
94    ARM_ABI_AAPCS // ARM EABI
95  } TargetABI;
96
97  /// This constructor initializes the data members to match that
98  /// of the specified triple.
99  ///
100  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
101
102  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
103  /// that still makes it profitable to inline the call.
104  unsigned getMaxInlineSizeThreshold() const {
105    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
106    // Change this once Thumb1 ldmia / stmia support is added.
107    return isThumb1Only() ? 0 : 64;
108  }
109  /// ParseSubtargetFeatures - Parses features string setting specified
110  /// subtarget options.  Definition of function is auto generated by tblgen.
111  std::string ParseSubtargetFeatures(const std::string &FS,
112                                     const std::string &CPU);
113
114  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
115  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
116  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
117  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
118  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
119  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
120
121  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
122  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
123  bool hasNEON() const { return ARMFPUType >= NEON;  }
124  bool useNEONForSinglePrecisionFP() const {
125    return hasNEON() && UseNEONForSinglePrecisionFP; }
126  bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
127
128  bool hasFP16() const { return HasFP16; }
129
130  bool isTargetDarwin() const { return TargetType == isDarwin; }
131  bool isTargetELF() const { return TargetType == isELF; }
132
133  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
134  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
135
136  bool isThumb() const { return IsThumb; }
137  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
138  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
139  bool hasThumb2() const { return ThumbMode >= Thumb2; }
140
141  bool isR9Reserved() const { return IsR9Reserved; }
142
143  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
144
145  const std::string & getCPUString() const { return CPUString; }
146
147  /// enablePostRAScheduler - True at 'More' optimization.
148  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
149                             TargetSubtarget::AntiDepBreakMode& Mode,
150                             RegClassVector& CriticalPathRCs) const;
151
152  /// getInstrItins - Return the instruction itineraies based on subtarget
153  /// selection.
154  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
155
156  /// getStackAlignment - Returns the minimum alignment known to hold of the
157  /// stack frame on entry to the function and which must be maintained by every
158  /// function for this subtarget.
159  unsigned getStackAlignment() const { return stackAlignment; }
160
161  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
162  /// symbol.
163  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
164};
165} // End llvm namespace
166
167#endif  // ARMSUBTARGET_H
168