1fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// 2fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// 3fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// The LLVM Compiler Infrastructure 4fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// 5fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// This file is distributed under the University of Illinois Open Source 6fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// License. See LICENSE.TXT for details. 7fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// 8fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner//===----------------------------------------------------------------------===// 9fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// 10fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// This class prints an ARM MCInst to a .s file. 11fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner// 12fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner//===----------------------------------------------------------------------===// 13fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner 14fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner#define DEBUG_TYPE "asm-printer" 15fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner#include "ARMInstPrinter.h" 16be74029f44c32efc09274a16cbff588ad10dc5eaEvan Cheng#include "MCTargetDesc/ARMBaseInfo.h" 17ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 18fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner#include "llvm/MC/MCInst.h" 1961d35c273e2196c87986829fdadccc7e301fc7a8Chris Lattner#include "llvm/MC/MCAsmInfo.h" 206f99776f6c1d6cc93a62192099a0fd8cc2cc3a0cChris Lattner#include "llvm/MC/MCExpr.h" 217c0b3c1fb6395475e262d66ee403645f0c67dee2Craig Topper#include "llvm/MC/MCInstrInfo.h" 2228f08c93e75d291695ea89b9004145103292e85bJim Grosbach#include "llvm/MC/MCRegisterInfo.h" 236f99776f6c1d6cc93a62192099a0fd8cc2cc3a0cChris Lattner#include "llvm/Support/raw_ostream.h" 24fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattnerusing namespace llvm; 25fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner 26fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner#include "ARMGenAsmWriter.inc" 27fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner 283dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. 293dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson/// 3001208d56e8341c17bb7dbeaf6c081fdffe523786Jim Grosbach/// getSORegOffset returns an integer from 0-31, representing '32' as 0. 313dac0bec7e7874ffb378385b6160bd2117184ca9Owen Andersonstatic unsigned translateShiftImm(unsigned imm) { 323dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson if (imm == 0) 333dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson return 32; 343dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson return imm; 353dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson} 363dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson 37b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy 38b950585cc5a0d665e9accfe5ce490cd269756f2eJames MolloyARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, 3917463b3ef1a3d39b10619254f12e806c8c43f9e7Craig Topper const MCInstrInfo &MII, 40c6449b636f4984be88f128d0375c056ad05e7e8fJim Grosbach const MCRegisterInfo &MRI, 41b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy const MCSubtargetInfo &STI) : 4217463b3ef1a3d39b10619254f12e806c8c43f9e7Craig Topper MCInstPrinter(MAI, MII, MRI) { 43b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy // Initialize the set of available features. 44b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy setAvailableFeatures(STI.getFeatureBits()); 45b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy} 46b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy 47cde4ce411b1ace4a80ea1dd38df97e8508aed0c9Rafael Espindolavoid ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 48cde4ce411b1ace4a80ea1dd38df97e8508aed0c9Rafael Espindola OS << getRegisterName(RegNo); 4957caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov} 506274ec48b3a3e1fbaf3a359868d53a76f20a4245Chris Lattner 5198c5ddabca1debf935a07d14d0cbc9732374bdb8Owen Andersonvoid ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 5298c5ddabca1debf935a07d14d0cbc9732374bdb8Owen Anderson StringRef Annot) { 5304863d06fb3f2972355c990b29edcab1d9a85b41Bill Wendling unsigned Opcode = MI->getOpcode(); 5404863d06fb3f2972355c990b29edcab1d9a85b41Bill Wendling 557e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach // Check for HINT instructions w/ canonical names. 567e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) { 577e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach switch (MI->getOperand(0).getImm()) { 587e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach case 0: O << "\tnop"; break; 597e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach case 1: O << "\tyield"; break; 607e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach case 2: O << "\twfe"; break; 617e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach case 3: O << "\twfi"; break; 627e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach case 4: O << "\tsev"; break; 637e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach default: 647e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach // Anything else should just print normally. 657e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach printInstruction(MI, O); 667e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach printAnnotation(O, Annot); 677e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach return; 687e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach } 697e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach printPredicateOperand(MI, 1, O); 707e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach if (Opcode == ARM::t2HINT) 717e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach O << ".w"; 727e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach printAnnotation(O, Annot); 737e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach return; 747e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach } 757e99a60857532ca2973cf9dabc790d84a2e15a8aJim Grosbach 769e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Check for MOVs and print canonical forms, instead. 77152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson if (Opcode == ARM::MOVsr) { 78e6be85e9ff6bd28c599421a120a8491257c13ebdJim Grosbach // FIXME: Thumb variants? 799e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &Dst = MI->getOperand(0); 809e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(1); 819e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(2); 829e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO3 = MI->getOperand(3); 839e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 849e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 8535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner printSBitModifierOperand(MI, 6, O); 8635c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner printPredicateOperand(MI, 4, O); 879e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 889e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << '\t' << getRegisterName(Dst.getReg()) 899e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ", " << getRegisterName(MO1.getReg()); 909e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 91152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << ", " << getRegisterName(MO2.getReg()); 92152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 93519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 94152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return; 95152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson } 969e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 97152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson if (Opcode == ARM::MOVsi) { 98152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // FIXME: Thumb variants? 99152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &Dst = MI->getOperand(0); 100152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO1 = MI->getOperand(1); 101152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO2 = MI->getOperand(2); 1029e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 103152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 104152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson printSBitModifierOperand(MI, 5, O); 105152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson printPredicateOperand(MI, 3, O); 106152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 107152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << '\t' << getRegisterName(Dst.getReg()) 108152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson << ", " << getRegisterName(MO1.getReg()); 109152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 110ede042dc8d59ff48a48ef8e2271f2a7ee8324ba5Owen Anderson if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 111519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 112152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return; 113ede042dc8d59ff48a48ef8e2271f2a7ee8324ba5Owen Anderson } 114152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1153dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 116519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 1179e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen return; 1189e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 1199e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 120152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 1219e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // A8.6.123 PUSH 12273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) && 12381550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson MI->getOperand(0).getReg() == ARM::SP && 12481550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson MI->getNumOperands() > 5) { 12581550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson // Should only print PUSH if there are at least two registers in the list. 12673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t' << "push"; 12773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printPredicateOperand(MI, 2, O); 12841ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1Jim Grosbach if (Opcode == ARM::t2STMDB_UPD) 12941ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1Jim Grosbach O << ".w"; 13073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t'; 13173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printRegisterList(MI, 4, O); 132519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 13373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling return; 1349e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 135f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && 136f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach MI->getOperand(3).getImm() == -4) { 137f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach O << '\t' << "push"; 138f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach printPredicateOperand(MI, 4, O); 139f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; 140519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 141f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach return; 142f6713916fb4504aab617f0e317689acd878cc37fJim Grosbach } 1439e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 1449e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // A8.6.122 POP 14573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) && 14681550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson MI->getOperand(0).getReg() == ARM::SP && 14781550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson MI->getNumOperands() > 5) { 14881550dc0a866e27a1efbc5de616fb366ebb547cdOwen Anderson // Should only print POP if there are at least two registers in the list. 14973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t' << "pop"; 15073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printPredicateOperand(MI, 2, O); 15141ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1Jim Grosbach if (Opcode == ARM::t2LDMIA_UPD) 15241ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1Jim Grosbach O << ".w"; 15373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t'; 15473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printRegisterList(MI, 4, O); 155519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 15673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling return; 1579e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 158f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && 159f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach MI->getOperand(4).getImm() == 4) { 160f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach O << '\t' << "pop"; 161f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach printPredicateOperand(MI, 5, O); 162f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}"; 163519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 164f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach return; 165f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach } 166f8fce711e8b756adca63044f7d122648c960ab96Jim Grosbach 1679e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 1689e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // A8.6.355 VPUSH 16973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) && 1709e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen MI->getOperand(0).getReg() == ARM::SP) { 17173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t' << "vpush"; 17273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printPredicateOperand(MI, 2, O); 17373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t'; 17473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printRegisterList(MI, 4, O); 175519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 17673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling return; 1779e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 1789e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 1799e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // A8.6.354 VPOP 18073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) && 1819e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen MI->getOperand(0).getReg() == ARM::SP) { 18273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t' << "vpop"; 18373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printPredicateOperand(MI, 2, O); 18473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling O << '\t'; 18573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling printRegisterList(MI, 4, O); 186519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 18773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling return; 1889e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 1899e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 190cefe4c9c483d8a50ff13f36881090ab44ec67f13Jim Grosbach if (Opcode == ARM::tLDMIA) { 191565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson bool Writeback = true; 192565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson unsigned BaseReg = MI->getOperand(0).getReg(); 193565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 194565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson if (MI->getOperand(i).getReg() == BaseReg) 195565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson Writeback = false; 196565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson } 197565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson 198cefe4c9c483d8a50ff13f36881090ab44ec67f13Jim Grosbach O << "\tldm"; 199565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson 200565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson printPredicateOperand(MI, 1, O); 201565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson O << '\t' << getRegisterName(BaseReg); 202565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson if (Writeback) O << "!"; 203565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson O << ", "; 204565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson printRegisterList(MI, 3, O); 205519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 206565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson return; 207565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson } 208565a0366974d82c3efe8a31e0ecc0609c67cad3eOwen Anderson 2090780b6303b99441fef04340b7a083006484f4743Jim Grosbach // Thumb1 NOP 2100780b6303b99441fef04340b7a083006484f4743Jim Grosbach if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && 2110780b6303b99441fef04340b7a083006484f4743Jim Grosbach MI->getOperand(1).getReg() == ARM::R8) { 2120780b6303b99441fef04340b7a083006484f4743Jim Grosbach O << "\tnop"; 213df9ce6bbc5b66c3c4d30c2f32b6f17c690cfa004Jim Grosbach printPredicateOperand(MI, 2, O); 214519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 2150780b6303b99441fef04340b7a083006484f4743Jim Grosbach return; 2160780b6303b99441fef04340b7a083006484f4743Jim Grosbach } 2170780b6303b99441fef04340b7a083006484f4743Jim Grosbach 21835c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner printInstruction(MI, O); 219519020adf1cf57e2e93cc4fd49c385c47f7ff0f7Owen Anderson printAnnotation(O, Annot); 22004863d06fb3f2972355c990b29edcab1d9a85b41Bill Wendling} 221fd60382e750c50ddb55485bf2cfcdf8dcbbcfd6bChris Lattner 2228bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattnervoid ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 2230a2287b909634991a8e8aa7a93f81f09375227b1Jim Grosbach raw_ostream &O) { 2248bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner const MCOperand &Op = MI->getOperand(OpNo); 2258bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner if (Op.isReg()) { 226bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner unsigned Reg = Op.getReg(); 22735636281c7ab6eb128b4ced6bf7ae0b6b8458dd2Jim Grosbach O << getRegisterName(Reg); 2288bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner } else if (Op.isImm()) { 2298bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner O << '#' << Op.getImm(); 2308bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner } else { 2318bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner assert(Op.isExpr() && "unknown operand kind in printOperand"); 2329e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby // If a symbolic branch target was added as a constant expression then print 2336c22695c6d10036f5635caec7ea84dbe84cc6beaKevin Enderby // that address in hex. And only print 32 unsigned bits for the address. 2349e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 2359e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby int64_t Address; 2369e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 2379e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby O << "0x"; 2386c22695c6d10036f5635caec7ea84dbe84cc6beaKevin Enderby O.write_hex((uint32_t)Address); 2399e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby } 2409e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby else { 2419e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby // Otherwise, just print the expression. 2429e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby O << *Op.getExpr(); 2439e5887b17e634b98f7c1cf0ee4f25c218097d08eKevin Enderby } 2448bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner } 2458bc86cba60fbb35fbfb52cc32b9e451e6b903a27Chris Lattner} 24661d35c273e2196c87986829fdadccc7e301fc7a8Chris Lattner 247e1368729700f1a51ee5cf33431df985e232bcc68Owen Andersonvoid ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, 248e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson raw_ostream &O) { 249e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson const MCOperand &MO1 = MI->getOperand(OpNum); 250e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson if (MO1.isExpr()) 251e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson O << *MO1.getExpr(); 252e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson else if (MO1.isImm()) 253e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson O << "[pc, #" << MO1.getImm() << "]"; 254e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson else 255e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson llvm_unreachable("Unknown LDR label operand?"); 256e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson} 257e1368729700f1a51ee5cf33431df985e232bcc68Owen Anderson 258017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner// so_reg is a 4-operand unit corresponding to register forms of the A5.1 259017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner// "Addressing Mode 1 - Data-processing operands" forms. This includes: 260017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner// REG 0 0 - e.g. R5 261017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner// REG REG 0,SH_OPC - e.g. R5, ROR R3 262017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 263152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Andersonvoid ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 26435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 265017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner const MCOperand &MO1 = MI->getOperand(OpNum); 266017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner const MCOperand &MO2 = MI->getOperand(OpNum+1); 267017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner const MCOperand &MO3 = MI->getOperand(OpNum+2); 26815d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 269017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner O << getRegisterName(MO1.getReg()); 27015d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 271017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner // Print the shift opc. 2721d9125a6ff192f1346d2b08bbf6ecc9c9e44103dBob Wilson ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 2731d9125a6ff192f1346d2b08bbf6ecc9c9e44103dBob Wilson O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 274e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach if (ShOpc == ARM_AM::rrx) 275e8606dc7c878d4562da5e3e5609b9d7d734d498cJim Grosbach return; 276293a5f69fad6053a328bf454e3f28d724d989231Jim Grosbach 277152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << ' ' << getRegisterName(MO2.getReg()); 278152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 279152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson} 280152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 281152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Andersonvoid ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 282152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson raw_ostream &O) { 283152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO1 = MI->getOperand(OpNum); 284152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson const MCOperand &MO2 = MI->getOperand(OpNum+1); 285152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 286152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << getRegisterName(MO1.getReg()); 287152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 288152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson // Print the shift opc. 289152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); 290152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 291152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson if (ShOpc == ARM_AM::rrx) 292152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return; 2933dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 294017d9478d52e56fd20db29eb40e0665cce9f094cChris Lattner} 295084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner 296152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 297ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes//===--------------------------------------------------------------------===// 298ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes// Addressing Mode #2 299ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes//===--------------------------------------------------------------------===// 300ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 301ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesvoid ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 302ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes raw_ostream &O) { 303084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner const MCOperand &MO1 = MI->getOperand(Op); 304084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner const MCOperand &MO2 = MI->getOperand(Op+1); 305084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner const MCOperand &MO3 = MI->getOperand(Op+2); 30615d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 307084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << "[" << getRegisterName(MO1.getReg()); 30815d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 309084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner if (!MO2.getReg()) { 3109e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0. 311084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << ", #" 3129e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 3139e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAM2Offset(MO3.getImm()); 314084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << "]"; 315084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner return; 316084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner } 31715d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 318084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << ", " 3199e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 3209e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << getRegisterName(MO2.getReg()); 32115d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 322084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) 323084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << ", " 324084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) 325084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner << " #" << ShImm; 326084f87d445620bd63573c0e8d9adf776dc62d87dChris Lattner O << "]"; 32715d78984d57378c3600ea26c37e1be05863644eaJim Grosbach} 328e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner 329ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesvoid ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op, 330ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes raw_ostream &O) { 331ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const MCOperand &MO1 = MI->getOperand(Op); 332ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const MCOperand &MO2 = MI->getOperand(Op+1); 333ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const MCOperand &MO3 = MI->getOperand(Op+2); 334ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 335ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes O << "[" << getRegisterName(MO1.getReg()) << "], "; 336ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 337ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes if (!MO2.getReg()) { 338ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm()); 339ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes O << '#' 340ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 341ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes << ImmOffs; 342ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return; 343ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 344ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 345ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 346ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes << getRegisterName(MO2.getReg()); 347ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 348ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) 349ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes O << ", " 350ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) 351ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes << " #" << ShImm; 352ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 353ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 3547f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbachvoid ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, 3557f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach raw_ostream &O) { 3567f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach const MCOperand &MO1 = MI->getOperand(Op); 3577f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach const MCOperand &MO2 = MI->getOperand(Op+1); 3587f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach O << "[" << getRegisterName(MO1.getReg()) << ", " 3597f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach << getRegisterName(MO2.getReg()) << "]"; 3607f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach} 3617f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 3627f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbachvoid ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, 3637f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach raw_ostream &O) { 3647f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach const MCOperand &MO1 = MI->getOperand(Op); 3657f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach const MCOperand &MO2 = MI->getOperand(Op+1); 3667f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach O << "[" << getRegisterName(MO1.getReg()) << ", " 3677f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach << getRegisterName(MO2.getReg()) << ", lsl #1]"; 3687f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach} 3697f739bee261debdf56bd89ac922b57eca53e91dcJim Grosbach 370ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopesvoid ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, 371ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes raw_ostream &O) { 372ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const MCOperand &MO1 = MI->getOperand(Op); 373ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 374ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 375ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes printOperand(MI, Op, O); 376ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return; 377ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 378ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 379ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes const MCOperand &MO3 = MI->getOperand(Op+2); 380ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); 381ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 382ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes if (IdxMode == ARMII::IndexModePost) { 383ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes printAM2PostIndexOp(MI, Op, O); 384ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return; 385ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 386ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes printAM2PreOrOffsetIndexOp(MI, Op, O); 387ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes} 388ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes 389bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattnervoid ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, 39035c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 39135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 392bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO1 = MI->getOperand(OpNum); 393bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO2 = MI->getOperand(OpNum+1); 39415d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 395bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner if (!MO1.getReg()) { 396bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); 3979e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << '#' 3989e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 3999e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ImmOffs; 400bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner return; 401bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner } 40215d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 4039e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 4049e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << getRegisterName(MO1.getReg()); 40515d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 406bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm())) 407bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << ", " 408bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm())) 409bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner << " #" << ShImm; 410bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner} 411bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 412ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes//===--------------------------------------------------------------------===// 413ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes// Addressing Mode #3 414ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes//===--------------------------------------------------------------------===// 415ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 416ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesvoid ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, 417ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes raw_ostream &O) { 418ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO1 = MI->getOperand(Op); 419ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO2 = MI->getOperand(Op+1); 420ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO3 = MI->getOperand(Op+2); 421ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 422ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes O << "[" << getRegisterName(MO1.getReg()) << "], "; 423ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 424ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes if (MO2.getReg()) { 425ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes O << (char)ARM_AM::getAM3Op(MO3.getImm()) 426ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes << getRegisterName(MO2.getReg()); 427ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return; 428ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 429ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 430ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 431ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes O << '#' 432ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 433ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes << ImmOffs; 434ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 435ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 436ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesvoid ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 437ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes raw_ostream &O) { 438ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO1 = MI->getOperand(Op); 439ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO2 = MI->getOperand(Op+1); 440ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO3 = MI->getOperand(Op+2); 44115d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 442bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << '[' << getRegisterName(MO1.getReg()); 44315d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 444bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner if (MO2.getReg()) { 4457ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 446bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner << getRegisterName(MO2.getReg()) << ']'; 447bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner return; 448bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner } 44915d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 450ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga //If the op is sub we have to print the immediate even if it is 0 451ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 452ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); 453ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga 454ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga if (ImmOffs || (op == ARM_AM::sub)) 455bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << ", #" 456ca3cd419a52c1dedee133d79772ef97f30e5d20bSilviu Baranga << ARM_AM::getAddrOpcStr(op) 4579e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ImmOffs; 458bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << ']'; 459bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner} 460bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 461ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopesvoid ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, 462ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes raw_ostream &O) { 4632f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach const MCOperand &MO1 = MI->getOperand(Op); 4642f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (!MO1.isReg()) { // For label symbolic references. 4652f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach printOperand(MI, Op, O); 4662f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 4672f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 4682f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 469ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes const MCOperand &MO3 = MI->getOperand(Op+2); 470ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm()); 471ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 472ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes if (IdxMode == ARMII::IndexModePost) { 473ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes printAM3PostIndexOp(MI, Op, O); 474ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return; 475ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 476ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes printAM3PreOrOffsetIndexOp(MI, Op, O); 477ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes} 478ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes 479bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattnervoid ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, 48035c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 48135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 482bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO1 = MI->getOperand(OpNum); 483bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO2 = MI->getOperand(OpNum+1); 48415d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 485bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner if (MO1.getReg()) { 4867ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 4877ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach << getRegisterName(MO1.getReg()); 488bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner return; 489bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner } 49015d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 491bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); 4929e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << '#' 4939e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 4949e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ImmOffs; 495bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner} 496bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 4977ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbachvoid ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, 4987ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned OpNum, 4997ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach raw_ostream &O) { 5007ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach const MCOperand &MO = MI->getOperand(OpNum); 5017ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach unsigned Imm = MO.getImm(); 5027ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); 5037ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach} 5047ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach 505ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbachvoid ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, 506ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach raw_ostream &O) { 507ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach const MCOperand &MO1 = MI->getOperand(OpNum); 508ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach const MCOperand &MO2 = MI->getOperand(OpNum+1); 509ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach 51016578b50889329eb62774148091ba0f38b681a09Jim Grosbach O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg()); 511ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach} 512ca8c70b9536bf351ee92395dae6f99a59c011a3dJim Grosbach 513154c41dbbc06284efd56782a8bc137a25148918eOwen Andersonvoid ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, 514154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson unsigned OpNum, 515154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson raw_ostream &O) { 516154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson const MCOperand &MO = MI->getOperand(OpNum); 517154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson unsigned Imm = MO.getImm(); 518154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2); 519154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson} 520154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson 521154c41dbbc06284efd56782a8bc137a25148918eOwen Anderson 522e6913600c723a10ab1f06a43c93d82ee8e26c71cJim Grosbachvoid ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, 5230a2287b909634991a8e8aa7a93f81f09375227b1Jim Grosbach raw_ostream &O) { 524e6913600c723a10ab1f06a43c93d82ee8e26c71cJim Grosbach ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) 525e6913600c723a10ab1f06a43c93d82ee8e26c71cJim Grosbach .getImm()); 526e6913600c723a10ab1f06a43c93d82ee8e26c71cJim Grosbach O << ARM_AM::getAMSubModeStr(Mode); 527e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner} 528e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner 529bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattnervoid ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, 5300a2287b909634991a8e8aa7a93f81f09375227b1Jim Grosbach raw_ostream &O) { 531bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO1 = MI->getOperand(OpNum); 532bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner const MCOperand &MO2 = MI->getOperand(OpNum+1); 53315d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 534bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 53535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner printOperand(MI, OpNum, O); 536bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner return; 537bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner } 53815d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 539bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << "[" << getRegisterName(MO1.getReg()); 54015d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 5410da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 5420da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); 5430da10cf44d0f22111dae728bb535ade2283d976bOwen Anderson if (ImmOffs || Op == ARM_AM::sub) { 544bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << ", #" 5459e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) 54692b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4Bill Wendling << ImmOffs * 4; 547bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner } 548bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << "]"; 549bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner} 550bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 55135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, 55235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 553235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner const MCOperand &MO1 = MI->getOperand(OpNum); 554235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner const MCOperand &MO2 = MI->getOperand(OpNum+1); 55515d78984d57378c3600ea26c37e1be05863644eaJim Grosbach 556226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson O << "[" << getRegisterName(MO1.getReg()); 557226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson if (MO2.getImm()) { 558226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // FIXME: Both darwin as and GNU as violate ARM docs here. 559273ff31e134d48c8247e981d30e214e82568ff86Bob Wilson O << ", :" << (MO2.getImm() << 3); 560235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner } 561226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson O << "]"; 562226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson} 563226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson 564505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopesvoid ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, 565505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes raw_ostream &O) { 566505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes const MCOperand &MO1 = MI->getOperand(OpNum); 567505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes O << "[" << getRegisterName(MO1.getReg()) << "]"; 568505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes} 569505f3cd2965e65b6b7ad023eaba0e3dc89b67409Bruno Cardoso Lopes 570226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilsonvoid ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, 57135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 57235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 573226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson const MCOperand &MO = MI->getOperand(OpNum); 574226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson if (MO.getReg() == 0) 575226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson O << "!"; 576226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson else 577226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson O << ", " << getRegisterName(MO.getReg()); 578235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner} 579235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner 580eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilsonvoid ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, 581eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson unsigned OpNum, 582eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson raw_ostream &O) { 583235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner const MCOperand &MO = MI->getOperand(OpNum); 584235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner uint32_t v = ~MO.getImm(); 585235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner int32_t lsb = CountTrailingZeros_32(v); 586235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; 587235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); 588235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner O << '#' << lsb << ", #" << width; 589235e2f6a68b5f37d6c1b554330eebc8d32f1aca9Chris Lattner} 590bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 5911adc40cac314b0a77b790b094bca146a3a868452Johnny Chenvoid ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, 5921adc40cac314b0a77b790b094bca146a3a868452Johnny Chen raw_ostream &O) { 5931adc40cac314b0a77b790b094bca146a3a868452Johnny Chen unsigned val = MI->getOperand(OpNum).getImm(); 5941adc40cac314b0a77b790b094bca146a3a868452Johnny Chen O << ARM_MB::MemBOptToString(val); 5951adc40cac314b0a77b790b094bca146a3a868452Johnny Chen} 5961adc40cac314b0a77b790b094bca146a3a868452Johnny Chen 59722f5dc79c05d69391b17e14ed912aa8e98a63027Bob Wilsonvoid ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, 598eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson raw_ostream &O) { 599eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 600580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach bool isASR = (ShiftOp & (1 << 5)) != 0; 601580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach unsigned Amt = ShiftOp & 0x1f; 602580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach if (isASR) 603580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach O << ", asr #" << (Amt == 0 ? 32 : Amt); 604580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach else if (Amt) 605580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9fJim Grosbach O << ", lsl #" << Amt; 606eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson} 607eaf1c98a7c38444d41d1c6dc2074736eec7d452fBob Wilson 608dde038af59506c631ce181aff66e315a0c477f4dJim Grosbachvoid ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, 609dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach raw_ostream &O) { 610dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach unsigned Imm = MI->getOperand(OpNum).getImm(); 611dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach if (Imm == 0) 612dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach return; 613dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); 614dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach O << ", lsl #" << Imm; 615dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach} 616dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach 617dde038af59506c631ce181aff66e315a0c477f4dJim Grosbachvoid ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, 618dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach raw_ostream &O) { 619dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach unsigned Imm = MI->getOperand(OpNum).getImm(); 620dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach // A shift amount of 32 is encoded as 0. 621dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach if (Imm == 0) 622dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach Imm = 32; 623dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); 624dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach O << ", asr #" << Imm; 625dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach} 626dde038af59506c631ce181aff66e315a0c477f4dJim Grosbach 62735c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, 62835c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 629e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner O << "{"; 6309e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { 6319e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (i != OpNum) O << ", "; 632e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner O << getRegisterName(MI->getOperand(i).getReg()); 633e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner } 634e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner O << "}"; 635e306d8d6cccea7461974cec2b0daa2933867eb22Chris Lattner} 6364d1522234192704f45dfd2527c2913fa60be616eChris Lattner 637b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbachvoid ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, 638b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach raw_ostream &O) { 639b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach const MCOperand &Op = MI->getOperand(OpNum); 640b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach if (Op.getImm()) 641b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach O << "be"; 642b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach else 643b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach O << "le"; 644b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach} 645b3af5de2d97c30355b8109e149326b0664d34085Jim Grosbach 646a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopesvoid ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, 647a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes raw_ostream &O) { 6489e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &Op = MI->getOperand(OpNum); 649a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes O << ARM_PROC::IModToString(Op.getImm()); 650a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes} 651a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes 652a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopesvoid ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, 653a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes raw_ostream &O) { 654a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes const MCOperand &Op = MI->getOperand(OpNum); 655a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes unsigned IFlags = Op.getImm(); 656a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes for (int i=2; i >= 0; --i) 657a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes if (IFlags & (1 << i)) 658a2b6e4151b75248f9dbf8067186cba673520f8f4Bruno Cardoso Lopes O << ARM_PROC::IFlagsToString(1 << i); 6592dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson 6602dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson if (IFlags == 0) 6612dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31Owen Anderson O << "none"; 6629e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 6639e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 66435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, 66535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 6669e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &Op = MI->getOperand(OpNum); 667584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned SpecRegRBit = Op.getImm() >> 4; 668584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes unsigned Mask = Op.getImm() & 0xf; 669584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 670acad68da50581de905a994ed3c6b9c197bcea687James Molloy if (getAvailableFeatures() & ARM::FeatureMClass) { 6710fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby unsigned SYSm = Op.getImm(); 6720fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby unsigned Opcode = MI->getOpcode(); 6730fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // For reads of the special registers ignore the "mask encoding" bits 6740fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby // which are only for writes. 6750fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby if (Opcode == ARM::t2MRS_M) 6760fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby SYSm &= 0xff; 6770fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby switch (SYSm) { 678bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unexpected mask value!"); 6790fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0: 6800fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr 6810fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x400: O << "apsr_g"; return; 6820fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0xc00: O << "apsr_nzcvqg"; return; 6830fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 1: 6840fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr 6850fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x401: O << "iapsr_g"; return; 6860fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0xc01: O << "iapsr_nzcvqg"; return; 6870fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 2: 6880fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr 6890fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x402: O << "eapsr_g"; return; 6900fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0xc02: O << "eapsr_nzcvqg"; return; 6910fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 3: 6920fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr 6930fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0x403: O << "xpsr_g"; return; 6940fd4f3c8de07e9cfe2a86093ccada82d64f38bfeKevin Enderby case 0xc03: O << "xpsr_nzcvqg"; return; 695f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 5: 696f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x805: O << "ipsr"; return; 697f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 6: 698f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x806: O << "epsr"; return; 699f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 7: 700f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x807: O << "iepsr"; return; 701f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 8: 702f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x808: O << "msp"; return; 703f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 9: 704f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x809: O << "psp"; return; 705f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x10: 706f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x810: O << "primask"; return; 707f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x11: 708f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x811: O << "basepri"; return; 709f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x12: 710f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x812: O << "basepri_max"; return; 711f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x13: 712f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x813: O << "faultmask"; return; 713f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x14: 714f49a4092bcf679d1634a8023efc593e98a3e5663Kevin Enderby case 0x814: O << "control"; return; 715acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 716acad68da50581de905a994ed3c6b9c197bcea687James Molloy } 717acad68da50581de905a994ed3c6b9c197bcea687James Molloy 718b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as 719b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. 720b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { 721b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach O << "APSR_"; 722b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach switch (Mask) { 723bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unexpected mask value!"); 724b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach case 4: O << "g"; return; 725b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach case 8: O << "nzcvq"; return; 726b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach case 12: O << "nzcvqg"; return; 727b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach } 728b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach } 729b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach 730584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes if (SpecRegRBit) 731b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach O << "SPSR"; 732584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes else 733b29b4dd988c50d5c4a15cd196e7910bf46f30b83Jim Grosbach O << "CPSR"; 734584bf7bb03e4cf1475b26851edcc1ddb66b85028Bruno Cardoso Lopes 7359e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (Mask) { 7369e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << '_'; 7379e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (Mask & 8) O << 'f'; 7389e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (Mask & 4) O << 's'; 7399e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (Mask & 2) O << 'x'; 7409e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (Mask & 1) O << 'c'; 7419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 7429e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 7439e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 74435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, 74535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 746413ae25fb593319caa6e5a16f986863057665331Chris Lattner ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 747b0578512c79134136e8b53c62a8677ab8e600be2Kevin Enderby // Handle the undefined 15 CC value here for printing so we don't abort(). 748b0578512c79134136e8b53c62a8677ab8e600be2Kevin Enderby if ((unsigned)CC == 15) 749b0578512c79134136e8b53c62a8677ab8e600be2Kevin Enderby O << "<und>"; 750b0578512c79134136e8b53c62a8677ab8e600be2Kevin Enderby else if (CC != ARMCC::AL) 751413ae25fb593319caa6e5a16f986863057665331Chris Lattner O << ARMCondCodeToString(CC); 752413ae25fb593319caa6e5a16f986863057665331Chris Lattner} 753413ae25fb593319caa6e5a16f986863057665331Chris Lattner 75415d78984d57378c3600ea26c37e1be05863644eaJim Grosbachvoid ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, 75535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 75635c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 7579d3acaa1a015c4499595eaff529686a517c14e15Johnny Chen ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 7589d3acaa1a015c4499595eaff529686a517c14e15Johnny Chen O << ARMCondCodeToString(CC); 7599d3acaa1a015c4499595eaff529686a517c14e15Johnny Chen} 7609d3acaa1a015c4499595eaff529686a517c14e15Johnny Chen 76135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, 76235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 763a7cc65283af74e8681522d4ede4d7c15d04f58e3Daniel Dunbar if (MI->getOperand(OpNum).getReg()) { 764a7cc65283af74e8681522d4ede4d7c15d04f58e3Daniel Dunbar assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && 765a7cc65283af74e8681522d4ede4d7c15d04f58e3Daniel Dunbar "Expect ARM CPSR register!"); 766233917c07282564351439df8e7a9c83c9d6c459eChris Lattner O << 's'; 767233917c07282564351439df8e7a9c83c9d6c459eChris Lattner } 768233917c07282564351439df8e7a9c83c9d6c459eChris Lattner} 769233917c07282564351439df8e7a9c83c9d6c459eChris Lattner 77035c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, 77135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 772bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner O << MI->getOperand(OpNum).getImm(); 773bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner} 774bf16faa16a7042c6d899e08730398e7c2e9c0edfChris Lattner 775e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Andersonvoid ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, 776bc9c80240bc922cffb02cae390181bf42ad231e5Jim Grosbach raw_ostream &O) { 777e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson O << "p" << MI->getOperand(OpNum).getImm(); 778e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 779e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 780e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Andersonvoid ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, 781bc9c80240bc922cffb02cae390181bf42ad231e5Jim Grosbach raw_ostream &O) { 782e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson O << "c" << MI->getOperand(OpNum).getImm(); 783e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson} 784e4e5e2aae7e1e0e84877061432e7b981a360a77dOwen Anderson 7859b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbachvoid ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, 7869b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach raw_ostream &O) { 7879b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach O << "{" << MI->getOperand(OpNum).getImm() << "}"; 7889b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach} 7899b8f2a0b365ea62a5fef80bbaab3cf0252db2fcfJim Grosbach 79035c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, 79135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 792d30cfde935cf5a8649285b6c47abb5e0f6669590Jim Grosbach llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); 7934d1522234192704f45dfd2527c2913fa60be616eChris Lattner} 7942ef9c8a43d1030bf65cafedf4b4b3f04d30180ceEvan Cheng 7951fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liuvoid ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, 7961fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu raw_ostream &O) { 7971fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu const MCOperand &MO = MI->getOperand(OpNum); 7981fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu 7991fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu if (MO.isExpr()) { 8001fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu O << *MO.getExpr(); 8011fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu return; 8021fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu } 8031fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu 8041fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu int32_t OffImm = (int32_t)MO.getImm(); 8051fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu 8061fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu if (OffImm == INT32_MIN) 8071fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu O << "#-0"; 8081fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu else if (OffImm < 0) 8091fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu O << "#-" << -OffImm; 8101fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu else 8111fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu O << "#" << OffImm; 8121fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu} 8131fb27eccf5b7eabde9678d84411eb1df8a693683Jiangning Liu 81435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, 81535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 81670939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach O << "#" << MI->getOperand(OpNum).getImm() * 4; 81770939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach} 81870939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach 81970939ee1415722d7f39f13faf9b3644b96007996Jim Grosbachvoid ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, 82070939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach raw_ostream &O) { 82170939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach unsigned Imm = MI->getOperand(OpNum).getImm(); 82270939ee1415722d7f39f13faf9b3644b96007996Jim Grosbach O << "#" << (Imm == 0 ? 32 : Imm); 8232ef9c8a43d1030bf65cafedf4b4b3f04d30180ceEvan Cheng} 8249e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 82535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, 82635c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 8279e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // (3 - the number of trailing zeros) is the number of then / else. 8289e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen unsigned Mask = MI->getOperand(OpNum).getImm(); 8294d2f077df1b46a126b5595d983f233ec896b757eRichard Barton unsigned Firstcond = MI->getOperand(OpNum-1).getImm(); 8304d2f077df1b46a126b5595d983f233ec896b757eRichard Barton unsigned CondBit0 = Firstcond & 1; 8319e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen unsigned NumTZ = CountTrailingZeros_32(Mask); 8329e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen assert(NumTZ <= 3 && "Invalid IT mask!"); 8339e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 8349e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen bool T = ((Mask >> Pos) & 1) == CondBit0; 8359e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (T) 8369e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << 't'; 8379e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen else 8389e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << 'e'; 8399e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 8409e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 84235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, 84335c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 8449e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(Op); 845f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling const MCOperand &MO2 = MI->getOperand(Op + 1); 846f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling 847f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 848f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling printOperand(MI, Op, O); 849f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling return; 850f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling } 851f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling 8529e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 853f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling if (unsigned RegNum = MO2.getReg()) 854f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling O << ", " << getRegisterName(RegNum); 855f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling O << "]"; 8569e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8579e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 858f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendlingvoid ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, 859f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling unsigned Op, 860f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling raw_ostream &O, 861f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling unsigned Scale) { 8629e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(Op); 863f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling const MCOperand &MO2 = MI->getOperand(Op + 1); 8649e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 8659e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 86635c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner printOperand(MI, Op, O); 8679e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen return; 8689e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 8699e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 8709e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 871f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling if (unsigned ImmOffs = MO2.getImm()) 8729e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", #" << ImmOffs * Scale; 8739e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "]"; 8749e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8759e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 876f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendlingvoid ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, 877f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling unsigned Op, 878f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling raw_ostream &O) { 879f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling printThumbAddrModeImm5SOperand(MI, Op, O, 1); 8809e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8819e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 882f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendlingvoid ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, 883f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling unsigned Op, 884f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling raw_ostream &O) { 885f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling printThumbAddrModeImm5SOperand(MI, Op, O, 2); 8869e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8879e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 888f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendlingvoid ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, 889f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling unsigned Op, 890f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling raw_ostream &O) { 891f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling printThumbAddrModeImm5SOperand(MI, Op, O, 4); 8929e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8939e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 89435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, 89535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 896f4caf69720d807573c50d41aa06bcec1c99bdbbdBill Wendling printThumbAddrModeImm5SOperand(MI, Op, O, 4); 8979e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 8989e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 8999e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 9009e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen// register with shift forms. 9019e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen// REG 0 0 - e.g. R5 9029e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen// REG IMM, SH_OPC - e.g. R5, LSL #3 90335c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattnervoid ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, 90435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 9059e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 9069e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(OpNum+1); 9079e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9089e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen unsigned Reg = MO1.getReg(); 9099e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << getRegisterName(Reg); 9109e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9119e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Print the shift opc. 9129e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen assert(MO2.isImm() && "Not a valid t2_so_reg value!"); 9131d9125a6ff192f1346d2b08bbf6ecc9c9e44103dBob Wilson ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); 9141d9125a6ff192f1346d2b08bbf6ecc9c9e44103dBob Wilson O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 9151d9125a6ff192f1346d2b08bbf6ecc9c9e44103dBob Wilson if (ShOpc != ARM_AM::rrx) 9163dac0bec7e7874ffb378385b6160bd2117184ca9Owen Anderson O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 9179e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 9189e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 919458f2dc5d1b0120bd5921582eb1149ea770568bdJim Grosbachvoid ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, 920458f2dc5d1b0120bd5921582eb1149ea770568bdJim Grosbach raw_ostream &O) { 9219e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 9229e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(OpNum+1); 9239e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9243e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 9253e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach printOperand(MI, OpNum, O); 9263e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach return; 9273e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach } 9283e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach 9299e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 9309e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 93177aee8e22c36257716c2df2f275724765704f20cJim Grosbach int32_t OffImm = (int32_t)MO2.getImm(); 932ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach bool isSub = OffImm < 0; 933ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach // Special value for #-0. All others are normal. 934ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach if (OffImm == INT32_MIN) 935ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach OffImm = 0; 936ab682a2090f795d0b67f29889622da0a74cd97c3Jim Grosbach if (isSub) 93777aee8e22c36257716c2df2f275724765704f20cJim Grosbach O << ", #-" << -OffImm; 93877aee8e22c36257716c2df2f275724765704f20cJim Grosbach else if (OffImm > 0) 9399e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", #" << OffImm; 9409e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "]"; 9419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 9429e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9439e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chenvoid ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, 94435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 94535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 9469e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 9479e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(OpNum+1); 9489e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9499e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 9509e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9519e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen int32_t OffImm = (int32_t)MO2.getImm(); 9529e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Don't print +0. 953705b48ff860e7484f0adee88362dbe1936ae936bOwen Anderson if (OffImm == INT32_MIN) 954705b48ff860e7484f0adee88362dbe1936ae936bOwen Anderson O << ", #-0"; 955705b48ff860e7484f0adee88362dbe1936ae936bOwen Anderson else if (OffImm < 0) 9569e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", #-" << -OffImm; 9579e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen else if (OffImm > 0) 9589e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", #" << OffImm; 9599e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "]"; 9609e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 9619e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9629e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chenvoid ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, 96335c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 96435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 9659e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 9669e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(OpNum+1); 9679e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 9682f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach if (!MO1.isReg()) { // For label symbolic references. 9692f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach printOperand(MI, OpNum, O); 9702f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach return; 9712f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach } 9722f196747f15240691bd4e622f7995edfedf90f61Jim Grosbach 9739e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 9749e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 975fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu int32_t OffImm = (int32_t)MO2.getImm(); 976fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu 977fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 978fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu 9799e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Don't print +0. 980fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu if (OffImm == INT32_MIN) 981fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #-0"; 982fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu else if (OffImm < 0) 983fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #-" << -OffImm; 9849e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen else if (OffImm > 0) 985fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #" << OffImm; 9869e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "]"; 9879e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 9889e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 989b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbachvoid ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI, 990b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach unsigned OpNum, 991b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach raw_ostream &O) { 992b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach const MCOperand &MO1 = MI->getOperand(OpNum); 993b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach const MCOperand &MO2 = MI->getOperand(OpNum+1); 994b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 995b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach O << "[" << getRegisterName(MO1.getReg()); 996b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach if (MO2.getImm()) 997b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach O << ", #" << MO2.getImm() * 4; 998b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach O << "]"; 999b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach} 1000b6aed508e310e31dcb080e761ca856127cec0773Jim Grosbach 10019e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chenvoid ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, 100235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 100335c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 10049e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 10059e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen int32_t OffImm = (int32_t)MO1.getImm(); 10069e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Don't print +0. 10079e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (OffImm < 0) 10080781c1f700886f94f5430380a5e82d7ccf6bbdc0Owen Anderson O << ", #-" << -OffImm; 10090781c1f700886f94f5430380a5e82d7ccf6bbdc0Owen Anderson else 10100781c1f700886f94f5430380a5e82d7ccf6bbdc0Owen Anderson O << ", #" << OffImm; 10119e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 10129e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10139e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chenvoid ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, 101435c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 101535c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 10169e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 1017fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu int32_t OffImm = (int32_t)MO1.getImm(); 1018fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu 1019fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 1020fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu 10219e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen // Don't print +0. 1022fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu if (OffImm == INT32_MIN) 1023fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #-0"; 1024fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu else if (OffImm < 0) 1025fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #-" << -OffImm; 1026fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu else if (OffImm > 0) 1027fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaaJiangning Liu O << ", #" << OffImm; 10289e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 10299e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10309e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chenvoid ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, 103135c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner unsigned OpNum, 103235c33bd772b3cfb34fdc6b5c9171f955454d0043Chris Lattner raw_ostream &O) { 10339e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO1 = MI->getOperand(OpNum); 10349e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO2 = MI->getOperand(OpNum+1); 10359e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen const MCOperand &MO3 = MI->getOperand(OpNum+2); 10369e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10379e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "[" << getRegisterName(MO1.getReg()); 10389e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10399e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen assert(MO2.getReg() && "Invalid so_reg load / store address!"); 10409e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", " << getRegisterName(MO2.getReg()); 10419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10429e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen unsigned ShAmt = MO3.getImm(); 10439e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen if (ShAmt) { 10449e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); 10459e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << ", lsl #" << ShAmt; 10469e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 10479e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen O << "]"; 10489e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 10499e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10504ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbachvoid ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 10514ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach raw_ostream &O) { 10528cb415e4c0032300a1b728c942f8b31acec0a9f5Bill Wendling const MCOperand &MO = MI->getOperand(OpNum); 10534ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach O << '#' << ARM_AM::getFPImmFloat(MO.getImm()); 10549e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen} 10559e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 10561a913ed17875d1a0fb490e1266b74c057c76a94bBob Wilsonvoid ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, 10571a913ed17875d1a0fb490e1266b74c057c76a94bBob Wilson raw_ostream &O) { 10586dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned EncodedImm = MI->getOperand(OpNum).getImm(); 10596dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned EltBits; 10606dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); 106170be28a5adba5bcae0c6dcd63f17592864c351fcBenjamin Kramer O << "#0x"; 106270be28a5adba5bcae0c6dcd63f17592864c351fcBenjamin Kramer O.write_hex(Val); 1063c7b65914e080b5236078e5f58ded5503226bcb71Johnny Chen} 10644a5ffb399f841783c201c599b88d576757f1922eJim Grosbach 1065f49433523e8a39db6d83503e312ae55160eed90aJim Grosbachvoid ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, 1066f49433523e8a39db6d83503e312ae55160eed90aJim Grosbach raw_ostream &O) { 10674a5ffb399f841783c201c599b88d576757f1922eJim Grosbach unsigned Imm = MI->getOperand(OpNum).getImm(); 10684a5ffb399f841783c201c599b88d576757f1922eJim Grosbach O << "#" << Imm + 1; 10694a5ffb399f841783c201c599b88d576757f1922eJim Grosbach} 107085bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach 107185bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbachvoid ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, 107285bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach raw_ostream &O) { 107385bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach unsigned Imm = MI->getOperand(OpNum).getImm(); 107485bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach if (Imm == 0) 107585bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach return; 107645f3929ef0dcdf281a10f23e031ffaba7664e7c0Jim Grosbach O << ", ror #"; 107785bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach switch (Imm) { 107885bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach default: assert (0 && "illegal ror immediate!"); 10792f815c0b50acc506a7bdcdfb63966c40a0d2e71bJim Grosbach case 1: O << "8"; break; 10802f815c0b50acc506a7bdcdfb63966c40a0d2e71bJim Grosbach case 2: O << "16"; break; 10812f815c0b50acc506a7bdcdfb63966c40a0d2e71bJim Grosbach case 3: O << "24"; break; 108285bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach } 108385bfd3b023d4d70936006eadd86588b03e5f40c0Jim Grosbach} 1084460a90540b045c102012da2492999557e6840526Jim Grosbach 10854050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbachvoid ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, 10864050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach raw_ostream &O) { 10874050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach O << "#" << 16 - MI->getOperand(OpNum).getImm(); 10884050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach} 10894050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 10904050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbachvoid ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, 10914050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach raw_ostream &O) { 10924050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach O << "#" << 32 - MI->getOperand(OpNum).getImm(); 10934050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach} 10944050bc4cab61f8d3c7583a9b60f17c7da47bbf69Jim Grosbach 1095460a90540b045c102012da2492999557e6840526Jim Grosbachvoid ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1096460a90540b045c102012da2492999557e6840526Jim Grosbach raw_ostream &O) { 1097460a90540b045c102012da2492999557e6840526Jim Grosbach O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1098460a90540b045c102012da2492999557e6840526Jim Grosbach} 1099862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach 1100862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbachvoid ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, 1101862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach raw_ostream &O) { 1102862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}"; 1103862019c37f5b5d76e34eeb0d5686e617d544059fJim Grosbach} 1104280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach 1105c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbachvoid ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, 110628f08c93e75d291695ea89b9004145103292e85bJim Grosbach raw_ostream &O) { 110728f08c93e75d291695ea89b9004145103292e85bJim Grosbach unsigned Reg = MI->getOperand(OpNum).getReg(); 110828f08c93e75d291695ea89b9004145103292e85bJim Grosbach unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 110928f08c93e75d291695ea89b9004145103292e85bJim Grosbach unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 111028f08c93e75d291695ea89b9004145103292e85bJim Grosbach O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 111128f08c93e75d291695ea89b9004145103292e85bJim Grosbach} 111228f08c93e75d291695ea89b9004145103292e85bJim Grosbach 1113c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbachvoid ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, 1114c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach unsigned OpNum, 1115c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach raw_ostream &O) { 1116c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach unsigned Reg = MI->getOperand(OpNum).getReg(); 1117c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1118c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1119c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 1120c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach} 1121c3384c93c0e4c50da4ad093f08997507f9281c75Jim Grosbach 1122cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbachvoid ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, 1123cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach raw_ostream &O) { 1124cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach // Normally, it's not safe to use register enum values directly with 1125cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach // addition to get the next register, but for VFP registers, the 1126cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 1127cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1128cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " 1129cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; 1130cdcfa280568d5d48ebeba2dcfc87915105e090d1Jim Grosbach} 1131b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach 1132b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbachvoid ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum, 1133b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach raw_ostream &O) { 1134b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach // Normally, it's not safe to use register enum values directly with 1135b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach // addition to get the next register, but for VFP registers, the 1136b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 1137b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1138b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", " 1139b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 1140b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}"; 1141b6310316dbaf8716003531d7ed245f77f1a76a11Jim Grosbach} 114298b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 114398b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbachvoid ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, 114498b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach unsigned OpNum, 114598b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach raw_ostream &O) { 114698b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}"; 114798b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach} 114898b05a57b67d1968381563c8cccbbb6c6cb65e3dJim Grosbach 114913af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbachvoid ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, 115013af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach unsigned OpNum, 115113af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach raw_ostream &O) { 1152c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach unsigned Reg = MI->getOperand(OpNum).getReg(); 1153c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1154c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1155c0fc450f0754508871bc70f21e528bf2f1520da1Jim Grosbach O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; 115613af222bab6fdc77d8193eb38e78a9cbed1d9d1fJim Grosbach} 1157e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach 11585e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbachvoid ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, 11595e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach unsigned OpNum, 11605e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach raw_ostream &O) { 11615e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // Normally, it's not safe to use register enum values directly with 11625e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // addition to get the next register, but for VFP registers, the 11635e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 11645e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 11655e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " 11665e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}"; 11675e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach} 11685e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 1169a57a36abe7d0b769a495ed886246db157aff4addJim Grosbachvoid ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, 1170a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach unsigned OpNum, 1171a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach raw_ostream &O) { 1172a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // Normally, it's not safe to use register enum values directly with 1173a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // addition to get the next register, but for VFP registers, the 1174a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // sort order is guaranteed because they're all of the form D<n>. 1175a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1176a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], " 1177a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1178a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}"; 1179a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach} 1180a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 11813471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbachvoid ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, 11823471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach unsigned OpNum, 11833471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach raw_ostream &O) { 11844d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach unsigned Reg = MI->getOperand(OpNum).getReg(); 11854d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 11864d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 11874d0983a4d734280d481bb56472fe44ad0ddc447dJim Grosbach O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; 11883471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach} 11893471d4fbbd50eabb12511b711cbd2afd7bb9d962Jim Grosbach 11905e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbachvoid ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI, 11915e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach unsigned OpNum, 11925e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach raw_ostream &O) { 11935e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // Normally, it's not safe to use register enum values directly with 11945e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // addition to get the next register, but for VFP registers, the 11955e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 11965e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 11975e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1198a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}"; 1199a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach} 1200a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach 1201a57a36abe7d0b769a495ed886246db157aff4addJim Grosbachvoid ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI, 1202a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach unsigned OpNum, 1203a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach raw_ostream &O) { 1204a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // Normally, it's not safe to use register enum values directly with 1205a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // addition to get the next register, but for VFP registers, the 1206a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach // sort order is guaranteed because they're all of the form D<n>. 1207a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " 1208a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], " 1209a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], " 1210a57a36abe7d0b769a495ed886246db157aff4addJim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}"; 12115e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach} 12125e59f7e15ed3770b32481cd72d2c15b159e991e6Jim Grosbach 1213c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbachvoid ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI, 1214c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach unsigned OpNum, 1215c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach raw_ostream &O) { 1216c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // Normally, it's not safe to use register enum values directly with 1217c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // addition to get the next register, but for VFP registers, the 1218c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 1219c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 1220c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 1221c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}"; 1222c387fc66bd52e4276fdc2704a3aaed57cc1f9a11Jim Grosbach} 12238abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach 12248abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbachvoid ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, 12258abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach unsigned OpNum, 12268abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach raw_ostream &O) { 12278abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach // Normally, it's not safe to use register enum values directly with 12288abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach // addition to get the next register, but for VFP registers, the 12298abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach // sort order is guaranteed because they're all of the form D<n>. 12308abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " 12318abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", " 12328abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", " 12338abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}"; 12348abe7e33641fccfa70a7e335939e83dfbf654fe8Jim Grosbach} 1235