Thumb1RegisterInfo.cpp revision 815baebe1c8dc02accf128ae10dff9a1742d3244 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "Thumb1InstrInfo.h"
21#include "Thumb1RegisterInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/Target/TargetFrameInfo.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41extern cl::opt<bool> ReuseFrameIndexVals;
42
43Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
44                                       const ARMSubtarget &sti)
45  : ARMBaseRegisterInfo(tii, sti) {
46}
47
48/// emitLoadConstPool - Emits a load from constpool to materialize the
49/// specified immediate.
50void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
51                                           MachineBasicBlock::iterator &MBBI,
52                                           DebugLoc dl,
53                                           unsigned DestReg, unsigned SubIdx,
54                                           int Val,
55                                           ARMCC::CondCodes Pred,
56                                           unsigned PredReg) const {
57  MachineFunction &MF = *MBB.getParent();
58  MachineConstantPool *ConstantPool = MF.getConstantPool();
59  Constant *C = ConstantInt::get(
60          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
61  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
62
63  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
64          .addReg(DestReg, getDefRegState(true), SubIdx)
65          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
66}
67
68const TargetRegisterClass*
69Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
70  if (isARMLowRegister(Reg))
71    return ARM::tGPRRegisterClass;
72  switch (Reg) {
73   default:
74    break;
75   case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
76   case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
77    return ARM::GPRRegisterClass;
78  }
79
80  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
81}
82
83bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
84  const MachineFrameInfo *FFI = MF.getFrameInfo();
85  unsigned CFSize = FFI->getMaxCallFrameSize();
86  // It's not always a good idea to include the call frame as part of the
87  // stack frame. ARM (especially Thumb) has small immediate offset to
88  // address the stack frame. So a large call frame can cause poor codegen
89  // and may even makes it impossible to scavenge a register.
90  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
91    return false;
92
93  return !MF.getFrameInfo()->hasVarSizedObjects();
94}
95
96
97/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
98/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
99/// in a register using mov / mvn sequences or load the immediate from a
100/// constpool entry.
101static
102void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
103                              MachineBasicBlock::iterator &MBBI,
104                              unsigned DestReg, unsigned BaseReg,
105                              int NumBytes, bool CanChangeCC,
106                              const TargetInstrInfo &TII,
107                              const Thumb1RegisterInfo& MRI,
108                              DebugLoc dl) {
109    MachineFunction &MF = *MBB.getParent();
110    bool isHigh = !isARMLowRegister(DestReg) ||
111                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
112    bool isSub = false;
113    // Subtract doesn't have high register version. Load the negative value
114    // if either base or dest register is a high register. Also, if do not
115    // issue sub as part of the sequence if condition register is to be
116    // preserved.
117    if (NumBytes < 0 && !isHigh && CanChangeCC) {
118      isSub = true;
119      NumBytes = -NumBytes;
120    }
121    unsigned LdReg = DestReg;
122    if (DestReg == ARM::SP) {
123      assert(BaseReg == ARM::SP && "Unexpected!");
124      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
125    }
126
127    if (NumBytes <= 255 && NumBytes >= 0)
128      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
129        .addImm(NumBytes);
130    else if (NumBytes < 0 && NumBytes >= -255) {
131      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
132        .addImm(NumBytes);
133      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
134        .addReg(LdReg, RegState::Kill);
135    } else
136      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
137
138    // Emit add / sub.
139    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
140    MachineInstrBuilder MIB =
141      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
142    if (Opc != ARM::tADDhirr)
143      MIB = AddDefaultT1CC(MIB);
144    if (DestReg == ARM::SP || isSub)
145      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
146    else
147      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
148    AddDefaultPred(MIB);
149}
150
151/// calcNumMI - Returns the number of instructions required to materialize
152/// the specific add / sub r, c instruction.
153static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
154                          unsigned NumBits, unsigned Scale) {
155  unsigned NumMIs = 0;
156  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
157
158  if (Opc == ARM::tADDrSPi) {
159    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
160    Bytes -= ThisVal;
161    NumMIs++;
162    NumBits = 8;
163    Scale = 1;  // Followed by a number of tADDi8.
164    Chunk = ((1 << NumBits) - 1) * Scale;
165  }
166
167  NumMIs += Bytes / Chunk;
168  if ((Bytes % Chunk) != 0)
169    NumMIs++;
170  if (ExtraOpc)
171    NumMIs++;
172  return NumMIs;
173}
174
175/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
176/// a destreg = basereg + immediate in Thumb code.
177static
178void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
179                               MachineBasicBlock::iterator &MBBI,
180                               unsigned DestReg, unsigned BaseReg,
181                               int NumBytes, const TargetInstrInfo &TII,
182                               const Thumb1RegisterInfo& MRI,
183                               DebugLoc dl) {
184  bool isSub = NumBytes < 0;
185  unsigned Bytes = (unsigned)NumBytes;
186  if (isSub) Bytes = -NumBytes;
187  bool isMul4 = (Bytes & 3) == 0;
188  bool isTwoAddr = false;
189  bool DstNotEqBase = false;
190  unsigned NumBits = 1;
191  unsigned Scale = 1;
192  int Opc = 0;
193  int ExtraOpc = 0;
194  bool NeedCC = false;
195  bool NeedPred = false;
196
197  if (DestReg == BaseReg && BaseReg == ARM::SP) {
198    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
199    NumBits = 7;
200    Scale = 4;
201    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
202    isTwoAddr = true;
203  } else if (!isSub && BaseReg == ARM::SP) {
204    // r1 = add sp, 403
205    // =>
206    // r1 = add sp, 100 * 4
207    // r1 = add r1, 3
208    if (!isMul4) {
209      Bytes &= ~3;
210      ExtraOpc = ARM::tADDi3;
211    }
212    NumBits = 8;
213    Scale = 4;
214    Opc = ARM::tADDrSPi;
215  } else {
216    // sp = sub sp, c
217    // r1 = sub sp, c
218    // r8 = sub sp, c
219    if (DestReg != BaseReg)
220      DstNotEqBase = true;
221    NumBits = 8;
222    if (DestReg == ARM::SP) {
223      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
224      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
225      NumBits = 7;
226      Scale = 4;
227    } else {
228      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
229      NumBits = 8;
230      NeedPred = NeedCC = true;
231    }
232    isTwoAddr = true;
233  }
234
235  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
236  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
237  if (NumMIs > Threshold) {
238    // This will expand into too many instructions. Load the immediate from a
239    // constpool entry.
240    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
241                             MRI, dl);
242    return;
243  }
244
245  if (DstNotEqBase) {
246    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
247      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
248      unsigned Chunk = (1 << 3) - 1;
249      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
250      Bytes -= ThisVal;
251      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
252      const MachineInstrBuilder MIB =
253        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
254      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
255    } else {
256      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
257        .addReg(BaseReg, RegState::Kill);
258    }
259    BaseReg = DestReg;
260  }
261
262  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
263  while (Bytes) {
264    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
265    Bytes -= ThisVal;
266    ThisVal /= Scale;
267    // Build the new tADD / tSUB.
268    if (isTwoAddr) {
269      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
270      if (NeedCC)
271        MIB = AddDefaultT1CC(MIB);
272      MIB .addReg(DestReg).addImm(ThisVal);
273      if (NeedPred)
274        MIB = AddDefaultPred(MIB);
275    }
276    else {
277      bool isKill = BaseReg != ARM::SP;
278      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
279      if (NeedCC)
280        MIB = AddDefaultT1CC(MIB);
281      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
282      if (NeedPred)
283        MIB = AddDefaultPred(MIB);
284      BaseReg = DestReg;
285
286      if (Opc == ARM::tADDrSPi) {
287        // r4 = add sp, imm
288        // r4 = add r4, imm
289        // ...
290        NumBits = 8;
291        Scale = 1;
292        Chunk = ((1 << NumBits) - 1) * Scale;
293        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
294        NeedPred = NeedCC = isTwoAddr = true;
295      }
296    }
297  }
298
299  if (ExtraOpc) {
300    const TargetInstrDesc &TID = TII.get(ExtraOpc);
301    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
302                   .addReg(DestReg, RegState::Kill)
303                   .addImm(((unsigned)NumBytes) & 3));
304  }
305}
306
307static void emitSPUpdate(MachineBasicBlock &MBB,
308                         MachineBasicBlock::iterator &MBBI,
309                         const TargetInstrInfo &TII, DebugLoc dl,
310                         const Thumb1RegisterInfo &MRI,
311                         int NumBytes) {
312  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
313                            MRI, dl);
314}
315
316void Thumb1RegisterInfo::
317eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
318                              MachineBasicBlock::iterator I) const {
319  if (!hasReservedCallFrame(MF)) {
320    // If we have alloca, convert as follows:
321    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
322    // ADJCALLSTACKUP   -> add, sp, sp, amount
323    MachineInstr *Old = I;
324    DebugLoc dl = Old->getDebugLoc();
325    unsigned Amount = Old->getOperand(0).getImm();
326    if (Amount != 0) {
327      // We need to keep the stack aligned properly.  To do this, we round the
328      // amount of space needed for the outgoing arguments up to the next
329      // alignment boundary.
330      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
331      Amount = (Amount+Align-1)/Align*Align;
332
333      // Replace the pseudo instruction with a new instruction...
334      unsigned Opc = Old->getOpcode();
335      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
336        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
337      } else {
338        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
339        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
340      }
341    }
342  }
343  MBB.erase(I);
344}
345
346/// emitThumbConstant - Emit a series of instructions to materialize a
347/// constant.
348static void emitThumbConstant(MachineBasicBlock &MBB,
349                              MachineBasicBlock::iterator &MBBI,
350                              unsigned DestReg, int Imm,
351                              const TargetInstrInfo &TII,
352                              const Thumb1RegisterInfo& MRI,
353                              DebugLoc dl) {
354  bool isSub = Imm < 0;
355  if (isSub) Imm = -Imm;
356
357  int Chunk = (1 << 8) - 1;
358  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
359  Imm -= ThisVal;
360  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
361                                        DestReg))
362                 .addImm(ThisVal));
363  if (Imm > 0)
364    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
365  if (isSub) {
366    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
367    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
368                   .addReg(DestReg, RegState::Kill));
369  }
370}
371
372static void removeOperands(MachineInstr &MI, unsigned i) {
373  unsigned Op = i;
374  for (unsigned e = MI.getNumOperands(); i != e; ++i)
375    MI.RemoveOperand(Op);
376}
377
378int Thumb1RegisterInfo::
379rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
380                  unsigned FrameReg, int Offset,
381                  unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
382{
383  // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
384  // version then can pull out Thumb1 specific parts here
385  return 0;
386}
387
388/// saveScavengerRegister - Spill the register so it can be used by the
389/// register scavenger. Return true.
390bool
391Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
392                                          MachineBasicBlock::iterator I,
393                                          MachineBasicBlock::iterator &UseMI,
394                                          const TargetRegisterClass *RC,
395                                          unsigned Reg) const {
396  // Thumb1 can't use the emergency spill slot on the stack because
397  // ldr/str immediate offsets must be positive, and if we're referencing
398  // off the frame pointer (if, for example, there are alloca() calls in
399  // the function, the offset will be negative. Use R12 instead since that's
400  // a call clobbered register that we know won't be used in Thumb1 mode.
401  DebugLoc DL = DebugLoc::getUnknownLoc();
402  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
403    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
404
405  // The UseMI is where we would like to restore the register. If there's
406  // interference with R12 before then, however, we'll need to restore it
407  // before that instead and adjust the UseMI.
408  bool done = false;
409  for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
410    // If this instruction affects R12, adjust our restore point.
411    for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
412      const MachineOperand &MO = II->getOperand(i);
413      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
414          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
415        continue;
416      if (MO.getReg() == ARM::R12) {
417        UseMI = II;
418        done = true;
419        break;
420      }
421    }
422  }
423  // Restore the register from R12
424  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
425    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
426
427  return true;
428}
429
430unsigned
431Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
432                                        int SPAdj, FrameIndexValue *Value,
433                                        RegScavenger *RS) const{
434  unsigned VReg = 0;
435  unsigned i = 0;
436  MachineInstr &MI = *II;
437  MachineBasicBlock &MBB = *MI.getParent();
438  MachineFunction &MF = *MBB.getParent();
439  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
440  DebugLoc dl = MI.getDebugLoc();
441
442  while (!MI.getOperand(i).isFI()) {
443    ++i;
444    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
445  }
446
447  unsigned FrameReg = ARM::SP;
448  int FrameIndex = MI.getOperand(i).getIndex();
449  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
450               MF.getFrameInfo()->getStackSize() + SPAdj;
451
452  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
453    Offset -= AFI->getGPRCalleeSavedArea1Offset();
454  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
455    Offset -= AFI->getGPRCalleeSavedArea2Offset();
456  else if (MF.getFrameInfo()->hasVarSizedObjects()) {
457    assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
458    // There are alloca()'s in this function, must reference off the frame
459    // pointer instead.
460    FrameReg = getFrameRegister(MF);
461    Offset -= AFI->getFramePtrSpillOffset();
462  }
463
464  unsigned Opcode = MI.getOpcode();
465  const TargetInstrDesc &Desc = MI.getDesc();
466  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
467
468  if (Opcode == ARM::tADDrSPi) {
469    Offset += MI.getOperand(i+1).getImm();
470
471    // Can't use tADDrSPi if it's based off the frame pointer.
472    unsigned NumBits = 0;
473    unsigned Scale = 1;
474    if (FrameReg != ARM::SP) {
475      Opcode = ARM::tADDi3;
476      MI.setDesc(TII.get(Opcode));
477      NumBits = 3;
478    } else {
479      NumBits = 8;
480      Scale = 4;
481      assert((Offset & 3) == 0 &&
482             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
483    }
484
485    unsigned PredReg;
486    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
487      // Turn it into a move.
488      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
489      MI.getOperand(i).ChangeToRegister(FrameReg, false);
490      // Remove offset and remaining explicit predicate operands.
491      do MI.RemoveOperand(i+1);
492      while (MI.getNumOperands() > i+1 &&
493             (!MI.getOperand(i+1).isReg() || !MI.getOperand(i+1).isImm()));
494      return 0;
495    }
496
497    // Common case: small offset, fits into instruction.
498    unsigned Mask = (1 << NumBits) - 1;
499    if (((Offset / Scale) & ~Mask) == 0) {
500      // Replace the FrameIndex with sp / fp
501      if (Opcode == ARM::tADDi3) {
502        removeOperands(MI, i);
503        MachineInstrBuilder MIB(&MI);
504        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
505                       .addImm(Offset / Scale));
506      } else {
507        MI.getOperand(i).ChangeToRegister(FrameReg, false);
508        MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
509      }
510      return 0;
511    }
512
513    unsigned DestReg = MI.getOperand(0).getReg();
514    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
515    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
516    // MI would expand into a large number of instructions. Don't try to
517    // simplify the immediate.
518    if (NumMIs > 2) {
519      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
520                                *this, dl);
521      MBB.erase(II);
522      return 0;
523    }
524
525    if (Offset > 0) {
526      // Translate r0 = add sp, imm to
527      // r0 = add sp, 255*4
528      // r0 = add r0, (imm - 255*4)
529      if (Opcode == ARM::tADDi3) {
530        removeOperands(MI, i);
531        MachineInstrBuilder MIB(&MI);
532        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
533      } else {
534        MI.getOperand(i).ChangeToRegister(FrameReg, false);
535        MI.getOperand(i+1).ChangeToImmediate(Mask);
536      }
537      Offset = (Offset - Mask * Scale);
538      MachineBasicBlock::iterator NII = llvm::next(II);
539      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
540                                *this, dl);
541    } else {
542      // Translate r0 = add sp, -imm to
543      // r0 = -imm (this is then translated into a series of instructons)
544      // r0 = add r0, sp
545      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
546
547      MI.setDesc(TII.get(ARM::tADDhirr));
548      MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
549      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
550      if (Opcode == ARM::tADDi3) {
551        MachineInstrBuilder MIB(&MI);
552        AddDefaultPred(MIB);
553      }
554    }
555    return 0;
556  } else {
557    unsigned ImmIdx = 0;
558    int InstrOffs = 0;
559    unsigned NumBits = 0;
560    unsigned Scale = 1;
561    switch (AddrMode) {
562    case ARMII::AddrModeT1_s: {
563      ImmIdx = i+1;
564      InstrOffs = MI.getOperand(ImmIdx).getImm();
565      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
566      Scale = 4;
567      break;
568    }
569    default:
570      llvm_unreachable("Unsupported addressing mode!");
571      break;
572    }
573
574    Offset += InstrOffs * Scale;
575    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
576
577    // Common case: small offset, fits into instruction.
578    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
579    int ImmedOffset = Offset / Scale;
580    unsigned Mask = (1 << NumBits) - 1;
581    if ((unsigned)Offset <= Mask * Scale) {
582      // Replace the FrameIndex with sp
583      MI.getOperand(i).ChangeToRegister(FrameReg, false);
584      ImmOp.ChangeToImmediate(ImmedOffset);
585      return 0;
586    }
587
588    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
589    if (AddrMode == ARMII::AddrModeT1_s) {
590      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
591      // a different base register.
592      NumBits = 5;
593      Mask = (1 << NumBits) - 1;
594    }
595    // If this is a thumb spill / restore, we will be using a constpool load to
596    // materialize the offset.
597    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
598      ImmOp.ChangeToImmediate(0);
599    else {
600      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
601      ImmedOffset = ImmedOffset & Mask;
602      ImmOp.ChangeToImmediate(ImmedOffset);
603      Offset &= ~(Mask*Scale);
604    }
605  }
606
607  // If we get here, the immediate doesn't fit into the instruction.  We folded
608  // as much as possible above, handle the rest, providing a register that is
609  // SP+LargeImm.
610  assert(Offset && "This code isn't needed if offset already handled!");
611
612  // Remove predicate first.
613  int PIdx = MI.findFirstPredOperandIdx();
614  if (PIdx != -1)
615    removeOperands(MI, PIdx);
616
617  if (Desc.mayLoad()) {
618    // Use the destination register to materialize sp + offset.
619    unsigned TmpReg = MI.getOperand(0).getReg();
620    bool UseRR = false;
621    if (Opcode == ARM::tRestore) {
622      if (FrameReg == ARM::SP)
623        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
624                                 Offset, false, TII, *this, dl);
625      else {
626        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
627        UseRR = true;
628      }
629    } else {
630      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
631                                *this, dl);
632    }
633
634    MI.setDesc(TII.get(ARM::tLDR));
635    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
636    if (UseRR)
637      // Use [reg, reg] addrmode.
638      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
639    else  // tLDR has an extra register operand.
640      MI.addOperand(MachineOperand::CreateReg(0, false));
641  } else if (Desc.mayStore()) {
642      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
643      assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
644      bool UseRR = false;
645      bool TrackVReg = true;
646      Value->first = FrameReg; // use the frame register as a kind indicator
647      Value->second = Offset;
648
649      if (Opcode == ARM::tSpill) {
650        if (FrameReg == ARM::SP)
651          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
652                                   Offset, false, TII, *this, dl);
653        else {
654          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
655          UseRR = true;
656          TrackVReg = false;
657        }
658      } else
659        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
660                                  *this, dl);
661      MI.setDesc(TII.get(ARM::tSTR));
662      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
663      if (UseRR)  // Use [reg, reg] addrmode.
664        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
665      else // tSTR has an extra register operand.
666        MI.addOperand(MachineOperand::CreateReg(0, false));
667      if (!ReuseFrameIndexVals || !TrackVReg)
668        VReg = 0;
669  } else
670    assert(false && "Unexpected opcode!");
671
672  // Add predicate back if it's needed.
673  if (MI.getDesc().isPredicable()) {
674    MachineInstrBuilder MIB(&MI);
675    AddDefaultPred(MIB);
676  }
677  return VReg;
678}
679
680void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
681  MachineBasicBlock &MBB = MF.front();
682  MachineBasicBlock::iterator MBBI = MBB.begin();
683  MachineFrameInfo  *MFI = MF.getFrameInfo();
684  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
685  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
686  unsigned NumBytes = MFI->getStackSize();
687  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
688  DebugLoc dl = (MBBI != MBB.end() ?
689                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
690
691  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
692  NumBytes = (NumBytes + 3) & ~3;
693  MFI->setStackSize(NumBytes);
694
695  // Determine the sizes of each callee-save spill areas and record which frame
696  // belongs to which callee-save spill areas.
697  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
698  int FramePtrSpillFI = 0;
699
700  if (VARegSaveSize)
701    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
702
703  if (!AFI->hasStackFrame()) {
704    if (NumBytes != 0)
705      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
706    return;
707  }
708
709  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
710    unsigned Reg = CSI[i].getReg();
711    int FI = CSI[i].getFrameIdx();
712    switch (Reg) {
713    case ARM::R4:
714    case ARM::R5:
715    case ARM::R6:
716    case ARM::R7:
717    case ARM::LR:
718      if (Reg == FramePtr)
719        FramePtrSpillFI = FI;
720      AFI->addGPRCalleeSavedArea1Frame(FI);
721      GPRCS1Size += 4;
722      break;
723    case ARM::R8:
724    case ARM::R9:
725    case ARM::R10:
726    case ARM::R11:
727      if (Reg == FramePtr)
728        FramePtrSpillFI = FI;
729      if (STI.isTargetDarwin()) {
730        AFI->addGPRCalleeSavedArea2Frame(FI);
731        GPRCS2Size += 4;
732      } else {
733        AFI->addGPRCalleeSavedArea1Frame(FI);
734        GPRCS1Size += 4;
735      }
736      break;
737    default:
738      AFI->addDPRCalleeSavedAreaFrame(FI);
739      DPRCSSize += 8;
740    }
741  }
742
743  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
744    ++MBBI;
745    if (MBBI != MBB.end())
746      dl = MBBI->getDebugLoc();
747  }
748
749  // Darwin ABI requires FP to point to the stack slot that contains the
750  // previous FP.
751  if (STI.isTargetDarwin() || hasFP(MF)) {
752    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
753      .addFrameIndex(FramePtrSpillFI).addImm(0);
754  }
755
756  // Determine starting offsets of spill areas.
757  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
758  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
759  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
760  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
761  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
762  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
763  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
764
765  NumBytes = DPRCSOffset;
766  if (NumBytes) {
767    // Insert it after all the callee-save spills.
768    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
769  }
770
771  if (STI.isTargetELF() && hasFP(MF)) {
772    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
773                             AFI->getFramePtrSpillOffset());
774  }
775
776  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
777  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
778  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
779}
780
781static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
782  for (unsigned i = 0; CSRegs[i]; ++i)
783    if (Reg == CSRegs[i])
784      return true;
785  return false;
786}
787
788static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
789  if (MI->getOpcode() == ARM::tRestore &&
790      MI->getOperand(1).isFI() &&
791      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
792    return true;
793  else if (MI->getOpcode() == ARM::tPOP) {
794    // The first two operands are predicates. The last two are
795    // imp-def and imp-use of SP. Check everything in between.
796    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
797      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
798        return false;
799    return true;
800  }
801  return false;
802}
803
804void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
805                                      MachineBasicBlock &MBB) const {
806  MachineBasicBlock::iterator MBBI = prior(MBB.end());
807  assert((MBBI->getOpcode() == ARM::tBX_RET ||
808          MBBI->getOpcode() == ARM::tPOP_RET) &&
809         "Can only insert epilog into returning blocks");
810  DebugLoc dl = MBBI->getDebugLoc();
811  MachineFrameInfo *MFI = MF.getFrameInfo();
812  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
813  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
814  int NumBytes = (int)MFI->getStackSize();
815  const unsigned *CSRegs = getCalleeSavedRegs();
816
817  if (!AFI->hasStackFrame()) {
818    if (NumBytes != 0)
819      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
820  } else {
821    // Unwind MBBI to point to first LDR / VLDRD.
822    if (MBBI != MBB.begin()) {
823      do
824        --MBBI;
825      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
826      if (!isCSRestore(MBBI, CSRegs))
827        ++MBBI;
828    }
829
830    // Move SP to start of FP callee save spill area.
831    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
832                 AFI->getGPRCalleeSavedArea2Size() +
833                 AFI->getDPRCalleeSavedAreaSize());
834
835    if (hasFP(MF)) {
836      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
837      // Reset SP based on frame pointer only if the stack frame extends beyond
838      // frame pointer stack slot or target is ELF and the function has FP.
839      if (NumBytes)
840        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
841                                  TII, *this, dl);
842      else
843        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
844          .addReg(FramePtr);
845    } else {
846      if (MBBI->getOpcode() == ARM::tBX_RET &&
847          &MBB.front() != MBBI &&
848          prior(MBBI)->getOpcode() == ARM::tPOP) {
849        MachineBasicBlock::iterator PMBBI = prior(MBBI);
850        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
851      } else
852        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
853    }
854  }
855
856  if (VARegSaveSize) {
857    // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
858    // to LR, and we can't pop the value directly to the PC since
859    // we need to update the SP after popping the value. Therefore, we
860    // pop the old LR into R3 as a temporary.
861
862    // Move back past the callee-saved register restoration
863    while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
864      ++MBBI;
865    // Epilogue for vararg functions: pop LR to R3 and branch off it.
866    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
867      .addReg(ARM::R3, RegState::Define);
868
869    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
870
871    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
872      .addReg(ARM::R3, RegState::Kill);
873    // erase the old tBX_RET instruction
874    MBB.erase(MBBI);
875  }
876}
877