History log of /external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 08-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
420761a0f193e87d08ee1c51b26bba23ab4bac7f 20-Apr-2012 Craig Topper <craig.topper@gmail.com> Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
c1f6f42049696e7357fb4837e1b25dabbaed3fe6 17-Mar-2012 Craig Topper <craig.topper@gmail.com> Reorder includes to match coding standards. Fix an issue or two exposed by that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b24b820bd7ddfe118141422f4d0cf378b2c9a6fd 01-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().

This function could have r12 live across a function call when compiling
thumb1 code.

The test case for this is not included because it is very long. It must
provoke emergency spilling near a function call. The behavior is
provoked by MultiSource/Applications/JM/lencod, and it triggers an
assertion in the scavenger.

<rdar://problem/10963642>

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
0f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9 28-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Enable ARM base pointer when calling functions with large arguments.

When an outgoing call takes more than 2k of arguments on the stack, we
don't allocate that call frame in the prolog, but adjust the stack
pointer immediately before the call instead.

This causes problems with the emergency spill slot because PEI can't
track stack pointer adjustments on the second pass, and if the outgoing
arguments are too big, SP can't be used to reach the emergency spill
slot at all.

Work around these problems by ensuring there is a base or frame pointer
that can be used to access the emergency spill slot.

<rdar://problem/10917166>

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
bc2198133a1836598b54b943420748e75d5dea94 07-Feb-2012 Craig Topper <craig.topper@gmail.com> Convert assert(0) to llvm_unreachable

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd 07-Dec-2011 Evan Cheng <evan.cheng@apple.com> Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
29b9d7e4ea7521be25bccdb66ecd9c9df5ed8b4b 10-Oct-2011 Chad Rosier <mcrosier@apple.com> Fix a regression from r138445. If we're loading from the frame/base pointer
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5b81584f7403ffdb9cc6babaaeb0411c080e0f81 24-Aug-2011 Jim Grosbach <grosbach@apple.com> Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.

Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
4372ca6fe4119d708d43d9c9ac3feafc7607952a 17-Aug-2011 Jim Grosbach <grosbach@apple.com> 80 columns.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
8884148b8e8f19d5484e735618cf188cfa02c626 17-Aug-2011 Jim Grosbach <grosbach@apple.com> Tidy up.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1f6a329f79b3568d379142f921f59c4143ddaa14 12-Aug-2011 Duncan Sands <baldrick@free.fr> Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ee04a6d3a40c3017124e3fd89a0db473a2824498 21-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
2d28617de2b0b731c08d1af9e830f31e14ac75b4 19-Jul-2011 Evan Cheng <evan.cheng@apple.com> Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 01-Jul-2011 Jim Grosbach <grosbach@apple.com> Refact ARM Thumb1 tMOVr instruction family.

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
63b46faeb8acae9b7e5f865b7417dc00b9b9dad3 01-Jul-2011 Jim Grosbach <grosbach@apple.com> Thumb1 register to register MOV instruction is predicable.

Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
74472b4bf963c424da04f42dffdb94c85ef964bc 29-Jun-2011 Jim Grosbach <grosbach@apple.com> Refactor away tSpill and tRestore pseudos in ARM backend.

The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.



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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
fa226bccaa90c520cac154df74069bbabb976eab 02-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Use TRI::has{Sub,Super}ClassEq() where possible.

No functional change.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
c9e5015dece0a1a73bec358e11bc87594831279d 26-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.

The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
0d062c1e14af5653bb6a4719b06f168e2dc0f5db 18-Apr-2011 Jim Grosbach <grosbach@apple.com> Trim a few unneeded includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1db952d0c6c93f24619af5de2ea1b0550665479c 01-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Provide a legal pointer register class when targeting thumb1.

The LocalStackSlotAllocation pass was creating illegal registers.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b3fcc06d2124f9d01e3b48097b44cc141309908e 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
3daccd82d3151fa3629de430b55698a81084fc9e 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
57caad7a33ff145b71545f10dcfbbf2fd0f595d3 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5f3e2be7c941b26ac865fa00c3f314bcd1e6cec8 13-Jan-2011 Jim Grosbach <grosbach@apple.com> When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly
set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
16c29b5f285f375be53dabaa73e3e91107485fe4 10-Jan-2011 Anton Korobeynikov <asl@math.spbu.ru> Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
6e90ce21cc2b0627ee9219e3fb0cf808f2b73328 21-Dec-2010 Eric Christopher <echristo@apple.com> If we're not using reg+reg offset we're using reg+imm, set the opcode
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.

Fixes part of rdar://8782207


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5a54516adf2b15fa337445d327ec3ad9bd1e3648 16-Dec-2010 Bill Wendling <isanbard@gmail.com> Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
3e333637f172c30adf5c8333b592fbde17ff9f78 16-Dec-2010 Jim Grosbach <grosbach@apple.com> Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
7a905a82f7425d1a10b828c8bb3365b2ebc15833 16-Dec-2010 Bill Wendling <isanbard@gmail.com> If we're changing the frame register to a physical register other than SP, we
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
f4caf69720d807573c50d41aa06bcec1c99bdbbd 14-Dec-2010 Bill Wendling <isanbard@gmail.com> The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
7920d96964d707a3af85332c98d95b2fabc3d5c9 19-Nov-2010 Benjamin Kramer <benny.kra@googlemail.com> Avoid release build warnings.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
d0c38176690e9602a93a20a43f1bd084564a8116 18-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move hasFP() and few related hooks to TargetFrameInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
33464912237efaa0ed7060829e66b59055bdd48b 15-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ab3d00e5350fd4c097e2a5b077da7584692029a7 02-Nov-2010 Jim Grosbach <grosbach@apple.com> Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e4ad387a5a88dae20f0f7578e55170bbc8eee2a9 20-Oct-2010 Jim Grosbach <grosbach@apple.com> Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1dc335a79f5e899aacc6710dfe08ef20abb6a6c0 20-Sep-2010 Jim Grosbach <grosbach@apple.com> Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12

rdar://8445635



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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
65482b1bb873dd820f54a24a2f34bd65f2669e5c 03-Sep-2010 Jim Grosbach <grosbach@apple.com> Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6 03-Sep-2010 Daniel Dunbar <daniel@zuster.org> Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.

This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1755b3964f931bdd6fa9b4c0138f666ccfa12aca 03-Sep-2010 Jim Grosbach <grosbach@apple.com> For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a 27-Aug-2010 Jim Grosbach <grosbach@apple.com> Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890

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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
74d7b0af58951dce2f874c600a6a48a2454b4914 19-Aug-2010 Jim Grosbach <grosbach@apple.com> Add Thumb1 support for virtual frame indices.

rdar://8277890



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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ac096808a3accc516ae7c193c9a2c1392bf3301a 10-Aug-2010 Evan Cheng <evan.cheng@apple.com> Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.

Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


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/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
4bd828f78139b9bab561102c5b9c40133ad375ca 10-Aug-2010 Daniel Dunbar <daniel@zuster.org> Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
c9aed19747608b7688a64f2f382a008889f8e57d 10-Aug-2010 Evan Cheng <evan.cheng@apple.com> Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
72852a8cfb605056d87b644d2e36b1346051413d 20-Jul-2010 Eric Christopher <echristo@apple.com> Constify some arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
d6d7abaf4ebbabb850aa9c20e1617f897608fe62 11-Jul-2010 Rafael Espindola <rafael.espindola@gmail.com> Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
077f1bfa91953eb2378fca9b5ae91b08a2fc17bd 29-Jun-2010 Jim Grosbach <grosbach@apple.com> skip dbg_value instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
6e62b4ef14bf96e84962171dd3f115a7f8c6dc49 04-May-2010 Jim Grosbach <grosbach@apple.com> rdar://7937137 - dbg values not being handled in thumb1 version of
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
8c407d45964fbba19719be555324f247e4fb14e1 15-Apr-2010 Dan Gohman <gohman@apple.com> ReuseFrameIndexVals is used in multiple files, so it can't be static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
46510a73e977273ec67747eb34cbdb43f815e451 15-Apr-2010 Dan Gohman <gohman@apple.com> Add const qualifiers to CodeGen's use of LLVM IR constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
c7f3ace20c325521c68335a1689645b43b06ddf0 02-Apr-2010 Chris Lattner <sabre@nondot.org> use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
815baebe1c8dc02accf128ae10dff9a1742d3244 13-Mar-2010 Bob Wilson <bob.wilson@apple.com> Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
004453e85e72a2a2ea9a70fc6b7b368feb877c4c 10-Mar-2010 Jim Grosbach <grosbach@apple.com> comment why we use custom epilogue for t1 functions using vaargs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
7c617b5e53987d786451dd668b5113f2e2b983f8 10-Mar-2010 Jim Grosbach <grosbach@apple.com> Clear up the last (famous last words) frame index value reuse issues for Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 09-Mar-2010 Jim Grosbach <grosbach@apple.com> Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
4e501545cd12d903d35096f42eb5fdbe4603d5da 09-Mar-2010 Jim Grosbach <grosbach@apple.com> scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e68bd742451aae5fcdf280e823d2829e11d184da 06-Mar-2010 Jim Grosbach <grosbach@apple.com> Thumb1 epilogue code generation needs to take into account that callee-saved
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5f366af2ff36cc65fe4964194b07bf1455828ff0 24-Feb-2010 Jim Grosbach <grosbach@apple.com> handle very large call frames when require SPAdj != 0 for Thumb1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
35f0febcb66b5a50a5a750efcbefc95f7fc25c7b 19-Jan-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove predicates when changing an add into an unpredicable mov.

Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
7896c9f436a4eda5ec15e882a7505ba482a2fcd0 03-Dec-2009 Chris Lattner <sabre@nondot.org> improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 09-Nov-2009 Jim Grosbach <grosbach@apple.com> Use Unified Assembly Syntax for the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
31c24bf5b39cc8391d4cfdbf8cf5163975fdb81e 07-Nov-2009 Jim Grosbach <grosbach@apple.com> 80-column cleanup of file header comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1e 28-Oct-2009 Jim Grosbach <grosbach@apple.com> Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
62d1723a9cbce2019aac862f51952a58146a6bf0 22-Oct-2009 Evan Cheng <evan.cheng@apple.com> Trim more includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
41fff8c19ab6d8e28f5362481c184ad628f8c704 22-Oct-2009 Jim Grosbach <grosbach@apple.com> Missing piece of the ARM frame index post-scavenging conditionalization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
8fa4efeabf705cfc217eb88a67e7398691c76ade 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
functions are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
6009751244909c277e6cee8e74a4ccf1846953bc 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable allocation of R3 in Thumb1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
d482f55af135081aee7f7ab972bb8973f189c88f 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1f30dcbd8dcf18cabb4be780fcf492869d5dcab9 08-Oct-2009 Jim Grosbach <grosbach@apple.com> Cleanup up unused R3LiveIn tracking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
65c58daa8b8985d2116216043103009815a55e77 08-Oct-2009 Jim Grosbach <grosbach@apple.com> Re-enable register scavenging in Thumb1 by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
9f3a559dff691bc1ed85089cb0870cf30a4a2d96 08-Oct-2009 Jim Grosbach <grosbach@apple.com> reverting thumb1 scavenging default due to test failure while I figure out what's up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ec1434dd8970f9bcd410ef6ffaa2d440995cb18b 08-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable thumb1 register scavenging by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b58f498f7502e7e1833decbbbb4df771367c7341 07-Oct-2009 Jim Grosbach <grosbach@apple.com> Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
540b05d227a79443b2a7b07d5152a35cb6392abf 06-Oct-2009 Jim Grosbach <grosbach@apple.com> In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
10469f8e48e007989b0469e677d4000a1311ecd2 01-Oct-2009 Evan Cheng <evan.cheng@apple.com> ARM::tPOP and tPOP_RET each has an extra writeback operand now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
3d6cb88a64fe67064de206405951eb326d86fc0c 25-Sep-2009 Jim Grosbach <grosbach@apple.com> Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b7c5bdf843419e4222770475c27932c4c8e5c303 06-Sep-2009 Duncan Sands <baldrick@free.fr> Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
1d0be15f89cb5056e20e2d24faa8d6afb1573bca 13-Aug-2009 Owen Anderson <resistor@mac.com> Push LLVMContexts through the IntegerType APIs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
4b322e58b77d16f103d88a3af3a4ebd2675245a0 11-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrinkify Thumb2 load / store multiple instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
764ab52dd80310a205c9888bf166d09dab858f90 11-Aug-2009 Jim Grosbach <grosbach@apple.com> Whitespace cleanup. Remove trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e50ed30282bb5b4a9ed952580523f2dda16215ac 11-Aug-2009 Owen Anderson <resistor@mac.com> Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
bae20a6353583089224b94280a2dd69805dca247 28-Jul-2009 Evan Cheng <evan.cheng@apple.com> tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
6495f63945e8dbde81f03a1dc2ab421993b9a495 28-Jul-2009 Evan Cheng <evan.cheng@apple.com> - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
d83360694a6d82772cf31a0be8a64570c2e5cb88 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
30b2bdfa734d59bb7bc769dc2f06e4900a77f6f8 26-Jul-2009 Evan Cheng <evan.cheng@apple.com> Refactor. Get rid of a few more getOpcode() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
eed707b1e6097aac2bb6b3d47271f6300ace7f2e 25-Jul-2009 Owen Anderson <resistor@mac.com> Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
5ff58b5c3ab6df332600678798ea5c69c5e943d3 24-Jul-2009 David Goodwin <david_goodwin@apple.com> Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
e922c0201916e0b980ab3cfe91e1413e68d55647 22-Jul-2009 Owen Anderson <resistor@mac.com> Get rid of the Pass+Context magic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
f6fe9579505be86420beea04f2c9ecb0fd7c55fd 20-Jul-2009 Evan Cheng <evan.cheng@apple.com> Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b46aaa3874d2753632c48400c66be1a10ac18d42 19-Jul-2009 Evan Cheng <evan.cheng@apple.com> Fix a regression from 76124. Thumb1 instructions default to S bit being true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcf 17-Jul-2009 Anton Korobeynikov <asl@math.spbu.ru> Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
378445303b10b092a898a75131141a8259cff50b 16-Jul-2009 Evan Cheng <evan.cheng@apple.com> Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
9adc0abad3c3ed40a268ccbcee0c74cb9e1359fe 15-Jul-2009 Owen Anderson <resistor@mac.com> Move EVER MORE stuff over to LLVMContext.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
446c428bf394b7113b0f18cbacb5e87b4efd1e14 11-Jul-2009 Evan Cheng <evan.cheng@apple.com> Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.

A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
dac237e18209b697a8ba122d0ddd9cad4dfba1f8 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
77521f5232e679aa3de10aaaed2464aa91d7ff55 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Generalize opcode selection in ARMBaseRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
db5a71a8e01ed9a0d93a19176df6ea0aea510d7b 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Push methods into base class in preparation for sharing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
ab7c09b6b6f4516a631fd6788918c237c83939af 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
b50ea5c48f8b1ce259e034ca5c16dc14af1a582c 03-Jul-2009 David Goodwin <david_goodwin@apple.com> Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp