Thumb1RegisterInfo.cpp revision 8fa4efeabf705cfc217eb88a67e7398691c76ade
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Thumb-1 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMMachineFunctionInfo.h" 18#include "ARMSubtarget.h" 19#include "Thumb1InstrInfo.h" 20#include "Thumb1RegisterInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Target/TargetFrameInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/ADT/BitVector.h" 34#include "llvm/ADT/SmallVector.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38using namespace llvm; 39 40Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, 41 const ARMSubtarget &sti) 42 : ARMBaseRegisterInfo(tii, sti) { 43} 44 45/// emitLoadConstPool - Emits a load from constpool to materialize the 46/// specified immediate. 47void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, 48 MachineBasicBlock::iterator &MBBI, 49 DebugLoc dl, 50 unsigned DestReg, unsigned SubIdx, 51 int Val, 52 ARMCC::CondCodes Pred, 53 unsigned PredReg) const { 54 MachineFunction &MF = *MBB.getParent(); 55 MachineConstantPool *ConstantPool = MF.getConstantPool(); 56 Constant *C = ConstantInt::get( 57 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); 58 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 59 60 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp)) 61 .addReg(DestReg, getDefRegState(true), SubIdx) 62 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg); 63} 64 65const TargetRegisterClass* 66Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const { 67 if (isARMLowRegister(Reg)) 68 return ARM::tGPRRegisterClass; 69 switch (Reg) { 70 default: 71 break; 72 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 73 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC: 74 return ARM::GPRRegisterClass; 75 } 76 77 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT); 78} 79 80bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 81 const MachineFrameInfo *FFI = MF.getFrameInfo(); 82 unsigned CFSize = FFI->getMaxCallFrameSize(); 83 // It's not always a good idea to include the call frame as part of the 84 // stack frame. ARM (especially Thumb) has small immediate offset to 85 // address the stack frame. So a large call frame can cause poor codegen 86 // and may even makes it impossible to scavenge a register. 87 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 88 return false; 89 90 return !MF.getFrameInfo()->hasVarSizedObjects(); 91} 92 93 94/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 95/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 96/// in a register using mov / mvn sequences or load the immediate from a 97/// constpool entry. 98static 99void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 100 MachineBasicBlock::iterator &MBBI, 101 unsigned DestReg, unsigned BaseReg, 102 int NumBytes, bool CanChangeCC, 103 const TargetInstrInfo &TII, 104 const Thumb1RegisterInfo& MRI, 105 DebugLoc dl) { 106 MachineFunction &MF = *MBB.getParent(); 107 bool isHigh = !isARMLowRegister(DestReg) || 108 (BaseReg != 0 && !isARMLowRegister(BaseReg)); 109 bool isSub = false; 110 // Subtract doesn't have high register version. Load the negative value 111 // if either base or dest register is a high register. Also, if do not 112 // issue sub as part of the sequence if condition register is to be 113 // preserved. 114 if (NumBytes < 0 && !isHigh && CanChangeCC) { 115 isSub = true; 116 NumBytes = -NumBytes; 117 } 118 unsigned LdReg = DestReg; 119 if (DestReg == ARM::SP) { 120 assert(BaseReg == ARM::SP && "Unexpected!"); 121 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); 122 } 123 124 if (NumBytes <= 255 && NumBytes >= 0) 125 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 126 .addImm(NumBytes); 127 else if (NumBytes < 0 && NumBytes >= -255) { 128 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 129 .addImm(NumBytes); 130 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) 131 .addReg(LdReg, RegState::Kill); 132 } else 133 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes); 134 135 // Emit add / sub. 136 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 137 MachineInstrBuilder MIB = 138 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 139 if (Opc != ARM::tADDhirr) 140 MIB = AddDefaultT1CC(MIB); 141 if (DestReg == ARM::SP || isSub) 142 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 143 else 144 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 145 AddDefaultPred(MIB); 146} 147 148/// calcNumMI - Returns the number of instructions required to materialize 149/// the specific add / sub r, c instruction. 150static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 151 unsigned NumBits, unsigned Scale) { 152 unsigned NumMIs = 0; 153 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 154 155 if (Opc == ARM::tADDrSPi) { 156 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 157 Bytes -= ThisVal; 158 NumMIs++; 159 NumBits = 8; 160 Scale = 1; // Followed by a number of tADDi8. 161 Chunk = ((1 << NumBits) - 1) * Scale; 162 } 163 164 NumMIs += Bytes / Chunk; 165 if ((Bytes % Chunk) != 0) 166 NumMIs++; 167 if (ExtraOpc) 168 NumMIs++; 169 return NumMIs; 170} 171 172/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 173/// a destreg = basereg + immediate in Thumb code. 174static 175void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 176 MachineBasicBlock::iterator &MBBI, 177 unsigned DestReg, unsigned BaseReg, 178 int NumBytes, const TargetInstrInfo &TII, 179 const Thumb1RegisterInfo& MRI, 180 DebugLoc dl) { 181 bool isSub = NumBytes < 0; 182 unsigned Bytes = (unsigned)NumBytes; 183 if (isSub) Bytes = -NumBytes; 184 bool isMul4 = (Bytes & 3) == 0; 185 bool isTwoAddr = false; 186 bool DstNotEqBase = false; 187 unsigned NumBits = 1; 188 unsigned Scale = 1; 189 int Opc = 0; 190 int ExtraOpc = 0; 191 bool NeedCC = false; 192 bool NeedPred = false; 193 194 if (DestReg == BaseReg && BaseReg == ARM::SP) { 195 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 196 NumBits = 7; 197 Scale = 4; 198 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 199 isTwoAddr = true; 200 } else if (!isSub && BaseReg == ARM::SP) { 201 // r1 = add sp, 403 202 // => 203 // r1 = add sp, 100 * 4 204 // r1 = add r1, 3 205 if (!isMul4) { 206 Bytes &= ~3; 207 ExtraOpc = ARM::tADDi3; 208 } 209 NumBits = 8; 210 Scale = 4; 211 Opc = ARM::tADDrSPi; 212 } else { 213 // sp = sub sp, c 214 // r1 = sub sp, c 215 // r8 = sub sp, c 216 if (DestReg != BaseReg) 217 DstNotEqBase = true; 218 NumBits = 8; 219 if (DestReg == ARM::SP) { 220 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 221 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 222 NumBits = 7; 223 Scale = 4; 224 } else { 225 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 226 NumBits = 8; 227 NeedPred = NeedCC = true; 228 } 229 isTwoAddr = true; 230 } 231 232 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 233 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 234 if (NumMIs > Threshold) { 235 // This will expand into too many instructions. Load the immediate from a 236 // constpool entry. 237 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, 238 MRI, dl); 239 return; 240 } 241 242 if (DstNotEqBase) { 243 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) { 244 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 245 unsigned Chunk = (1 << 3) - 1; 246 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 247 Bytes -= ThisVal; 248 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); 249 const MachineInstrBuilder MIB = 250 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg)); 251 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 252 } else { 253 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) 254 .addReg(BaseReg, RegState::Kill); 255 } 256 BaseReg = DestReg; 257 } 258 259 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 260 while (Bytes) { 261 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 262 Bytes -= ThisVal; 263 ThisVal /= Scale; 264 // Build the new tADD / tSUB. 265 if (isTwoAddr) { 266 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 267 if (NeedCC) 268 MIB = AddDefaultT1CC(MIB); 269 MIB .addReg(DestReg).addImm(ThisVal); 270 if (NeedPred) 271 MIB = AddDefaultPred(MIB); 272 } 273 else { 274 bool isKill = BaseReg != ARM::SP; 275 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 276 if (NeedCC) 277 MIB = AddDefaultT1CC(MIB); 278 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); 279 if (NeedPred) 280 MIB = AddDefaultPred(MIB); 281 BaseReg = DestReg; 282 283 if (Opc == ARM::tADDrSPi) { 284 // r4 = add sp, imm 285 // r4 = add r4, imm 286 // ... 287 NumBits = 8; 288 Scale = 1; 289 Chunk = ((1 << NumBits) - 1) * Scale; 290 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 291 NeedPred = NeedCC = isTwoAddr = true; 292 } 293 } 294 } 295 296 if (ExtraOpc) { 297 const TargetInstrDesc &TID = TII.get(ExtraOpc); 298 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg)) 299 .addReg(DestReg, RegState::Kill) 300 .addImm(((unsigned)NumBytes) & 3)); 301 } 302} 303 304static void emitSPUpdate(MachineBasicBlock &MBB, 305 MachineBasicBlock::iterator &MBBI, 306 const TargetInstrInfo &TII, DebugLoc dl, 307 const Thumb1RegisterInfo &MRI, 308 int NumBytes) { 309 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, 310 MRI, dl); 311} 312 313void Thumb1RegisterInfo:: 314eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 315 MachineBasicBlock::iterator I) const { 316 if (!hasReservedCallFrame(MF)) { 317 // If we have alloca, convert as follows: 318 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 319 // ADJCALLSTACKUP -> add, sp, sp, amount 320 MachineInstr *Old = I; 321 DebugLoc dl = Old->getDebugLoc(); 322 unsigned Amount = Old->getOperand(0).getImm(); 323 if (Amount != 0) { 324 // We need to keep the stack aligned properly. To do this, we round the 325 // amount of space needed for the outgoing arguments up to the next 326 // alignment boundary. 327 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 328 Amount = (Amount+Align-1)/Align*Align; 329 330 // Replace the pseudo instruction with a new instruction... 331 unsigned Opc = Old->getOpcode(); 332 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 333 emitSPUpdate(MBB, I, TII, dl, *this, -Amount); 334 } else { 335 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 336 emitSPUpdate(MBB, I, TII, dl, *this, Amount); 337 } 338 } 339 } 340 MBB.erase(I); 341} 342 343/// emitThumbConstant - Emit a series of instructions to materialize a 344/// constant. 345static void emitThumbConstant(MachineBasicBlock &MBB, 346 MachineBasicBlock::iterator &MBBI, 347 unsigned DestReg, int Imm, 348 const TargetInstrInfo &TII, 349 const Thumb1RegisterInfo& MRI, 350 DebugLoc dl) { 351 bool isSub = Imm < 0; 352 if (isSub) Imm = -Imm; 353 354 int Chunk = (1 << 8) - 1; 355 int ThisVal = (Imm > Chunk) ? Chunk : Imm; 356 Imm -= ThisVal; 357 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), 358 DestReg)) 359 .addImm(ThisVal)); 360 if (Imm > 0) 361 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); 362 if (isSub) { 363 const TargetInstrDesc &TID = TII.get(ARM::tRSB); 364 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg)) 365 .addReg(DestReg, RegState::Kill)); 366 } 367} 368 369static void removeOperands(MachineInstr &MI, unsigned i) { 370 unsigned Op = i; 371 for (unsigned e = MI.getNumOperands(); i != e; ++i) 372 MI.RemoveOperand(Op); 373} 374 375int Thumb1RegisterInfo:: 376rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 377 unsigned FrameReg, int Offset, 378 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const 379{ 380 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo 381 // version then can pull out Thumb1 specific parts here 382 return 0; 383} 384 385/// saveScavengerRegister - Spill the register so it can be used by the 386/// register scavenger. Return true. 387bool 388Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator I, 390 MachineBasicBlock::iterator &UseMI, 391 const TargetRegisterClass *RC, 392 unsigned Reg) const { 393 // Thumb1 can't use the emergency spill slot on the stack because 394 // ldr/str immediate offsets must be positive, and if we're referencing 395 // off the frame pointer (if, for example, there are alloca() calls in 396 // the function, the offset will be negative. Use R12 instead since that's 397 // a call clobbered register that we know won't be used in Thumb1 mode. 398 DebugLoc DL = DebugLoc::getUnknownLoc(); 399 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)). 400 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill); 401 402 // The UseMI is where we would like to restore the register. If there's 403 // interference with R12 before then, however, we'll need to restore it 404 // before that instead and adjust the UseMI. 405 bool done = false; 406 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { 407 // If this instruction affects R12, adjust our restore point. 408 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { 409 const MachineOperand &MO = II->getOperand(i); 410 if (!MO.isReg() || MO.isUndef() || !MO.getReg() || 411 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 412 continue; 413 if (MO.getReg() == ARM::R12) { 414 UseMI = II; 415 done = true; 416 break; 417 } 418 } 419 } 420 // Restore the register from R12 421 BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)). 422 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill); 423 424 return true; 425} 426 427unsigned 428Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 429 int SPAdj, int *Value, 430 RegScavenger *RS) const{ 431 unsigned VReg = 0; 432 unsigned i = 0; 433 MachineInstr &MI = *II; 434 MachineBasicBlock &MBB = *MI.getParent(); 435 MachineFunction &MF = *MBB.getParent(); 436 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 437 DebugLoc dl = MI.getDebugLoc(); 438 439 while (!MI.getOperand(i).isFI()) { 440 ++i; 441 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 442 } 443 444 unsigned FrameReg = ARM::SP; 445 int FrameIndex = MI.getOperand(i).getIndex(); 446 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 447 MF.getFrameInfo()->getStackSize() + SPAdj; 448 449 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 450 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 451 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 452 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 453 else if (hasFP(MF)) { 454 assert(SPAdj == 0 && "Unexpected"); 455 // There is alloca()'s in this function, must reference off the frame 456 // pointer instead. 457 FrameReg = getFrameRegister(MF); 458 Offset -= AFI->getFramePtrSpillOffset(); 459 } 460 461 unsigned Opcode = MI.getOpcode(); 462 const TargetInstrDesc &Desc = MI.getDesc(); 463 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 464 465 if (Opcode == ARM::tADDrSPi) { 466 Offset += MI.getOperand(i+1).getImm(); 467 468 // Can't use tADDrSPi if it's based off the frame pointer. 469 unsigned NumBits = 0; 470 unsigned Scale = 1; 471 if (FrameReg != ARM::SP) { 472 Opcode = ARM::tADDi3; 473 MI.setDesc(TII.get(Opcode)); 474 NumBits = 3; 475 } else { 476 NumBits = 8; 477 Scale = 4; 478 assert((Offset & 3) == 0 && 479 "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 480 } 481 482 if (Offset == 0) { 483 // Turn it into a move. 484 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr)); 485 MI.getOperand(i).ChangeToRegister(FrameReg, false); 486 MI.RemoveOperand(i+1); 487 return 0; 488 } 489 490 // Common case: small offset, fits into instruction. 491 unsigned Mask = (1 << NumBits) - 1; 492 if (((Offset / Scale) & ~Mask) == 0) { 493 // Replace the FrameIndex with sp / fp 494 if (Opcode == ARM::tADDi3) { 495 removeOperands(MI, i); 496 MachineInstrBuilder MIB(&MI); 497 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg) 498 .addImm(Offset / Scale)); 499 } else { 500 MI.getOperand(i).ChangeToRegister(FrameReg, false); 501 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 502 } 503 return 0; 504 } 505 506 unsigned DestReg = MI.getOperand(0).getReg(); 507 unsigned Bytes = (Offset > 0) ? Offset : -Offset; 508 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 509 // MI would expand into a large number of instructions. Don't try to 510 // simplify the immediate. 511 if (NumMIs > 2) { 512 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, 513 *this, dl); 514 MBB.erase(II); 515 return 0; 516 } 517 518 if (Offset > 0) { 519 // Translate r0 = add sp, imm to 520 // r0 = add sp, 255*4 521 // r0 = add r0, (imm - 255*4) 522 if (Opcode == ARM::tADDi3) { 523 removeOperands(MI, i); 524 MachineInstrBuilder MIB(&MI); 525 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask)); 526 } else { 527 MI.getOperand(i).ChangeToRegister(FrameReg, false); 528 MI.getOperand(i+1).ChangeToImmediate(Mask); 529 } 530 Offset = (Offset - Mask * Scale); 531 MachineBasicBlock::iterator NII = next(II); 532 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, 533 *this, dl); 534 } else { 535 // Translate r0 = add sp, -imm to 536 // r0 = -imm (this is then translated into a series of instructons) 537 // r0 = add r0, sp 538 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); 539 540 MI.setDesc(TII.get(ARM::tADDhirr)); 541 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 542 MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 543 if (Opcode == ARM::tADDi3) { 544 MachineInstrBuilder MIB(&MI); 545 AddDefaultPred(MIB); 546 } 547 } 548 return 0; 549 } else { 550 unsigned ImmIdx = 0; 551 int InstrOffs = 0; 552 unsigned NumBits = 0; 553 unsigned Scale = 1; 554 switch (AddrMode) { 555 case ARMII::AddrModeT1_s: { 556 ImmIdx = i+1; 557 InstrOffs = MI.getOperand(ImmIdx).getImm(); 558 NumBits = (FrameReg == ARM::SP) ? 8 : 5; 559 Scale = 4; 560 break; 561 } 562 default: 563 llvm_unreachable("Unsupported addressing mode!"); 564 break; 565 } 566 567 Offset += InstrOffs * Scale; 568 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 569 570 // Common case: small offset, fits into instruction. 571 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 572 int ImmedOffset = Offset / Scale; 573 unsigned Mask = (1 << NumBits) - 1; 574 if ((unsigned)Offset <= Mask * Scale) { 575 // Replace the FrameIndex with sp 576 MI.getOperand(i).ChangeToRegister(FrameReg, false); 577 ImmOp.ChangeToImmediate(ImmedOffset); 578 return 0; 579 } 580 581 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 582 if (AddrMode == ARMII::AddrModeT1_s) { 583 // Thumb tLDRspi, tSTRspi. These will change to instructions that use 584 // a different base register. 585 NumBits = 5; 586 Mask = (1 << NumBits) - 1; 587 } 588 // If this is a thumb spill / restore, we will be using a constpool load to 589 // materialize the offset. 590 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore) 591 ImmOp.ChangeToImmediate(0); 592 else { 593 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 594 ImmedOffset = ImmedOffset & Mask; 595 ImmOp.ChangeToImmediate(ImmedOffset); 596 Offset &= ~(Mask*Scale); 597 } 598 } 599 600 // If we get here, the immediate doesn't fit into the instruction. We folded 601 // as much as possible above, handle the rest, providing a register that is 602 // SP+LargeImm. 603 assert(Offset && "This code isn't needed if offset already handled!"); 604 605 // Remove predicate first. 606 int PIdx = MI.findFirstPredOperandIdx(); 607 if (PIdx != -1) 608 removeOperands(MI, PIdx); 609 610 if (Desc.mayLoad()) { 611 // Use the destination register to materialize sp + offset. 612 unsigned TmpReg = MI.getOperand(0).getReg(); 613 bool UseRR = false; 614 if (Opcode == ARM::tRestore) { 615 if (FrameReg == ARM::SP) 616 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, 617 Offset, false, TII, *this, dl); 618 else { 619 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); 620 UseRR = true; 621 } 622 } else { 623 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, 624 *this, dl); 625 } 626 627 MI.setDesc(TII.get(ARM::tLDR)); 628 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 629 if (UseRR) 630 // Use [reg, reg] addrmode. 631 MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); 632 else // tLDR has an extra register operand. 633 MI.addOperand(MachineOperand::CreateReg(0, false)); 634 } else if (Desc.mayStore()) { 635 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); 636 assert (Value && "Frame index virtual allocated, but Value arg is NULL!"); 637 *Value = Offset; 638 bool UseRR = false; 639 640 if (Opcode == ARM::tSpill) { 641 if (FrameReg == ARM::SP) 642 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg, 643 Offset, false, TII, *this, dl); 644 else { 645 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); 646 UseRR = true; 647 } 648 } else 649 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII, 650 *this, dl); 651 MI.setDesc(TII.get(ARM::tSTR)); 652 MI.getOperand(i).ChangeToRegister(VReg, false, false, true); 653 if (UseRR) // Use [reg, reg] addrmode. 654 MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); 655 else // tSTR has an extra register operand. 656 MI.addOperand(MachineOperand::CreateReg(0, false)); 657 } else 658 assert(false && "Unexpected opcode!"); 659 660 // Add predicate back if it's needed. 661 if (MI.getDesc().isPredicable()) { 662 MachineInstrBuilder MIB(&MI); 663 AddDefaultPred(MIB); 664 } 665 return VReg; 666} 667 668void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const { 669 MachineBasicBlock &MBB = MF.front(); 670 MachineBasicBlock::iterator MBBI = MBB.begin(); 671 MachineFrameInfo *MFI = MF.getFrameInfo(); 672 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 673 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 674 unsigned NumBytes = MFI->getStackSize(); 675 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 676 DebugLoc dl = (MBBI != MBB.end() ? 677 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 678 679 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 680 NumBytes = (NumBytes + 3) & ~3; 681 MFI->setStackSize(NumBytes); 682 683 // Determine the sizes of each callee-save spill areas and record which frame 684 // belongs to which callee-save spill areas. 685 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 686 int FramePtrSpillFI = 0; 687 688 if (VARegSaveSize) 689 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize); 690 691 if (!AFI->hasStackFrame()) { 692 if (NumBytes != 0) 693 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes); 694 return; 695 } 696 697 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 698 unsigned Reg = CSI[i].getReg(); 699 int FI = CSI[i].getFrameIdx(); 700 switch (Reg) { 701 case ARM::R4: 702 case ARM::R5: 703 case ARM::R6: 704 case ARM::R7: 705 case ARM::LR: 706 if (Reg == FramePtr) 707 FramePtrSpillFI = FI; 708 AFI->addGPRCalleeSavedArea1Frame(FI); 709 GPRCS1Size += 4; 710 break; 711 case ARM::R8: 712 case ARM::R9: 713 case ARM::R10: 714 case ARM::R11: 715 if (Reg == FramePtr) 716 FramePtrSpillFI = FI; 717 if (STI.isTargetDarwin()) { 718 AFI->addGPRCalleeSavedArea2Frame(FI); 719 GPRCS2Size += 4; 720 } else { 721 AFI->addGPRCalleeSavedArea1Frame(FI); 722 GPRCS1Size += 4; 723 } 724 break; 725 default: 726 AFI->addDPRCalleeSavedAreaFrame(FI); 727 DPRCSSize += 8; 728 } 729 } 730 731 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 732 ++MBBI; 733 if (MBBI != MBB.end()) 734 dl = MBBI->getDebugLoc(); 735 } 736 737 // Darwin ABI requires FP to point to the stack slot that contains the 738 // previous FP. 739 if (STI.isTargetDarwin() || hasFP(MF)) { 740 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 741 .addFrameIndex(FramePtrSpillFI).addImm(0); 742 } 743 744 // Determine starting offsets of spill areas. 745 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 746 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 747 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 748 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 749 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 750 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 751 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 752 753 NumBytes = DPRCSOffset; 754 if (NumBytes) { 755 // Insert it after all the callee-save spills. 756 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes); 757 } 758 759 if (STI.isTargetELF() && hasFP(MF)) { 760 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 761 AFI->getFramePtrSpillOffset()); 762 } 763 764 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 765 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 766 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 767} 768 769static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 770 for (unsigned i = 0; CSRegs[i]; ++i) 771 if (Reg == CSRegs[i]) 772 return true; 773 return false; 774} 775 776static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 777 return (MI->getOpcode() == ARM::tRestore && 778 MI->getOperand(1).isFI() && 779 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 780} 781 782void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF, 783 MachineBasicBlock &MBB) const { 784 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 785 assert((MBBI->getOpcode() == ARM::tBX_RET || 786 MBBI->getOpcode() == ARM::tPOP_RET) && 787 "Can only insert epilog into returning blocks"); 788 DebugLoc dl = MBBI->getDebugLoc(); 789 MachineFrameInfo *MFI = MF.getFrameInfo(); 790 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 791 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 792 int NumBytes = (int)MFI->getStackSize(); 793 794 if (!AFI->hasStackFrame()) { 795 if (NumBytes != 0) 796 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes); 797 } else { 798 // Unwind MBBI to point to first LDR / FLDD. 799 const unsigned *CSRegs = getCalleeSavedRegs(); 800 if (MBBI != MBB.begin()) { 801 do 802 --MBBI; 803 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 804 if (!isCSRestore(MBBI, CSRegs)) 805 ++MBBI; 806 } 807 808 // Move SP to start of FP callee save spill area. 809 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 810 AFI->getGPRCalleeSavedArea2Size() + 811 AFI->getDPRCalleeSavedAreaSize()); 812 813 if (hasFP(MF)) { 814 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 815 // Reset SP based on frame pointer only if the stack frame extends beyond 816 // frame pointer stack slot or target is ELF and the function has FP. 817 if (NumBytes) 818 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, 819 TII, *this, dl); 820 else 821 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 822 .addReg(FramePtr); 823 } else { 824 if (MBBI->getOpcode() == ARM::tBX_RET && 825 &MBB.front() != MBBI && 826 prior(MBBI)->getOpcode() == ARM::tPOP) { 827 MachineBasicBlock::iterator PMBBI = prior(MBBI); 828 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes); 829 } else 830 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes); 831 } 832 } 833 834 if (VARegSaveSize) { 835 // Epilogue for vararg functions: pop LR to R3 and branch off it. 836 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 837 .addReg(0) // No write back. 838 .addReg(ARM::R3, RegState::Define); 839 840 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize); 841 842 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) 843 .addReg(ARM::R3, RegState::Kill); 844 MBB.erase(MBBI); 845 } 846} 847