SPUISelDAGToDAG.cpp revision 574aab5700bde870a2fb1334b5bb82551b6b6bce 
1//===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a pattern matching instruction selector for the Cell SPU,
11// converting from a legalized dag to a SPU-target dag.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SPU.h"
16#include "SPUTargetMachine.h"
17#include "SPUHazardRecognizers.h"
18#include "SPUFrameInfo.h"
19#include "SPURegisterNames.h"
20#include "SPUTargetMachine.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/CodeGen/SelectionDAGISel.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/Target/TargetOptions.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/Constants.h"
30#include "llvm/GlobalValue.h"
31#include "llvm/Intrinsics.h"
32#include "llvm/LLVMContext.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/MathExtras.h"
36#include "llvm/Support/Compiler.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42  //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
43  bool
44  isI64IntS10Immediate(ConstantSDNode *CN)
45  {
46    return isInt<10>(CN->getSExtValue());
47  }
48
49  //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
50  bool
51  isI32IntS10Immediate(ConstantSDNode *CN)
52  {
53    return isInt<10>(CN->getSExtValue());
54  }
55
56  //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
57  bool
58  isI32IntU10Immediate(ConstantSDNode *CN)
59  {
60    return isUInt<10>(CN->getSExtValue());
61  }
62
63  //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
64  bool
65  isI16IntS10Immediate(ConstantSDNode *CN)
66  {
67    return isInt<10>(CN->getSExtValue());
68  }
69
70  //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
71  bool
72  isI16IntU10Immediate(ConstantSDNode *CN)
73  {
74    return isUInt<10>((short) CN->getZExtValue());
75  }
76
77  //! ConstantSDNode predicate for signed 16-bit values
78  /*!
79    \arg CN The constant SelectionDAG node holding the value
80    \arg Imm The returned 16-bit value, if returning true
81
82    This predicate tests the value in \a CN to see whether it can be
83    represented as a 16-bit, sign-extended quantity. Returns true if
84    this is the case.
85   */
86  bool
87  isIntS16Immediate(ConstantSDNode *CN, short &Imm)
88  {
89    EVT vt = CN->getValueType(0);
90    Imm = (short) CN->getZExtValue();
91    if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
92      return true;
93    } else if (vt == MVT::i32) {
94      int32_t i_val = (int32_t) CN->getZExtValue();
95      short s_val = (short) i_val;
96      return i_val == s_val;
97    } else {
98      int64_t i_val = (int64_t) CN->getZExtValue();
99      short s_val = (short) i_val;
100      return i_val == s_val;
101    }
102
103    return false;
104  }
105
106  //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
107  static bool
108  isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
109  {
110    EVT vt = FPN->getValueType(0);
111    if (vt == MVT::f32) {
112      int val = FloatToBits(FPN->getValueAPF().convertToFloat());
113      int sval = (int) ((val << 16) >> 16);
114      Imm = (short) val;
115      return val == sval;
116    }
117
118    return false;
119  }
120
121  //===------------------------------------------------------------------===//
122  //! EVT to "useful stuff" mapping structure:
123
124  struct valtype_map_s {
125    EVT VT;
126    unsigned ldresult_ins;      /// LDRESULT instruction (0 = undefined)
127    bool ldresult_imm;          /// LDRESULT instruction requires immediate?
128    unsigned lrinst;            /// LR instruction
129  };
130
131  const valtype_map_s valtype_map[] = {
132    { MVT::i8,    SPU::ORBIr8,  true,  SPU::LRr8 },
133    { MVT::i16,   SPU::ORHIr16, true,  SPU::LRr16 },
134    { MVT::i32,   SPU::ORIr32,  true,  SPU::LRr32 },
135    { MVT::i64,   SPU::ORr64,   false, SPU::LRr64 },
136    { MVT::f32,   SPU::ORf32,   false, SPU::LRf32 },
137    { MVT::f64,   SPU::ORf64,   false, SPU::LRf64 },
138    // vector types... (sigh!)
139    { MVT::v16i8, 0,            false, SPU::LRv16i8 },
140    { MVT::v8i16, 0,            false, SPU::LRv8i16 },
141    { MVT::v4i32, 0,            false, SPU::LRv4i32 },
142    { MVT::v2i64, 0,            false, SPU::LRv2i64 },
143    { MVT::v4f32, 0,            false, SPU::LRv4f32 },
144    { MVT::v2f64, 0,            false, SPU::LRv2f64 }
145  };
146
147  const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
148
149  const valtype_map_s *getValueTypeMapEntry(EVT VT)
150  {
151    const valtype_map_s *retval = 0;
152    for (size_t i = 0; i < n_valtype_map; ++i) {
153      if (valtype_map[i].VT == VT) {
154        retval = valtype_map + i;
155        break;
156      }
157    }
158
159
160#ifndef NDEBUG
161    if (retval == 0) {
162      report_fatal_error("SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns"
163                         "NULL for " + Twine(VT.getEVTString()));
164    }
165#endif
166
167    return retval;
168  }
169
170  //! Generate the carry-generate shuffle mask.
171  SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
172    SmallVector<SDValue, 16 > ShufBytes;
173
174    // Create the shuffle mask for "rotating" the borrow up one register slot
175    // once the borrow is generated.
176    ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
177    ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
178    ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
179    ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
180
181    return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
182                       &ShufBytes[0], ShufBytes.size());
183  }
184
185  //! Generate the borrow-generate shuffle mask
186  SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
187    SmallVector<SDValue, 16 > ShufBytes;
188
189    // Create the shuffle mask for "rotating" the borrow up one register slot
190    // once the borrow is generated.
191    ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
192    ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
193    ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
194    ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
195
196    return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
197                       &ShufBytes[0], ShufBytes.size());
198  }
199
200  //===------------------------------------------------------------------===//
201  /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
202  /// instructions for SelectionDAG operations.
203  ///
204  class SPUDAGToDAGISel :
205    public SelectionDAGISel
206  {
207    const SPUTargetMachine &TM;
208    const SPUTargetLowering &SPUtli;
209    unsigned GlobalBaseReg;
210
211  public:
212    explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
213      SelectionDAGISel(tm),
214      TM(tm),
215      SPUtli(*tm.getTargetLowering())
216    { }
217
218    virtual bool runOnMachineFunction(MachineFunction &MF) {
219      // Make sure we re-emit a set of the global base reg if necessary
220      GlobalBaseReg = 0;
221      SelectionDAGISel::runOnMachineFunction(MF);
222      return true;
223    }
224
225    /// getI32Imm - Return a target constant with the specified value, of type
226    /// i32.
227    inline SDValue getI32Imm(uint32_t Imm) {
228      return CurDAG->getTargetConstant(Imm, MVT::i32);
229    }
230
231    /// getI64Imm - Return a target constant with the specified value, of type
232    /// i64.
233    inline SDValue getI64Imm(uint64_t Imm) {
234      return CurDAG->getTargetConstant(Imm, MVT::i64);
235    }
236
237    /// getSmallIPtrImm - Return a target constant of pointer type.
238    inline SDValue getSmallIPtrImm(unsigned Imm) {
239      return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
240      }
241
242    SDNode *emitBuildVector(SDNode *bvNode) {
243      EVT vecVT = bvNode->getValueType(0);
244      DebugLoc dl = bvNode->getDebugLoc();
245
246      // Check to see if this vector can be represented as a CellSPU immediate
247      // constant by invoking all of the instruction selection predicates:
248      if (((vecVT == MVT::v8i16) &&
249           (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
250          ((vecVT == MVT::v4i32) &&
251           ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
252            (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
253            (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
254            (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
255          ((vecVT == MVT::v2i64) &&
256           ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
257            (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
258            (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
259        HandleSDNode Dummy(SDValue(bvNode, 0));
260        if (SDNode *N = Select(bvNode))
261          return N;
262        return Dummy.getValue().getNode();
263      }
264
265      // No, need to emit a constant pool spill:
266      std::vector<Constant*> CV;
267
268      for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
269        ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
270        CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
271      }
272
273      const Constant *CP = ConstantVector::get(CV);
274      SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
275      unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276      SDValue CGPoolOffset =
277              SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
278
279      HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
280                                         CurDAG->getEntryNode(), CGPoolOffset,
281                                         PseudoSourceValue::getConstantPool(),0,
282                                         false, false, Alignment));
283      CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
284      if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
285        return N;
286      return Dummy.getValue().getNode();
287    }
288
289    /// Select - Convert the specified operand from a target-independent to a
290    /// target-specific node if it hasn't already been changed.
291    SDNode *Select(SDNode *N);
292
293    //! Emit the instruction sequence for i64 shl
294    SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
295
296    //! Emit the instruction sequence for i64 srl
297    SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
298
299    //! Emit the instruction sequence for i64 sra
300    SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
301
302    //! Emit the necessary sequence for loading i64 constants:
303    SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
304
305    //! Alternate instruction emit sequence for loading i64 constants
306    SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
307
308    //! Returns true if the address N is an A-form (local store) address
309    bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
310                         SDValue &Index);
311
312    //! D-form address predicate
313    bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
314                         SDValue &Index);
315
316    /// Alternate D-form address using i7 offset predicate
317    bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
318                          SDValue &Base);
319
320    /// D-form address selection workhorse
321    bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
322                               SDValue &Base, int minOffset, int maxOffset);
323
324    //! Address predicate if N can be expressed as an indexed [r+r] operation.
325    bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
326                         SDValue &Index);
327
328    /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
329    /// inline asm expressions.
330    virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
331                                              char ConstraintCode,
332                                              std::vector<SDValue> &OutOps) {
333      SDValue Op0, Op1;
334      switch (ConstraintCode) {
335      default: return true;
336      case 'm':   // memory
337        if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
338            && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
339          SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
340        break;
341      case 'o':   // offsetable
342        if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
343            && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
344          Op0 = Op;
345          Op1 = getSmallIPtrImm(0);
346        }
347        break;
348      case 'v':   // not offsetable
349#if 1
350        llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
351#else
352        SelectAddrIdxOnly(Op, Op, Op0, Op1);
353#endif
354        break;
355      }
356
357      OutOps.push_back(Op0);
358      OutOps.push_back(Op1);
359      return false;
360    }
361
362    virtual const char *getPassName() const {
363      return "Cell SPU DAG->DAG Pattern Instruction Selection";
364    }
365
366    /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
367    /// this target when scheduling the DAG.
368    virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
369      const TargetInstrInfo *II = TM.getInstrInfo();
370      assert(II && "No InstrInfo?");
371      return new SPUHazardRecognizer(*II);
372    }
373
374    // Include the pieces autogenerated from the target description.
375#include "SPUGenDAGISel.inc"
376  };
377}
378
379/*!
380 \arg Op The ISD instruction operand
381 \arg N The address to be tested
382 \arg Base The base address
383 \arg Index The base address index
384 */
385bool
386SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
387                    SDValue &Index) {
388  // These match the addr256k operand type:
389  EVT OffsVT = MVT::i16;
390  SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
391
392  switch (N.getOpcode()) {
393  case ISD::Constant:
394  case ISD::ConstantPool:
395  case ISD::GlobalAddress:
396    report_fatal_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
397    /*NOTREACHED*/
398
399  case ISD::TargetConstant:
400  case ISD::TargetGlobalAddress:
401  case ISD::TargetJumpTable:
402    report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
403                      "not wrapped as A-form address.");
404    /*NOTREACHED*/
405
406  case SPUISD::AFormAddr:
407    // Just load from memory if there's only a single use of the location,
408    // otherwise, this will get handled below with D-form offset addresses
409    if (N.hasOneUse()) {
410      SDValue Op0 = N.getOperand(0);
411      switch (Op0.getOpcode()) {
412      case ISD::TargetConstantPool:
413      case ISD::TargetJumpTable:
414        Base = Op0;
415        Index = Zero;
416        return true;
417
418      case ISD::TargetGlobalAddress: {
419        GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
420        const GlobalValue *GV = GSDN->getGlobal();
421        if (GV->getAlignment() == 16) {
422          Base = Op0;
423          Index = Zero;
424          return true;
425        }
426        break;
427      }
428      }
429    }
430    break;
431  }
432  return false;
433}
434
435bool
436SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
437                                  SDValue &Base) {
438  const int minDForm2Offset = -(1 << 7);
439  const int maxDForm2Offset = (1 << 7) - 1;
440  return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
441                               maxDForm2Offset);
442}
443
444/*!
445  \arg Op The ISD instruction (ignored)
446  \arg N The address to be tested
447  \arg Base Base address register/pointer
448  \arg Index Base address index
449
450  Examine the input address by a base register plus a signed 10-bit
451  displacement, [r+I10] (D-form address).
452
453  \return true if \a N is a D-form address with \a Base and \a Index set
454  to non-empty SDValue instances.
455*/
456bool
457SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
458                                 SDValue &Index) {
459  return DFormAddressPredicate(Op, N, Base, Index,
460                               SPUFrameInfo::minFrameOffset(),
461                               SPUFrameInfo::maxFrameOffset());
462}
463
464bool
465SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
466                                      SDValue &Index, int minOffset,
467                                      int maxOffset) {
468  unsigned Opc = N.getOpcode();
469  EVT PtrTy = SPUtli.getPointerTy();
470
471  if (Opc == ISD::FrameIndex) {
472    // Stack frame index must be less than 512 (divided by 16):
473    FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
474    int FI = int(FIN->getIndex());
475    DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
476               << FI << "\n");
477    if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
478      Base = CurDAG->getTargetConstant(0, PtrTy);
479      Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
480      return true;
481    }
482  } else if (Opc == ISD::ADD) {
483    // Generated by getelementptr
484    const SDValue Op0 = N.getOperand(0);
485    const SDValue Op1 = N.getOperand(1);
486
487    if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
488        || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
489      Base = CurDAG->getTargetConstant(0, PtrTy);
490      Index = N;
491      return true;
492    } else if (Op1.getOpcode() == ISD::Constant
493               || Op1.getOpcode() == ISD::TargetConstant) {
494      ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
495      int32_t offset = int32_t(CN->getSExtValue());
496
497      if (Op0.getOpcode() == ISD::FrameIndex) {
498        FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
499        int FI = int(FIN->getIndex());
500        DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
501                   << " frame index = " << FI << "\n");
502
503        if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
504          Base = CurDAG->getTargetConstant(offset, PtrTy);
505          Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
506          return true;
507        }
508      } else if (offset > minOffset && offset < maxOffset) {
509        Base = CurDAG->getTargetConstant(offset, PtrTy);
510        Index = Op0;
511        return true;
512      }
513    } else if (Op0.getOpcode() == ISD::Constant
514               || Op0.getOpcode() == ISD::TargetConstant) {
515      ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
516      int32_t offset = int32_t(CN->getSExtValue());
517
518      if (Op1.getOpcode() == ISD::FrameIndex) {
519        FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
520        int FI = int(FIN->getIndex());
521        DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
522                   << " frame index = " << FI << "\n");
523
524        if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
525          Base = CurDAG->getTargetConstant(offset, PtrTy);
526          Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
527          return true;
528        }
529      } else if (offset > minOffset && offset < maxOffset) {
530        Base = CurDAG->getTargetConstant(offset, PtrTy);
531        Index = Op1;
532        return true;
533      }
534    }
535  } else if (Opc == SPUISD::IndirectAddr) {
536    // Indirect with constant offset -> D-Form address
537    const SDValue Op0 = N.getOperand(0);
538    const SDValue Op1 = N.getOperand(1);
539
540    if (Op0.getOpcode() == SPUISD::Hi
541        && Op1.getOpcode() == SPUISD::Lo) {
542      // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
543      Base = CurDAG->getTargetConstant(0, PtrTy);
544      Index = N;
545      return true;
546    } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
547      int32_t offset = 0;
548      SDValue idxOp;
549
550      if (isa<ConstantSDNode>(Op1)) {
551        ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
552        offset = int32_t(CN->getSExtValue());
553        idxOp = Op0;
554      } else if (isa<ConstantSDNode>(Op0)) {
555        ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
556        offset = int32_t(CN->getSExtValue());
557        idxOp = Op1;
558      }
559
560      if (offset >= minOffset && offset <= maxOffset) {
561        Base = CurDAG->getTargetConstant(offset, PtrTy);
562        Index = idxOp;
563        return true;
564      }
565    }
566  } else if (Opc == SPUISD::AFormAddr) {
567    Base = CurDAG->getTargetConstant(0, N.getValueType());
568    Index = N;
569    return true;
570  } else if (Opc == SPUISD::LDRESULT) {
571    Base = CurDAG->getTargetConstant(0, N.getValueType());
572    Index = N;
573    return true;
574  } else if (Opc == ISD::Register
575           ||Opc == ISD::CopyFromReg
576           ||Opc == ISD::UNDEF
577           ||Opc == ISD::Constant) {
578    unsigned OpOpc = Op->getOpcode();
579
580    if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
581      // Direct load/store without getelementptr
582      SDValue Offs;
583
584      Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
585
586      if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
587        if (Offs.getOpcode() == ISD::UNDEF)
588          Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
589
590        Base = Offs;
591        Index = N;
592        return true;
593      }
594    } else {
595      /* If otherwise unadorned, default to D-form address with 0 offset: */
596      if (Opc == ISD::CopyFromReg) {
597        Index = N.getOperand(1);
598      } else {
599        Index = N;
600      }
601
602      Base = CurDAG->getTargetConstant(0, Index.getValueType());
603      return true;
604    }
605  }
606
607  return false;
608}
609
610/*!
611  \arg Op The ISD instruction operand
612  \arg N The address operand
613  \arg Base The base pointer operand
614  \arg Index The offset/index operand
615
616  If the address \a N can be expressed as an A-form or D-form address, returns
617  false.  Otherwise, creates two operands, Base and Index that will become the
618  (r)(r) X-form address.
619*/
620bool
621SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
622                                 SDValue &Index) {
623  if (!SelectAFormAddr(Op, N, Base, Index)
624      && !SelectDFormAddr(Op, N, Base, Index)) {
625    // If the address is neither A-form or D-form, punt and use an X-form
626    // address:
627    Base = N.getOperand(1);
628    Index = N.getOperand(0);
629    return true;
630  }
631
632  return false;
633}
634
635//! Convert the operand from a target-independent to a target-specific node
636/*!
637 */
638SDNode *
639SPUDAGToDAGISel::Select(SDNode *N) {
640  unsigned Opc = N->getOpcode();
641  int n_ops = -1;
642  unsigned NewOpc;
643  EVT OpVT = N->getValueType(0);
644  SDValue Ops[8];
645  DebugLoc dl = N->getDebugLoc();
646
647  if (N->isMachineOpcode())
648    return NULL;   // Already selected.
649
650  if (Opc == ISD::FrameIndex) {
651    int FI = cast<FrameIndexSDNode>(N)->getIndex();
652    SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
653    SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
654
655    if (FI < 128) {
656      NewOpc = SPU::AIr32;
657      Ops[0] = TFI;
658      Ops[1] = Imm0;
659      n_ops = 2;
660    } else {
661      NewOpc = SPU::Ar32;
662      Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
663      Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
664                                              N->getValueType(0), TFI, Imm0),
665                       0);
666      n_ops = 2;
667    }
668  } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
669    // Catch the i64 constants that end up here. Note: The backend doesn't
670    // attempt to legalize the constant (it's useless because DAGCombiner
671    // will insert 64-bit constants and we can't stop it).
672    return SelectI64Constant(N, OpVT, N->getDebugLoc());
673  } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
674             && OpVT == MVT::i64) {
675    SDValue Op0 = N->getOperand(0);
676    EVT Op0VT = Op0.getValueType();
677    EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
678                                    Op0VT, (128 / Op0VT.getSizeInBits()));
679    EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
680                                   OpVT, (128 / OpVT.getSizeInBits()));
681    SDValue shufMask;
682
683    switch (Op0VT.getSimpleVT().SimpleTy) {
684    default:
685      report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
686      /*NOTREACHED*/
687    case MVT::i32:
688      shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
689                                 CurDAG->getConstant(0x80808080, MVT::i32),
690                                 CurDAG->getConstant(0x00010203, MVT::i32),
691                                 CurDAG->getConstant(0x80808080, MVT::i32),
692                                 CurDAG->getConstant(0x08090a0b, MVT::i32));
693      break;
694
695    case MVT::i16:
696      shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
697                                 CurDAG->getConstant(0x80808080, MVT::i32),
698                                 CurDAG->getConstant(0x80800203, MVT::i32),
699                                 CurDAG->getConstant(0x80808080, MVT::i32),
700                                 CurDAG->getConstant(0x80800a0b, MVT::i32));
701      break;
702
703    case MVT::i8:
704      shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
705                                 CurDAG->getConstant(0x80808080, MVT::i32),
706                                 CurDAG->getConstant(0x80808003, MVT::i32),
707                                 CurDAG->getConstant(0x80808080, MVT::i32),
708                                 CurDAG->getConstant(0x8080800b, MVT::i32));
709      break;
710    }
711
712    SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
713
714    HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
715                                               Op0VecVT, Op0));
716
717    SDValue PromScalar;
718    if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
719      PromScalar = SDValue(N, 0);
720    else
721      PromScalar = PromoteScalar.getValue();
722
723    SDValue zextShuffle =
724            CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
725                            PromScalar, PromScalar,
726                            SDValue(shufMaskLoad, 0));
727
728    HandleSDNode Dummy2(zextShuffle);
729    if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
730      zextShuffle = SDValue(N, 0);
731    else
732      zextShuffle = Dummy2.getValue();
733    HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
734                                       zextShuffle));
735
736    CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
737    SelectCode(Dummy.getValue().getNode());
738    return Dummy.getValue().getNode();
739  } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
740    SDNode *CGLoad =
741            emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
742
743    HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
744                                       N->getOperand(0), N->getOperand(1),
745                                       SDValue(CGLoad, 0)));
746
747    CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
748    if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
749      return N;
750    return Dummy.getValue().getNode();
751  } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
752    SDNode *CGLoad =
753            emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
754
755    HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
756                                       N->getOperand(0), N->getOperand(1),
757                                       SDValue(CGLoad, 0)));
758
759    CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
760    if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
761      return N;
762    return Dummy.getValue().getNode();
763  } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
764    SDNode *CGLoad =
765            emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
766
767    HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
768                                       N->getOperand(0), N->getOperand(1),
769                                       SDValue(CGLoad, 0)));
770    CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
771    if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
772      return N;
773    return Dummy.getValue().getNode();
774  } else if (Opc == ISD::TRUNCATE) {
775    SDValue Op0 = N->getOperand(0);
776    if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
777        && OpVT == MVT::i32
778        && Op0.getValueType() == MVT::i64) {
779      // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
780      //
781      // Take advantage of the fact that the upper 32 bits are in the
782      // i32 preferred slot and avoid shuffle gymnastics:
783      ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
784      if (CN != 0) {
785        unsigned shift_amt = unsigned(CN->getZExtValue());
786
787        if (shift_amt >= 32) {
788          SDNode *hi32 =
789                  CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT,
790                                         Op0.getOperand(0));
791
792          shift_amt -= 32;
793          if (shift_amt > 0) {
794            // Take care of the additional shift, if present:
795            SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
796            unsigned Opc = SPU::ROTMAIr32_i32;
797
798            if (Op0.getOpcode() == ISD::SRL)
799              Opc = SPU::ROTMr32;
800
801            hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
802                                          shift);
803          }
804
805          return hi32;
806        }
807      }
808    }
809  } else if (Opc == ISD::SHL) {
810    if (OpVT == MVT::i64)
811      return SelectSHLi64(N, OpVT);
812  } else if (Opc == ISD::SRL) {
813    if (OpVT == MVT::i64)
814      return SelectSRLi64(N, OpVT);
815  } else if (Opc == ISD::SRA) {
816    if (OpVT == MVT::i64)
817      return SelectSRAi64(N, OpVT);
818  } else if (Opc == ISD::FNEG
819             && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
820    DebugLoc dl = N->getDebugLoc();
821    // Check if the pattern is a special form of DFNMS:
822    // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
823    SDValue Op0 = N->getOperand(0);
824    if (Op0.getOpcode() == ISD::FSUB) {
825      SDValue Op00 = Op0.getOperand(0);
826      if (Op00.getOpcode() == ISD::FMUL) {
827        unsigned Opc = SPU::DFNMSf64;
828        if (OpVT == MVT::v2f64)
829          Opc = SPU::DFNMSv2f64;
830
831        return CurDAG->getMachineNode(Opc, dl, OpVT,
832                                      Op00.getOperand(0),
833                                      Op00.getOperand(1),
834                                      Op0.getOperand(1));
835      }
836    }
837
838    SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
839    SDNode *signMask = 0;
840    unsigned Opc = SPU::XORfneg64;
841
842    if (OpVT == MVT::f64) {
843      signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
844    } else if (OpVT == MVT::v2f64) {
845      Opc = SPU::XORfnegvec;
846      signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
847                                                 MVT::v2i64,
848                                                 negConst, negConst).getNode());
849    }
850
851    return CurDAG->getMachineNode(Opc, dl, OpVT,
852                                  N->getOperand(0), SDValue(signMask, 0));
853  } else if (Opc == ISD::FABS) {
854    if (OpVT == MVT::f64) {
855      SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
856      return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
857                                    N->getOperand(0), SDValue(signMask, 0));
858    } else if (OpVT == MVT::v2f64) {
859      SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
860      SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
861                                       absConst, absConst);
862      SDNode *signMask = emitBuildVector(absVec.getNode());
863      return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
864                                    N->getOperand(0), SDValue(signMask, 0));
865    }
866  } else if (Opc == SPUISD::LDRESULT) {
867    // Custom select instructions for LDRESULT
868    EVT VT = N->getValueType(0);
869    SDValue Arg = N->getOperand(0);
870    SDValue Chain = N->getOperand(1);
871    SDNode *Result;
872    const valtype_map_s *vtm = getValueTypeMapEntry(VT);
873
874    if (vtm->ldresult_ins == 0) {
875      report_fatal_error("LDRESULT for unsupported type: " +
876                         Twine(VT.getEVTString()));
877    }
878
879    Opc = vtm->ldresult_ins;
880    if (vtm->ldresult_imm) {
881      SDValue Zero = CurDAG->getTargetConstant(0, VT);
882
883      Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
884    } else {
885      Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
886    }
887
888    return Result;
889  } else if (Opc == SPUISD::IndirectAddr) {
890    // Look at the operands: SelectCode() will catch the cases that aren't
891    // specifically handled here.
892    //
893    // SPUInstrInfo catches the following patterns:
894    // (SPUindirect (SPUhi ...), (SPUlo ...))
895    // (SPUindirect $sp, imm)
896    EVT VT = N->getValueType(0);
897    SDValue Op0 = N->getOperand(0);
898    SDValue Op1 = N->getOperand(1);
899    RegisterSDNode *RN;
900
901    if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
902        || (Op0.getOpcode() == ISD::Register
903            && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
904                && RN->getReg() != SPU::R1))) {
905      NewOpc = SPU::Ar32;
906      Ops[1] = Op1;
907      if (Op1.getOpcode() == ISD::Constant) {
908        ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
909        Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
910        if (isInt<10>(CN->getSExtValue())) {
911          NewOpc = SPU::AIr32;
912          Ops[1] = Op1;
913        } else {
914          Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
915                                                  N->getValueType(0),
916                                                  Op1),
917                           0);
918        }
919      }
920      Ops[0] = Op0;
921      n_ops = 2;
922    }
923  }
924
925  if (n_ops > 0) {
926    if (N->hasOneUse())
927      return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
928    else
929      return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
930  } else
931    return SelectCode(N);
932}
933
934/*!
935 * Emit the instruction sequence for i64 left shifts. The basic algorithm
936 * is to fill the bottom two word slots with zeros so that zeros are shifted
937 * in as the entire quadword is shifted left.
938 *
939 * \note This code could also be used to implement v2i64 shl.
940 *
941 * @param Op The shl operand
942 * @param OpVT Op's machine value value type (doesn't need to be passed, but
943 * makes life easier.)
944 * @return The SDNode with the entire instruction sequence
945 */
946SDNode *
947SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
948  SDValue Op0 = N->getOperand(0);
949  EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
950                               OpVT, (128 / OpVT.getSizeInBits()));
951  SDValue ShiftAmt = N->getOperand(1);
952  EVT ShiftAmtVT = ShiftAmt.getValueType();
953  SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
954  SDValue SelMaskVal;
955  DebugLoc dl = N->getDebugLoc();
956
957  VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
958  SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
959  SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
960  ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
961                                    CurDAG->getTargetConstant(0, OpVT));
962  VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
963                                  SDValue(ZeroFill, 0),
964                                  SDValue(VecOp0, 0),
965                                  SDValue(SelMask, 0));
966
967  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
968    unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
969    unsigned bits = unsigned(CN->getZExtValue()) & 7;
970
971    if (bytes > 0) {
972      Shift =
973        CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
974                               SDValue(VecOp0, 0),
975                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
976    }
977
978    if (bits > 0) {
979      Shift =
980        CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
981                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
982                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
983    }
984  } else {
985    SDNode *Bytes =
986      CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
987                             ShiftAmt,
988                             CurDAG->getTargetConstant(3, ShiftAmtVT));
989    SDNode *Bits =
990      CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
991                             ShiftAmt,
992                             CurDAG->getTargetConstant(7, ShiftAmtVT));
993    Shift =
994      CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
995                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
996    Shift =
997      CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
998                             SDValue(Shift, 0), SDValue(Bits, 0));
999  }
1000
1001  return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1002}
1003
1004/*!
1005 * Emit the instruction sequence for i64 logical right shifts.
1006 *
1007 * @param Op The shl operand
1008 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1009 * makes life easier.)
1010 * @return The SDNode with the entire instruction sequence
1011 */
1012SDNode *
1013SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
1014  SDValue Op0 = N->getOperand(0);
1015  EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1016                               OpVT, (128 / OpVT.getSizeInBits()));
1017  SDValue ShiftAmt = N->getOperand(1);
1018  EVT ShiftAmtVT = ShiftAmt.getValueType();
1019  SDNode *VecOp0, *Shift = 0;
1020  DebugLoc dl = N->getDebugLoc();
1021
1022  VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1023
1024  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1025    unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1026    unsigned bits = unsigned(CN->getZExtValue()) & 7;
1027
1028    if (bytes > 0) {
1029      Shift =
1030        CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1031                               SDValue(VecOp0, 0),
1032                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1033    }
1034
1035    if (bits > 0) {
1036      Shift =
1037        CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1038                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
1039                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1040    }
1041  } else {
1042    SDNode *Bytes =
1043      CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1044                             ShiftAmt,
1045                             CurDAG->getTargetConstant(3, ShiftAmtVT));
1046    SDNode *Bits =
1047      CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1048                             ShiftAmt,
1049                             CurDAG->getTargetConstant(7, ShiftAmtVT));
1050
1051    // Ensure that the shift amounts are negated!
1052    Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1053                                   SDValue(Bytes, 0),
1054                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
1055
1056    Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1057                                  SDValue(Bits, 0),
1058                                  CurDAG->getTargetConstant(0, ShiftAmtVT));
1059
1060    Shift =
1061      CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1062                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
1063    Shift =
1064      CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1065                             SDValue(Shift, 0), SDValue(Bits, 0));
1066  }
1067
1068  return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1069}
1070
1071/*!
1072 * Emit the instruction sequence for i64 arithmetic right shifts.
1073 *
1074 * @param Op The shl operand
1075 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1076 * makes life easier.)
1077 * @return The SDNode with the entire instruction sequence
1078 */
1079SDNode *
1080SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1081  // Promote Op0 to vector
1082  EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1083                               OpVT, (128 / OpVT.getSizeInBits()));
1084  SDValue ShiftAmt = N->getOperand(1);
1085  EVT ShiftAmtVT = ShiftAmt.getValueType();
1086  DebugLoc dl = N->getDebugLoc();
1087
1088  SDNode *VecOp0 =
1089    CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0));
1090
1091  SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1092  SDNode *SignRot =
1093    CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1094                           SDValue(VecOp0, 0), SignRotAmt);
1095  SDNode *UpperHalfSign =
1096    CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1097
1098  SDNode *UpperHalfSignMask =
1099    CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1100  SDNode *UpperLowerMask =
1101    CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1102                           CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1103  SDNode *UpperLowerSelect =
1104    CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1105                           SDValue(UpperHalfSignMask, 0),
1106                           SDValue(VecOp0, 0),
1107                           SDValue(UpperLowerMask, 0));
1108
1109  SDNode *Shift = 0;
1110
1111  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1112    unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1113    unsigned bits = unsigned(CN->getZExtValue()) & 7;
1114
1115    if (bytes > 0) {
1116      bytes = 31 - bytes;
1117      Shift =
1118        CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1119                               SDValue(UpperLowerSelect, 0),
1120                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1121    }
1122
1123    if (bits > 0) {
1124      bits = 8 - bits;
1125      Shift =
1126        CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1127                               SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1128                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1129    }
1130  } else {
1131    SDNode *NegShift =
1132      CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1133                             ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1134
1135    Shift =
1136      CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1137                             SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1138    Shift =
1139      CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1140                             SDValue(Shift, 0), SDValue(NegShift, 0));
1141  }
1142
1143  return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1144}
1145
1146/*!
1147 Do the necessary magic necessary to load a i64 constant
1148 */
1149SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1150                                           DebugLoc dl) {
1151  ConstantSDNode *CN = cast<ConstantSDNode>(N);
1152  return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1153}
1154
1155SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1156                                           DebugLoc dl) {
1157  EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1158  SDValue i64vec =
1159          SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1160
1161  // Here's where it gets interesting, because we have to parse out the
1162  // subtree handed back in i64vec:
1163
1164  if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1165    // The degenerate case where the upper and lower bits in the splat are
1166    // identical:
1167    SDValue Op0 = i64vec.getOperand(0);
1168
1169    ReplaceUses(i64vec, Op0);
1170    return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1171                                  SDValue(emitBuildVector(Op0.getNode()), 0));
1172  } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1173    SDValue lhs = i64vec.getOperand(0);
1174    SDValue rhs = i64vec.getOperand(1);
1175    SDValue shufmask = i64vec.getOperand(2);
1176
1177    if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1178      ReplaceUses(lhs, lhs.getOperand(0));
1179      lhs = lhs.getOperand(0);
1180    }
1181
1182    SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1183                       ? lhs.getNode()
1184                       : emitBuildVector(lhs.getNode()));
1185
1186    if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1187      ReplaceUses(rhs, rhs.getOperand(0));
1188      rhs = rhs.getOperand(0);
1189    }
1190
1191    SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1192                       ? rhs.getNode()
1193                       : emitBuildVector(rhs.getNode()));
1194
1195    if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1196      ReplaceUses(shufmask, shufmask.getOperand(0));
1197      shufmask = shufmask.getOperand(0);
1198    }
1199
1200    SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1201                            ? shufmask.getNode()
1202                            : emitBuildVector(shufmask.getNode()));
1203
1204   SDValue shufNode =
1205            CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1206                                   SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1207                                   SDValue(shufMaskNode, 0));
1208    HandleSDNode Dummy(shufNode);
1209    SDNode *SN = SelectCode(Dummy.getValue().getNode());
1210    if (SN == 0) SN = Dummy.getValue().getNode();
1211
1212    return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(SN, 0));
1213  } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1214    return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1215                                  SDValue(emitBuildVector(i64vec.getNode()), 0));
1216  } else {
1217    report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1218                      "condition");
1219  }
1220}
1221
1222/// createSPUISelDag - This pass converts a legalized DAG into a
1223/// SPU-specific DAG, ready for instruction scheduling.
1224///
1225FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1226  return new SPUDAGToDAGISel(TM);
1227}
1228