1//===-- SPUSubtarget.cpp - STI Cell SPU Subtarget Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CellSPU-specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SPUSubtarget.h"
15#include "SPU.h"
16#include "SPURegisterInfo.h"
17#include "llvm/Support/TargetRegistry.h"
18
19#define GET_SUBTARGETINFO_TARGET_DESC
20#define GET_SUBTARGETINFO_CTOR
21#include "SPUGenSubtargetInfo.inc"
22
23using namespace llvm;
24
25SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
26                           const std::string &FS) :
27  SPUGenSubtargetInfo(TT, CPU, FS),
28  StackAlignment(16),
29  ProcDirective(SPU::DEFAULT_PROC),
30  UseLargeMem(false)
31{
32  // Should be the target SPU processor type. For now, since there's only
33  // one, simply default to the current "v0" default:
34  std::string default_cpu("v0");
35
36  // Parse features string.
37  ParseSubtargetFeatures(default_cpu, FS);
38
39  // Initialize scheduling itinerary for the specified CPU.
40  InstrItins = getInstrItineraryForCPU(default_cpu);
41}
42
43/// SetJITMode - This is called to inform the subtarget info that we are
44/// producing code for the JIT.
45void SPUSubtarget::SetJITMode() {
46}
47
48/// Enable PostRA scheduling for optimization levels -O2 and -O3.
49bool SPUSubtarget::enablePostRAScheduler(
50                       CodeGenOpt::Level OptLevel,
51                       TargetSubtargetInfo::AntiDepBreakMode& Mode,
52                       RegClassVector& CriticalPathRCs) const {
53  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
54  // CriticalPathsRCs seems to be the set of
55  // RegisterClasses that antidep breakings are performed for.
56  // Do it for all register classes
57  CriticalPathRCs.clear();
58  CriticalPathRCs.push_back(&SPU::R8CRegClass);
59  CriticalPathRCs.push_back(&SPU::R16CRegClass);
60  CriticalPathRCs.push_back(&SPU::R32CRegClass);
61  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
62  CriticalPathRCs.push_back(&SPU::R64CRegClass);
63  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
64  return OptLevel >= CodeGenOpt::Default;
65}
66