1//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the Mips specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsSubtarget.h" 15#include "Mips.h" 16#include "MipsRegisterInfo.h" 17#include "llvm/Support/TargetRegistry.h" 18 19#define GET_SUBTARGETINFO_TARGET_DESC 20#define GET_SUBTARGETINFO_CTOR 21#include "MipsGenSubtargetInfo.inc" 22 23using namespace llvm; 24 25void MipsSubtarget::anchor() { } 26 27MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, 28 const std::string &FS, bool little, 29 Reloc::Model RM) : 30 MipsGenSubtargetInfo(TT, CPU, FS), 31 MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little), 32 IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), 33 IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), 34 HasMinMax(false), HasSwap(false), HasBitCount(false), InMips16Mode(false) 35{ 36 std::string CPUName = CPU; 37 if (CPUName.empty()) 38 CPUName = "mips32"; 39 40 // Parse features string. 41 ParseSubtargetFeatures(CPUName, FS); 42 43 // Initialize scheduling itinerary for the specified CPU. 44 InstrItins = getInstrItineraryForCPU(CPUName); 45 46 // Set MipsABI if it hasn't been set yet. 47 if (MipsABI == UnknownABI) 48 MipsABI = hasMips64() ? N64 : O32; 49 50 // Check if Architecture and ABI are compatible. 51 assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) || 52 (hasMips64() && (isABI_N32() || isABI_N64()))) && 53 "Invalid Arch & ABI pair."); 54 55 // Is the target system Linux ? 56 if (TT.find("linux") == std::string::npos) 57 IsLinux = false; 58 59 // Set UseSmallSection. 60 UseSmallSection = !IsLinux && (RM == Reloc::Static); 61} 62 63bool 64MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, 65 TargetSubtargetInfo::AntiDepBreakMode &Mode, 66 RegClassVector &CriticalPathRCs) const { 67 Mode = TargetSubtargetInfo::ANTIDEP_NONE; 68 CriticalPathRCs.clear(); 69 CriticalPathRCs.push_back(hasMips64() ? 70 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass); 71 return OptLevel >= CodeGenOpt::Aggressive; 72} 73