1#!/usr/bin/env python 2 3num_regs = 396 4 5outFile = open('NVPTXRegisterInfo.td', 'w') 6 7outFile.write(''' 8//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===// 9// 10// The LLVM Compiler Infrastructure 11// 12// This file is distributed under the University of Illinois Open Source 13// License. See LICENSE.TXT for details. 14// 15//===----------------------------------------------------------------------===// 16 17//===----------------------------------------------------------------------===// 18// Declarations that describe the PTX register file 19//===----------------------------------------------------------------------===// 20 21class NVPTXReg<string n> : Register<n> { 22 let Namespace = "NVPTX"; 23} 24 25class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList> 26 : RegisterClass <"NVPTX", regTypes, alignment, regList>; 27 28//===----------------------------------------------------------------------===// 29// Registers 30//===----------------------------------------------------------------------===// 31 32// Special Registers used as stack pointer 33def VRFrame : NVPTXReg<"%SP">; 34def VRFrameLocal : NVPTXReg<"%SPL">; 35 36// Special Registers used as the stack 37def VRDepot : NVPTXReg<"%Depot">; 38''') 39 40# Predicates 41outFile.write(''' 42//===--- Predicate --------------------------------------------------------===// 43''') 44for i in range(0, num_regs): 45 outFile.write('def P%d : NVPTXReg<"%%p%d">;\n' % (i, i)) 46 47# Int8 48outFile.write(''' 49//===--- 8-bit ------------------------------------------------------------===// 50''') 51for i in range(0, num_regs): 52 outFile.write('def RC%d : NVPTXReg<"%%rc%d">;\n' % (i, i)) 53 54# Int16 55outFile.write(''' 56//===--- 16-bit -----------------------------------------------------------===// 57''') 58for i in range(0, num_regs): 59 outFile.write('def RS%d : NVPTXReg<"%%rs%d">;\n' % (i, i)) 60 61# Int32 62outFile.write(''' 63//===--- 32-bit -----------------------------------------------------------===// 64''') 65for i in range(0, num_regs): 66 outFile.write('def R%d : NVPTXReg<"%%r%d">;\n' % (i, i)) 67 68# Int64 69outFile.write(''' 70//===--- 64-bit -----------------------------------------------------------===// 71''') 72for i in range(0, num_regs): 73 outFile.write('def RL%d : NVPTXReg<"%%rl%d">;\n' % (i, i)) 74 75# F32 76outFile.write(''' 77//===--- 32-bit float -----------------------------------------------------===// 78''') 79for i in range(0, num_regs): 80 outFile.write('def F%d : NVPTXReg<"%%f%d">;\n' % (i, i)) 81 82# F64 83outFile.write(''' 84//===--- 64-bit float -----------------------------------------------------===// 85''') 86for i in range(0, num_regs): 87 outFile.write('def FL%d : NVPTXReg<"%%fl%d">;\n' % (i, i)) 88 89# Vector registers 90outFile.write(''' 91//===--- Vector -----------------------------------------------------------===// 92''') 93for i in range(0, num_regs): 94 outFile.write('def v2b8_%d : NVPTXReg<"%%v2b8_%d">;\n' % (i, i)) 95for i in range(0, num_regs): 96 outFile.write('def v2b16_%d : NVPTXReg<"%%v2b16_%d">;\n' % (i, i)) 97for i in range(0, num_regs): 98 outFile.write('def v2b32_%d : NVPTXReg<"%%v2b32_%d">;\n' % (i, i)) 99for i in range(0, num_regs): 100 outFile.write('def v2b64_%d : NVPTXReg<"%%v2b64_%d">;\n' % (i, i)) 101 102for i in range(0, num_regs): 103 outFile.write('def v4b8_%d : NVPTXReg<"%%v4b8_%d">;\n' % (i, i)) 104for i in range(0, num_regs): 105 outFile.write('def v4b16_%d : NVPTXReg<"%%v4b16_%d">;\n' % (i, i)) 106for i in range(0, num_regs): 107 outFile.write('def v4b32_%d : NVPTXReg<"%%v4b32_%d">;\n' % (i, i)) 108 109# Argument registers 110outFile.write(''' 111//===--- Arguments --------------------------------------------------------===// 112''') 113for i in range(0, num_regs): 114 outFile.write('def ia%d : NVPTXReg<"%%ia%d">;\n' % (i, i)) 115for i in range(0, num_regs): 116 outFile.write('def la%d : NVPTXReg<"%%la%d">;\n' % (i, i)) 117for i in range(0, num_regs): 118 outFile.write('def fa%d : NVPTXReg<"%%fa%d">;\n' % (i, i)) 119for i in range(0, num_regs): 120 outFile.write('def da%d : NVPTXReg<"%%da%d">;\n' % (i, i)) 121 122outFile.write(''' 123//===----------------------------------------------------------------------===// 124// Register classes 125//===----------------------------------------------------------------------===// 126''') 127 128outFile.write('def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%%u", 0, %d))>;\n' % (num_regs-1)) 129outFile.write('def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%%u", 0, %d))>;\n' % (num_regs-1)) 130outFile.write('def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%%u", 0, %d))>;\n' % (num_regs-1)) 131outFile.write('def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%%u", 0, %d))>;\n' % (num_regs-1)) 132outFile.write('def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%%u", 0, %d))>;\n' % (num_regs-1)) 133 134outFile.write('def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%%u", 0, %d))>;\n' % (num_regs-1)) 135outFile.write('def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%%u", 0, %d))>;\n' % (num_regs-1)) 136 137outFile.write('def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%%u", 0, %d))>;\n' % (num_regs-1)) 138outFile.write('def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%%u", 0, %d))>;\n' % (num_regs-1)) 139outFile.write('def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%%u", 0, %d))>;\n' % (num_regs-1)) 140outFile.write('def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%%u", 0, %d))>;\n' % (num_regs-1)) 141 142outFile.write(''' 143// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used. 144def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>; 145''') 146 147outFile.write(''' 148class NVPTXVecRegClass<list<ValueType> regTypes, int alignment, dag regList, 149 NVPTXRegClass sClass, 150 int e, 151 string n> 152 : NVPTXRegClass<regTypes, alignment, regList> 153{ 154 NVPTXRegClass scalarClass=sClass; 155 int elems=e; 156 string name=n; 157} 158''') 159 160 161outFile.write('def V2F32Regs\n : NVPTXVecRegClass<[v2f32], 64, (add (sequence "v2b32_%%u", 0, %d)),\n Float32Regs, 2, ".v2.f32">;\n' % (num_regs-1)) 162outFile.write('def V4F32Regs\n : NVPTXVecRegClass<[v4f32], 128, (add (sequence "v4b32_%%u", 0, %d)),\n Float32Regs, 4, ".v4.f32">;\n' % (num_regs-1)) 163 164outFile.write('def V2I32Regs\n : NVPTXVecRegClass<[v2i32], 64, (add (sequence "v2b32_%%u", 0, %d)),\n Int32Regs, 2, ".v2.u32">;\n' % (num_regs-1)) 165outFile.write('def V4I32Regs\n : NVPTXVecRegClass<[v4i32], 128, (add (sequence "v4b32_%%u", 0, %d)),\n Int32Regs, 4, ".v4.u32">;\n' % (num_regs-1)) 166 167outFile.write('def V2F64Regs\n : NVPTXVecRegClass<[v2f64], 128, (add (sequence "v2b64_%%u", 0, %d)),\n Float64Regs, 2, ".v2.f64">;\n' % (num_regs-1)) 168outFile.write('def V2I64Regs\n : NVPTXVecRegClass<[v2i64], 128, (add (sequence "v2b64_%%u", 0, %d)),\n Int64Regs, 2, ".v2.u64">;\n' % (num_regs-1)) 169 170outFile.write('def V2I16Regs\n : NVPTXVecRegClass<[v2i16], 32, (add (sequence "v2b16_%%u", 0, %d)),\n Int16Regs, 2, ".v2.u16">;\n' % (num_regs-1)) 171outFile.write('def V4I16Regs\n : NVPTXVecRegClass<[v4i16], 64, (add (sequence "v4b16_%%u", 0, %d)),\n Int16Regs, 4, ".v4.u16">;\n' % (num_regs-1)) 172 173outFile.write('def V2I8Regs\n : NVPTXVecRegClass<[v2i8], 16, (add (sequence "v2b8_%%u", 0, %d)),\n Int8Regs, 2, ".v2.u8">;\n' % (num_regs-1)) 174outFile.write('def V4I8Regs\n : NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%%u", 0, %d)),\n Int8Regs, 4, ".v4.u8">;\n' % (num_regs-1)) 175 176outFile.close() 177 178 179outFile = open('NVPTXNumRegisters.h', 'w') 180outFile.write(''' 181//===-- NVPTXNumRegisters.h - PTX Register Info ---------------------------===// 182// 183// The LLVM Compiler Infrastructure 184// 185// This file is distributed under the University of Illinois Open Source 186// License. See LICENSE.TXT for details. 187// 188//===----------------------------------------------------------------------===// 189 190#ifndef NVPTX_NUM_REGISTERS_H 191#define NVPTX_NUM_REGISTERS_H 192 193namespace llvm { 194 195const unsigned NVPTXNumRegisters = %d; 196 197} 198 199#endif 200''' % num_regs) 201 202outFile.close() 203