PPCInstrInfo.cpp revision 746ad69e088176819981b4b2c5ac8dcd49f5e60e
121e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1416e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCInstrInfo.h" 15f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson#include "PPCInstrBuilder.h" 167194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "PPCMachineFunctionInfo.h" 17df4ed6350b2a51f71c0980e86c9078f4046ea706Chris Lattner#include "PPCPredicates.h" 184c7b43b43fdf943c7298718e15ab5d6dfe345be7Chris Lattner#include "PPCGenInstrInfo.inc" 19b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner#include "PPCTargetMachine.h" 20718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 21f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 22243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen#include "llvm/CodeGen/MachineRegisterInfo.h" 23880d0f6018b6928bdcad291be60c801238619955Bill Wendling#include "llvm/Support/CommandLine.h" 24dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 25dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 26af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner#include "llvm/MC/MCAsmInfo.h" 27f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 2882bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmannamespace llvm { 294a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingextern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 304a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingextern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 3182bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman} 3282bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman 3382bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmanusing namespace llvm; 34880d0f6018b6928bdcad291be60c801238619955Bill Wendling 35b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris LattnerPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 36641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 377ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng RI(*TM.getSubtargetImpl(), *this) {} 38b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 3921e463b2bf864671a87ebe386cb100ef9349a540Nate Begemanbool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 4021e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman unsigned& sourceReg, 4104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& destReg, 4204ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& sourceSubIdx, 4304ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& destSubIdx) const { 4404ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng sourceSubIdx = destSubIdx = 0; // No sub-registers. 4504ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng 46cc8cd0cbf12c12916d4b38ef0de5be5501c8270eChris Lattner unsigned oc = MI.getOpcode(); 47b410dc99774d52b4491750dab10b91cca1d661d8Chris Lattner if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 4814c09b81ead8fe8b754fca2d0a8237cb810b37d6Chris Lattner oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 491e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 50d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(0).isReg() && 51d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(1).isReg() && 52d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(2).isReg() && 53f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC OR instruction!"); 54f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 55f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 56f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 57f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 58f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 59f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } else if (oc == PPC::ADDI) { // addi r1, r2, 0 601e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 61d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(0).isReg() && 62d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(2).isImm() && 63f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC ADDI instruction!"); 64d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) { 65f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 66f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 67f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 68f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 69cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } else if (oc == PPC::ORI) { // ori r1, r2, 0 701e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 71d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(0).isReg() && 72d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(1).isReg() && 73d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(2).isImm() && 74cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman "invalid PPC ORI instruction!"); 759a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI.getOperand(2).getImm() == 0) { 76cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman sourceReg = MI.getOperand(1).getReg(); 77cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman destReg = MI.getOperand(0).getReg(); 78cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman return true; 79cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } 80baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2 811e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 82d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(0).isReg() && 83d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(1).isReg() && 84f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC FMR instruction"); 85f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 86f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 87f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 887af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 891e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 90d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(0).isReg() && 91d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI.getOperand(1).isReg() && 927af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman "invalid PPC MCRF instruction"); 937af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman sourceReg = MI.getOperand(1).getReg(); 947af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman destReg = MI.getOperand(0).getReg(); 957af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman return true; 96f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 97f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return false; 98f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 99043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 100cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1019c09c9ec9dab61450800b42cbf746164aa076b88Chris Lattner int &FrameIndex) const { 102408396014742a05cad1c91949d2226169e3f9d80Chris Lattner switch (MI->getOpcode()) { 103408396014742a05cad1c91949d2226169e3f9d80Chris Lattner default: break; 104408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LD: 105408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LWZ: 106408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFS: 107408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFD: 108d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 109d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 1108aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 111408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return MI->getOperand(0).getReg(); 112408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 113408396014742a05cad1c91949d2226169e3f9d80Chris Lattner break; 114408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 115408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return 0; 1166524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 117408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 118cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1196524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner int &FrameIndex) const { 1206524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner switch (MI->getOpcode()) { 1216524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner default: break; 1223b478b31e297208ef2c9f74750a8a603eb3726fbNate Begeman case PPC::STD: 1236524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STW: 1246524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFS: 1256524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFD: 126d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 127d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 1288aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 1296524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return MI->getOperand(0).getReg(); 1306524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1316524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner break; 1326524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1336524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return 0; 1346524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 135408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 136043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// commuteInstruction - We can commute rlwimi instructions, but only if the 137043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// rotate amt is zero. We also have to munge the immediates a bit. 13858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr * 13958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengPPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1408e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 1418e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 142043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Normal instructions can be commuted the obvious way. 143043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner if (MI->getOpcode() != PPC::RLWIMI) 14458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 145043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 146043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Cannot commute if it has a non-zero rotate count. 1479a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI->getOperand(3).getImm() != 0) 148043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return 0; 149043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 150043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // If we have a zero rotate count, we have: 151043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask(MB,ME) 152043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op1 & ~M) | (Op2 & M) 153043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Change this to: 154043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask((ME+1)&31, (MB-1)&31) 155043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op2 & ~M) | (Op1 & M) 156043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 157043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap op1/op2 158a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng unsigned Reg0 = MI->getOperand(0).getReg(); 159043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 160043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 1616ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg1IsKill = MI->getOperand(1).isKill(); 1626ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg2IsKill = MI->getOperand(2).isKill(); 16358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 164a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // If machine instrs are no longer in two-address forms, update 165a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // destination register as well. 166a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng if (Reg0 == Reg1) { 167a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 168a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 169a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 170a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 17158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 17258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 17358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 17458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Masks. 17558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned MB = MI->getOperand(4).getImm(); 17658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned ME = MI->getOperand(5).getImm(); 17758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 17858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 17958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 18058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 18158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool Reg0IsDead = MI->getOperand(0).isDead(); 182d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 183587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 184587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg2, getKillRegState(Reg2IsKill)) 185587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg1, getKillRegState(Reg1IsKill)) 18658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((ME+1) & 31) 18758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((MB-1) & 31); 188a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 18958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 19058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 19158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 192e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(2).setReg(Reg1); 193e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(1).setReg(Reg2); 194f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 195f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 196043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 197043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap the mask around. 1989a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(4).setImm((ME+1) & 31); 1999a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(5).setImm((MB-1) & 31); 200043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return MI; 201043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner} 202bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 203bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattnervoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 204bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const { 205c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 206d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::NOP)); 207bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner} 208c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 209c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 210c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner// Branch analysis. 211c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 212c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 213dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 214dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const { 215c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If the block has no terminators, it just falls into the block after it. 216c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 21793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 21893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 21993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 22093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 22193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 22293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 22393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 22493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 22593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 226c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 227c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 228c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the last instruction in the block. 229c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *LastInst = I; 230c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 231c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there is only one terminator instruction, process it. 232bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 233c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (LastInst->getOpcode() == PPC::B) { 23482ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(0).isMBB()) 23582ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2368aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(0).getMBB(); 237c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 238289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner } else if (LastInst->getOpcode() == PPC::BCC) { 23982ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(2).isMBB()) 24082ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 241c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Block ends with fall-through condbranch. 2428aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(2).getMBB(); 243c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(0)); 244c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(1)); 2457c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 246c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 247c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, don't know what this is. 248c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 249c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 250c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 251c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the instruction before it if it's a terminator. 252c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *SecondLastInst = I; 253c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 254c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there are three terminators, we don't know what sort of block this is. 255c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (SecondLastInst && I != MBB.begin() && 256bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng isUnpredicatedTerminator(--I)) 257c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 258c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 259289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner // If the block ends with PPC::B and PPC:BCC, handle it. 260289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (SecondLastInst->getOpcode() == PPC::BCC && 261c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner LastInst->getOpcode() == PPC::B) { 26282ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(2).isMBB() || 26382ae933e55839713ea039e7c6353483b14dc5724Evan Cheng !LastInst->getOperand(0).isMBB()) 26482ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2658aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(2).getMBB(); 266c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(0)); 267c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(1)); 2688aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FBB = LastInst->getOperand(0).getMBB(); 269c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 270c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 271c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 27213e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // If the block ends with two PPC:Bs, handle it. The second one is not 27313e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // executed, so remove it. 27413e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen if (SecondLastInst->getOpcode() == PPC::B && 27513e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen LastInst->getOpcode() == PPC::B) { 27682ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(0).isMBB()) 27782ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2788aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(0).getMBB(); 27913e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I = LastInst; 280dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng if (AllowModify) 281dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng I->eraseFromParent(); 28213e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen return false; 28313e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen } 28413e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen 285c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, can't handle this. 286c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 287c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 288c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 289b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 290c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 291b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 0; 292c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 29393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 29493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 29593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 29693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 29793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 298289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 299b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 300c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 301c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 302c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 303c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 304c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I = MBB.end(); 305c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 306b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 1; 307c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 308289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::BCC) 309b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 310c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 311c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 312c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 313b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 314c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 315c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 316b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned 317b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan ChengPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 318b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 31944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const { 320536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen // FIXME this should probably have a DebugLoc argument 321c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl; 3222dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner // Shouldn't be a fall through. 3232dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 32454108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner assert((Cond.size() == 2 || Cond.size() == 0) && 32554108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner "PPC branch conditions have two components!"); 3262dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner 32754108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner // One-way branch. 3282dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner if (FBB == 0) { 32954108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner if (Cond.empty()) // Unconditional branch 330536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); 33154108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner else // Conditional branch 332536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(&MBB, dl, get(PPC::BCC)) 33318258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 334b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 3352dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner } 336c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 337879d09cf130f3760a08865913c04d9ff328fad5fChris Lattner // Two-way Conditional Branch. 338536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(&MBB, dl, get(PPC::BCC)) 33918258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 340536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); 341b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 342c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 343c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 344940f83e772ca2007d62faffc83094bd7e8da6401Owen Andersonbool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 345d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 346d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 347d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 348d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 349d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 350940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Not yet supported! 351940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 352d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 353d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 354c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 355d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (MI != MBB.end()) DL = MI->getDebugLoc(); 356d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 357d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == PPC::GPRCRegisterClass) { 358d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 359d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::G8RCRegisterClass) { 360d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 361baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen } else if (DestRC == PPC::F4RCRegisterClass || 362baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen DestRC == PPC::F8RCRegisterClass) { 363baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg); 364d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::CRRCRegisterClass) { 365d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg); 366d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::VRRCRegisterClass) { 367d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 3680404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray } else if (DestRC == PPC::CRBITRCRegisterClass) { 369d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); 370d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else { 371940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Attempt to copy register that is not GPR or FPR 372940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 373d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 374940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson 375940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return true; 376d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 377d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 3784a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingbool 3798e5f2c6f65841542e2a7092553fe42a00048e4c7Dan GohmanPPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 3808e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned SrcReg, bool isKill, 3814a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling int FrameIdx, 3824a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 3834a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const{ 384c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 385f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 386f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR) { 38721b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 388587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 389587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 3904a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling FrameIdx)); 391f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 392f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 393f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 394f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 39521b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 39621b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 397587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R11, 398587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 3994a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling FrameIdx)); 400f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 401f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 402f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR8) { 40321b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 404587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 405587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 406587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 407f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 408f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 409f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 410f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 41121b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 41221b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 413587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::X11, 414587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 415587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 416f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 417f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 41821b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 419587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 420587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 421587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 422f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 42321b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 424587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 425587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 426587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 427f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 4284a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 4294a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 4304a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling // FIXME (64-bit): Enable 43121b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 432587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 433587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 43471a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner FrameIdx)); 4357194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return true; 4367194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } else { 437c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // FIXME: We need a scatch reg here. The trouble with using R0 is that 438c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // it's possible for the stack frame to be so big the save location is 439c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // out of range of immediate offsets, necessitating another register. 440c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // We hack this on Darwin by reserving R2. It's probably broken on Linux 441c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // at the moment. 442c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen 443c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // We need to store the CR in the low 4-bits of the saved value. First, 444c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // issue a MFCR to save all of the CRBits. 445c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 446c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen PPC::R2 : PPC::R0; 447c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg)); 448f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 4497194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // If the saved register wasn't CR0, shift the bits left so that they are 4507194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // in CR0's slot. 4517194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (SrcReg != PPC::CR0) { 4527194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 453c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // rlwinm scratch, scratch, ShiftBits, 0, 31. 454c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 455c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg).addImm(ShiftBits) 456c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addImm(0).addImm(31)); 4577194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 458f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 45921b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 460c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg, 461587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 4627194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIdx)); 4637194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 4640404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray } else if (RC == PPC::CRBITRCRegisterClass) { 4650404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 4660404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // backend currently only uses CR1EQ as an individual bit, this should 4670404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // not cause any bug. If we need other uses of CR bits, the following 4680404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // code may be invalid. 4699348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 4706a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 4716a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 4729348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 4736a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 4746a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 4759348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 4766a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 4776a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 4789348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 4796a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 4806a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 4819348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 4826a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 4836a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 4849348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 4856a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 4866a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 4879348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 4886a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 4896a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 4909348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 4916a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 4926a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 4939348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 4949348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 4958e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 4969348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray PPC::CRRCRegisterClass, NewMIs); 4979348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 498f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 499f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 500f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 501f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // STVX VAL, 0, R0 502f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 503f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 50421b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 505f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 50621b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 507587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, getKillRegState(isKill)) 508587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R0) 509587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R0)); 510f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 511c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 512f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 5137194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return false; 515f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 516f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 517f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 518f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 5197194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 5207194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned SrcReg, bool isKill, int FrameIdx, 521746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 522746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 5238e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 524f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 5257194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5268e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 5278e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5287194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FuncInfo->setSpillsCR(); 5297194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 5307194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 531f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 532f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 533f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 534f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 5354a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingvoid 536d1c321a89ab999b9bb602b0f398ecd4c2022262cBill WendlingPPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 5378e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned DestReg, int FrameIdx, 5384a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 5394a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs)const{ 540f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 541f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR) { 542d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 543d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling DestReg), FrameIdx)); 544f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 545d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 546d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling PPC::R11), FrameIdx)); 547d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 548f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 549f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 550f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR8) { 551d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 552f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 553f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 554d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 555d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling PPC::R11), FrameIdx)); 556d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 557f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 558f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 559d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 560f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 561f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 562d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 563f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 564f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 565c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // FIXME: We need a scatch reg here. The trouble with using R0 is that 566c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // it's possible for the stack frame to be so big the save location is 567c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // out of range of immediate offsets, necessitating another register. 568c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // We hack this on Darwin by reserving R2. It's probably broken on Linux 569c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // at the moment. 570c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 571c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen PPC::R2 : PPC::R0; 572c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 573c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen ScratchReg), FrameIdx)); 574f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 575f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // If the reloaded register isn't CR0, shift the bits right so that they are 576f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // in the right CR's slot. 577f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::CR0) { 578f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 579f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // rlwinm r11, r11, 32-ShiftBits, 0, 31. 580c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 581c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 582c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addImm(31)); 583f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 584f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 585c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 586c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg)); 5870404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray } else if (RC == PPC::CRBITRCRegisterClass) { 5889348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 5899348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 5906a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 5916a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 5929348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 5936a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 5946a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 5959348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 5966a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 5976a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 5989348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 5996a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 6006a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 6019348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 6026a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 6036a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 6049348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 6056a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 6066a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 6079348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 6086a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 6096a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 6109348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 6116a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 6126a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 6139348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 6149348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 615d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 6169348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray PPC::CRRCRegisterClass, NewMIs); 6179348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 618f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 619f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 620f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 621f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // Dest = LVX 0, R0 622f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 623f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 624d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 625f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 626d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 627f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0)); 628f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 629c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 630f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 631f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 632f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 633f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 634f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 6357194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 6367194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned DestReg, int FrameIdx, 637746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 638746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 6398e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 640f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 641c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 642d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (MI != MBB.end()) DL = MI->getDebugLoc(); 643d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 644f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 645f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 646f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 647f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 6480965217e74fe07f1451350a80114ab566ced5de0Evan ChengMachineInstr* 6490965217e74fe07f1451350a80114ab566ced5de0Evan ChengPPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 6508601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 6510965217e74fe07f1451350a80114ab566ced5de0Evan Cheng const MDNode *MDPtr, 6520965217e74fe07f1451350a80114ab566ced5de0Evan Cheng DebugLoc DL) const { 6530965217e74fe07f1451350a80114ab566ced5de0Evan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 6540965217e74fe07f1451350a80114ab566ced5de0Evan Cheng addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 6550965217e74fe07f1451350a80114ab566ced5de0Evan Cheng return &*MIB; 6560965217e74fe07f1451350a80114ab566ced5de0Evan Cheng} 6570965217e74fe07f1451350a80114ab566ced5de0Evan Cheng 65843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 65943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// copy instructions, turning them into load/store instructions. 660c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 661c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *MI, 662c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 663c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 66443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 66543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 66643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 66743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 66843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 66943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 67043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 67143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 67243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 67343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 67443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 67543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 6769f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 6772578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 678d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) 6792578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng .addReg(InReg, 6802578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getKillRegState(isKill) | 6812578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 68243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 68343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 68443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 6859f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 6862578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 687d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) 688587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(OutReg, 689587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling RegState::Define | 6902578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getDeadRegState(isDead) | 6912578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 69243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 69343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 69443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if ((Opc == PPC::OR8 && 69543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 69643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 69743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 6989f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 6992578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 700d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) 7012578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng .addReg(InReg, 7022578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getKillRegState(isKill) | 7032578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 70443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 70543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 70643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 7079f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 7082578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 709d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) 710587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(OutReg, 711587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling RegState::Define | 7122578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getDeadRegState(isDead) | 7132578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 7149f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng FrameIndex); 71543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 716baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) { 717243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen // The register may be F4RC or F8RC, and that determines the memory op. 718243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen unsigned OrigReg = MI->getOperand(OpNum).getReg(); 719243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen // We cannot tell the register class from a physreg alone. 720243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(OrigReg)) 721243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen return NULL; 722243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg); 723243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen const bool is64 = RC == PPC::F8RCRegisterClass; 724243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen 72543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 72643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 7279f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 7282578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 729243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), 730243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen get(is64 ? PPC::STFD : PPC::STFS)) 7312578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng .addReg(InReg, 7322578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getKillRegState(isKill) | 7332578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 73443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 73543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 73643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 7379f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 7382578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 739243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), 740243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen get(is64 ? PPC::LFD : PPC::LFS)) 741587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(OutReg, 742587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling RegState::Define | 7432578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getDeadRegState(isDead) | 7442578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getUndefRegState(isUndef)), 7459f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng FrameIndex); 74643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 74743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 74843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 74943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 75043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 75143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 7528e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohmanbool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 7538e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const { 75443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return false; 75543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 75643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 75743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 75843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 75943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 76043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 76143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 76243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 76343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else if ((Opc == PPC::OR8 && 76443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 76543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 766baafcbb4dbbda50d5b811b6888c77fd64d073865Jakob Stoklund Olesen else if (Opc == PPC::FMR || Opc == PPC::FMRSD) 76743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 76843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 76943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 77043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 77143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 772f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 773c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo:: 77444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen AndersonReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 7757c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 7767c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner // Leave the CR# the same, but invert the condition. 77718258c640466274c26e89016e361ec411ff78520Chris Lattner Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 7787c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 779c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 78052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 78152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// GetInstSize - Return the number of bytes of code the specified 78252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// instruction may be. This returns the maximum number of bytes. 78352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// 78452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffrayunsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 78552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray switch (MI->getOpcode()) { 78652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray case PPC::INLINEASM: { // Inline Asm: Variable size. 78752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const MachineFunction *MF = MI->getParent()->getParent(); 78852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const char *AsmStr = MI->getOperand(0).getSymbolName(); 789af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 79052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 7914406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::DBG_LABEL: 7924406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::EH_LABEL: 7934406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::GC_LABEL: 794375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case PPC::DBG_VALUE: 79552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 79652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray default: 79752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 4; // PowerPC instructions are all 4 bytes 79852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 79952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray} 800