| 621b77ade2ff46d1d8594bddee6931b2f4a14706 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC Freescale e500mc and e5500 subtargets.
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7164288c3eb52e20454fc757440f867f04eb13a4 |
|
19-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement PPCInstrInfo::isCoalescableExtInstr().
The PPC::EXTSW instruction preserves the low 32 bits of its input, just
like some of the x86 instructions. Use it to reduce register pressure
when the low 32 bits have multiple uses.
This requires a small change to PeepholeOptimizer since EXTSW takes a
64-bit input register.
This is related to PR5997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7255d2a8084cb6aa96ea0e5f30acfff76df04ee8 |
|
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Enable PPC CTR loop formation by default.
Thanks to Jakob's help, this now causes no new test suite failures!
Over the entire test suite, this gives an average 1% speedup. The largest speedups are:
SingleSource/Benchmarks/Misc/pi - 108%
SingleSource/Benchmarks/CoyoteBench/lpbench - 54%
MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50%
SingleSource/Benchmarks/Shootout/ary3 - 32%
SingleSource/Benchmarks/Shootout-C++/matrix - 30%
The largest slowdowns are:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30%
MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22%
MultiSource/Applications/d/make_dparser - -14%
SingleSource/Benchmarks/Shootout-C++/ary - -13%
In light of these slowdowns, additional profiling work is obviously needed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 09fdc7baae1b6905fe18df48e2278e74d4e39ccd |
|
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Disable the PPC CTR-Loops pass by default.
The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 99f823f94374917174f96a7689955b8463db6816 |
|
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.
This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c909950c384e8234a7b3c5a76b7f79e3f7012ceb |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4d989ac93ce608057fb6b13a4068264ab037ecd5 |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 5b00ceaeeabff8c25abb09926343c3fcb06053d8 |
|
31-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 234bb38d6c421ea22229087a9835afe99e531276 |
|
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7ad6b7d35978e1bb89de90aa732cf2f57377d69d |
|
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
64-bit LR8 load should use X11 not R11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d21e930eac3d99dd77ee33ea5826700b4bc97ae8 |
|
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add RESTORE_CR and support CR unspills
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 3fd0018af1b692cabfa5a002bf41f1e756aa9dde |
|
05-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
enable PPC register scavenging by default (update tests and remove some FIXMEs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 64c34e253563a8ba6b41fbce2bb020632cf65961 |
|
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
update PPC 940 hazard rec. to function in postRA mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 768c65f677af3f05c2e94982043f90a1bfaceda5 |
|
22-Nov-2011 |
Hal Finkel <hfinkel@anl.gov> |
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 978e0dfe46e481bfb1281e683aa308329e879e95 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 0839033cbca20a1d1348bdf1c9f63fb263b248a6 |
|
08-Nov-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
PPCInstrInfo.cpp: Fix one "unused" warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| ed8db320af68556de5fcfe2cbec688003acc33f5 |
|
21-Oct-2011 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 5bdab4a63cab2ed2f96a3490fa2349550da7c7f9 |
|
20-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Disable the PPC hazard recognizer. It currently only supports
top-down scheduling and top-down scheduling is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 |
|
17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC 440 scheduler and some associated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 01faf432d9d81212b492f326594d43a951fe64f0 |
|
04-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach PPCInstrInfo to handle sub-classes.
This has already been done for most other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
|
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 966aeb5788c242cfaca35c56c0ddc0ff778d4376 |
|
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor PPC target to separate MC routines from Target routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
|
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d5b03f252c0db6b49a242abab63d7c5a260fceae |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
|
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
|
17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| a90c3f600d5bea9e01722d7df5752f9adfcf4635 |
|
16-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit COPY instead of FMR/FMSD instructions for floating point conversion on
PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7a79fcb55b83b8b98b9853c390cc5bf8ce382dd3 |
|
16-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory
operands.
Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 600f171486708734e2b9c9c617528cfc51c16850 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 27689b0affee8fb1bfbef11dcc84287b7757cfe8 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
|
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 5f07d5224ddc32f405d7e19de8e58e91ab2816bc |
|
20-May-2010 |
Dale Johannesen <dalej@apple.com> |
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 9f2cda73e470673ab63509adc9d096b0a1d13c54 |
|
05-May-2010 |
Dan Gohman <gohman@apple.com> |
No-ops emitted for scheduling don't correspond with anything in the
user's source, so don't arbitrarily assign them a debug location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
|
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 0965217e74fe07f1451350a80114ab566ced5de0 |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add PPC specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 82bcd236937b378e56e46bdde9c17a3ea3377068 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 375be7730a6f3dee7a6dc319ee6c355a11ac99ad |
|
07-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 93d6a7e9c21204c52d6efec6c672163e7de79660 |
|
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| baafcbb4dbbda50d5b811b6888c77fd64d073865 |
|
26-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Merge PPC instructions FMRS and FMRD into a single FMR instruction.
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.
Also allow folding of memory operands on FMRSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 243296690ec78fc918762bd73896b09e26537f47 |
|
26-Feb-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.
Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.
X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c12da8d30a1394847ee4608fcd54daa24b889b37 |
|
12-Feb-2010 |
Dale Johannesen <dalej@apple.com> |
When save/restoring CR at prolog/epilog, in a large
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.
SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.
Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 |
|
22-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
|
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
|
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 6a3a1ba97e996bfdc061f9a51bd4cf4915962913 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Various small changes related to the Condition Register on PowerPC.
Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 2578ba26e72e36dde64be0f52a2788480aad3378 |
|
01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
|
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 82ae933e55839713ea039e7c6353483b14dc5724 |
|
09-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
PPC::B and PPC::BCC's target operand may be an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 97357614b5957cc167c261d3be54713802715d9a |
|
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 536a2f1f8467a17f6d145bd83f25faae1f689839 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 21b5541814d57d0a31f353948e4e933dbb1af6a4 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d1c321a89ab999b9bb602b0f398ecd4c2022262c |
|
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
|
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
|
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 014278e6a11fa0767853b831e5bf51b95bf541c5 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
|
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
|
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 9f1c8317a4676945b4961ddb9827ef2412551620 |
|
03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
|
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
|
16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
|
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 71a2cb25ebc818383dd0f80475bc166f834e8d99 |
|
20-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
detabify llvm, patch by Mike Stump!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4a66e9a57e679b4f3243bf2061daf53c70102030 |
|
10-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| cb341de0e238f80dabf3da7b4f2aad58de6914bd |
|
10-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
fix 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 9348c69dcfe1aa1e7f92752a18222dcfbcd96214 |
|
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Stylistic modifications. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 0404cd97e4f6ebfe4f8057d4e21119d77654dff2 |
|
10-Mar-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Add description of individual bits in CR. This fix PR1765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 880d0f6018b6928bdcad291be60c801238619955 |
|
05-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Use a command-line option to turn register scavenging on/off for PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7194aaf738a1b89441635340403f1c5b06ae18ef |
|
03-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| a4d16a1f0dcdd1ab2862737105f900e2c577532d |
|
13-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
commuteInstr() can now commute non-ssa machine instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
|
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| cc8cd0cbf12c12916d4b38ef0de5be5501c8270e |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
|
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 264e6fec9f3962cb269031d6d84cee9f896e0286 |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 641055225092833197efe8e5bce01d50bcf1daae |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
|
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| f73823000e2d5d6e1cf65bdf5a107297e18d35fb |
|
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
into MachineOperand::print.
- Change various set* methods for register flags to take a bool
for the value to set it to. Remove unset* methods.
- Group methods more logically by operand flavor in MachineOperand.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
|
30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
|
07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 13e8b51e3ec014c5d7ae83afdf3b8fd29c3a461d |
|
13-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Handle blocks with 2 unconditional branches in AnalyzeBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 |
|
08-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 126f17a17625876adb63f06d043fc1b1e4f0361c |
|
21-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| b5cdaa257e167a08a8a54ea9249d847ccc415ce0 |
|
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 1e341729dd003ca33ecea4abf13134f20062c5f8 |
|
25-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 18258c640466274c26e89016e361ec411ff78520 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 289c2d5f4566d8d7722e3934f4763d3df92886f3 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
rename PPC::COND_BRANCH to PPC::BCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| df4ed6350b2a51f71c0980e86c9078f4046ea706 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
start using PPC predicates more consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 6ce7dc2a97260eea5fba414332796464912b9359 |
|
15-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Properly transfer kill / dead info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 |
|
14-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| ef13982aa7f3e57e82cd48370e79033dff0da295 |
|
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement the BlockHasNoFallThrough hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7c4fe259f8bfeae542cfef25c1f1e9b1ff25a39b |
|
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement support for branch reversal, fix a bug in branch analysis.
This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 879d09cf130f3760a08865913c04d9ff328fad5f |
|
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Simplify code, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 54108068b71a7dbc48f4ebf1b2d7d87ca541070a |
|
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement support for inserting a cond branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 2dc7723474c54efcbcac6265dad0a7271902f1a5 |
|
17-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
add support for inserting an uncond branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| c50e2bcdf7bff1f9681ab80e52691f274950fab5 |
|
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement branch inspection/modification methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 804e06704261f233111913a047ef7f7dec1b8725 |
|
11-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| b410dc99774d52b4491750dab10b91cca1d661d8 |
|
21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| b1d26f66658cff3ceb7d44a72fbc8c8e975532f9 |
|
17-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the getPointerRegClass method, which is required for the ptr_rc
magic to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| e53f4a055f74bded20d6129b4724ddd17fd199f6 |
|
04-May-2006 |
Chris Lattner <sabre@nondot.org> |
Move some methods out of MachineInstr into MachineOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 9c09c9ec9dab61450800b42cbf746164aa076b88 |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
teach the ppc backend how to spill/reload vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 335fd3c7c2057b4e5fedb3161df44d7bc1759791 |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for copying registers. still needed: spilling and reloading them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| bbf1c72d51a77bf54c9c684b90a78e59f0b70b2f |
|
06-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement TII::insertNoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 3b478b31e297208ef2c9f74750a8a603eb3726fb |
|
02-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 6524287c53cf727a8ef33517403fcb1bbd7adff9 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
implement isStoreToStackSlot for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 408396014742a05cad1c91949d2226169e3f9d80 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 14c09b81ead8fe8b754fca2d0a8237cb810b37d6 |
|
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
teach ppc backend these are copies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 2668959b8879097db368aec7d76c455260abc75b |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 4c7b43b43fdf943c7298718e15ab5d6dfe345be7 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2 |
|
07-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 919c032fa4511468aadc6f50d6ed9c50890710b3 |
|
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 043870dd85ea41e8972c304b122070a417c8a4bc |
|
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the code generator that rlwimi is commutable if the rotate amount
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 |
|
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
|
| 7af0248af47fbd86ec65d308adda22ec367accc4 |
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12-Apr-2005 |
Nate Begeman <natebegeman@mac.com> |
Initial support for allocation condition registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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| cb90de37a720b0b00d6303b49b8df6d5ac5f34f9 |
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08-Oct-2004 |
Nate Begeman <natebegeman@mac.com> |
Add ori reg, reg, 0 as a move instruction. This can be generated from
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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| f2ccb77ee9d8ab35866dae111fa36929689c7511 |
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17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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