PPCInstrInfo.cpp revision 31d157ae1ac2cd9c787dc3c1d28e64c682803844 
1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCTargetMachine.h"
19#include "PPCHazardRecognizers.h"
20#include "MCTargetDesc/PPCPredicates.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/TargetRegistry.h"
29#include "llvm/Support/raw_ostream.h"
30#include "llvm/ADT/STLExtras.h"
31
32#define GET_INSTRINFO_CTOR
33#include "PPCGenInstrInfo.inc"
34
35namespace llvm {
36extern cl::opt<bool> DisablePPC32RS;
37extern cl::opt<bool> DisablePPC64RS;
38}
39
40using namespace llvm;
41
42PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
45
46/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47/// this target when scheduling the DAG.
48ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49  const TargetMachine *TM,
50  const ScheduleDAG *DAG) const {
51  unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52  if (Directive == PPC::DIR_440) {
53    const InstrItineraryData *II = TM->getInstrItineraryData();
54    return new PPCHazardRecognizer440(II, DAG);
55  }
56
57  return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
58}
59
60/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
61/// to use for this target when scheduling the DAG.
62ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
63  const InstrItineraryData *II,
64  const ScheduleDAG *DAG) const {
65  unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
66
67  // Most subtargets use a PPC970 recognizer.
68  if (Directive != PPC::DIR_440) {
69    const TargetInstrInfo *TII = TM.getInstrInfo();
70    assert(TII && "No InstrInfo?");
71
72    return new PPCHazardRecognizer970(*TII);
73  }
74
75  return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
76}
77unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
78                                           int &FrameIndex) const {
79  switch (MI->getOpcode()) {
80  default: break;
81  case PPC::LD:
82  case PPC::LWZ:
83  case PPC::LFS:
84  case PPC::LFD:
85    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
86        MI->getOperand(2).isFI()) {
87      FrameIndex = MI->getOperand(2).getIndex();
88      return MI->getOperand(0).getReg();
89    }
90    break;
91  }
92  return 0;
93}
94
95unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96                                          int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::STD:
100  case PPC::STW:
101  case PPC::STFS:
102  case PPC::STFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113// commuteInstruction - We can commute rlwimi instructions, but only if the
114// rotate amt is zero.  We also have to munge the immediates a bit.
115MachineInstr *
116PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
117  MachineFunction &MF = *MI->getParent()->getParent();
118
119  // Normal instructions can be commuted the obvious way.
120  if (MI->getOpcode() != PPC::RLWIMI)
121    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
122
123  // Cannot commute if it has a non-zero rotate count.
124  if (MI->getOperand(3).getImm() != 0)
125    return 0;
126
127  // If we have a zero rotate count, we have:
128  //   M = mask(MB,ME)
129  //   Op0 = (Op1 & ~M) | (Op2 & M)
130  // Change this to:
131  //   M = mask((ME+1)&31, (MB-1)&31)
132  //   Op0 = (Op2 & ~M) | (Op1 & M)
133
134  // Swap op1/op2
135  unsigned Reg0 = MI->getOperand(0).getReg();
136  unsigned Reg1 = MI->getOperand(1).getReg();
137  unsigned Reg2 = MI->getOperand(2).getReg();
138  bool Reg1IsKill = MI->getOperand(1).isKill();
139  bool Reg2IsKill = MI->getOperand(2).isKill();
140  bool ChangeReg0 = false;
141  // If machine instrs are no longer in two-address forms, update
142  // destination register as well.
143  if (Reg0 == Reg1) {
144    // Must be two address instruction!
145    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
146           "Expecting a two-address instruction!");
147    Reg2IsKill = false;
148    ChangeReg0 = true;
149  }
150
151  // Masks.
152  unsigned MB = MI->getOperand(4).getImm();
153  unsigned ME = MI->getOperand(5).getImm();
154
155  if (NewMI) {
156    // Create a new instruction.
157    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
158    bool Reg0IsDead = MI->getOperand(0).isDead();
159    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
160      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
161      .addReg(Reg2, getKillRegState(Reg2IsKill))
162      .addReg(Reg1, getKillRegState(Reg1IsKill))
163      .addImm((ME+1) & 31)
164      .addImm((MB-1) & 31);
165  }
166
167  if (ChangeReg0)
168    MI->getOperand(0).setReg(Reg2);
169  MI->getOperand(2).setReg(Reg1);
170  MI->getOperand(1).setReg(Reg2);
171  MI->getOperand(2).setIsKill(Reg1IsKill);
172  MI->getOperand(1).setIsKill(Reg2IsKill);
173
174  // Swap the mask around.
175  MI->getOperand(4).setImm((ME+1) & 31);
176  MI->getOperand(5).setImm((MB-1) & 31);
177  return MI;
178}
179
180void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
181                              MachineBasicBlock::iterator MI) const {
182  DebugLoc DL;
183  BuildMI(MBB, MI, DL, get(PPC::NOP));
184}
185
186
187// Branch analysis.
188bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
189                                 MachineBasicBlock *&FBB,
190                                 SmallVectorImpl<MachineOperand> &Cond,
191                                 bool AllowModify) const {
192  // If the block has no terminators, it just falls into the block after it.
193  MachineBasicBlock::iterator I = MBB.end();
194  if (I == MBB.begin())
195    return false;
196  --I;
197  while (I->isDebugValue()) {
198    if (I == MBB.begin())
199      return false;
200    --I;
201  }
202  if (!isUnpredicatedTerminator(I))
203    return false;
204
205  // Get the last instruction in the block.
206  MachineInstr *LastInst = I;
207
208  // If there is only one terminator instruction, process it.
209  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
210    if (LastInst->getOpcode() == PPC::B) {
211      if (!LastInst->getOperand(0).isMBB())
212        return true;
213      TBB = LastInst->getOperand(0).getMBB();
214      return false;
215    } else if (LastInst->getOpcode() == PPC::BCC) {
216      if (!LastInst->getOperand(2).isMBB())
217        return true;
218      // Block ends with fall-through condbranch.
219      TBB = LastInst->getOperand(2).getMBB();
220      Cond.push_back(LastInst->getOperand(0));
221      Cond.push_back(LastInst->getOperand(1));
222      return false;
223    }
224    // Otherwise, don't know what this is.
225    return true;
226  }
227
228  // Get the instruction before it if it's a terminator.
229  MachineInstr *SecondLastInst = I;
230
231  // If there are three terminators, we don't know what sort of block this is.
232  if (SecondLastInst && I != MBB.begin() &&
233      isUnpredicatedTerminator(--I))
234    return true;
235
236  // If the block ends with PPC::B and PPC:BCC, handle it.
237  if (SecondLastInst->getOpcode() == PPC::BCC &&
238      LastInst->getOpcode() == PPC::B) {
239    if (!SecondLastInst->getOperand(2).isMBB() ||
240        !LastInst->getOperand(0).isMBB())
241      return true;
242    TBB =  SecondLastInst->getOperand(2).getMBB();
243    Cond.push_back(SecondLastInst->getOperand(0));
244    Cond.push_back(SecondLastInst->getOperand(1));
245    FBB = LastInst->getOperand(0).getMBB();
246    return false;
247  }
248
249  // If the block ends with two PPC:Bs, handle it.  The second one is not
250  // executed, so remove it.
251  if (SecondLastInst->getOpcode() == PPC::B &&
252      LastInst->getOpcode() == PPC::B) {
253    if (!SecondLastInst->getOperand(0).isMBB())
254      return true;
255    TBB = SecondLastInst->getOperand(0).getMBB();
256    I = LastInst;
257    if (AllowModify)
258      I->eraseFromParent();
259    return false;
260  }
261
262  // Otherwise, can't handle this.
263  return true;
264}
265
266unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
267  MachineBasicBlock::iterator I = MBB.end();
268  if (I == MBB.begin()) return 0;
269  --I;
270  while (I->isDebugValue()) {
271    if (I == MBB.begin())
272      return 0;
273    --I;
274  }
275  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
276    return 0;
277
278  // Remove the branch.
279  I->eraseFromParent();
280
281  I = MBB.end();
282
283  if (I == MBB.begin()) return 1;
284  --I;
285  if (I->getOpcode() != PPC::BCC)
286    return 1;
287
288  // Remove the branch.
289  I->eraseFromParent();
290  return 2;
291}
292
293unsigned
294PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
295                           MachineBasicBlock *FBB,
296                           const SmallVectorImpl<MachineOperand> &Cond,
297                           DebugLoc DL) const {
298  // Shouldn't be a fall through.
299  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
300  assert((Cond.size() == 2 || Cond.size() == 0) &&
301         "PPC branch conditions have two components!");
302
303  // One-way branch.
304  if (FBB == 0) {
305    if (Cond.empty())   // Unconditional branch
306      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
307    else                // Conditional branch
308      BuildMI(&MBB, DL, get(PPC::BCC))
309        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
310    return 1;
311  }
312
313  // Two-way Conditional Branch.
314  BuildMI(&MBB, DL, get(PPC::BCC))
315    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
316  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
317  return 2;
318}
319
320void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
321                               MachineBasicBlock::iterator I, DebugLoc DL,
322                               unsigned DestReg, unsigned SrcReg,
323                               bool KillSrc) const {
324  unsigned Opc;
325  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
326    Opc = PPC::OR;
327  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
328    Opc = PPC::OR8;
329  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
330    Opc = PPC::FMR;
331  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
332    Opc = PPC::MCRF;
333  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
334    Opc = PPC::VOR;
335  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
336    Opc = PPC::CROR;
337  else
338    llvm_unreachable("Impossible reg-to-reg copy");
339
340  const MCInstrDesc &MCID = get(Opc);
341  if (MCID.getNumOperands() == 3)
342    BuildMI(MBB, I, DL, MCID, DestReg)
343      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
344  else
345    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
346}
347
348// This function returns true if a CR spill is necessary and false otherwise.
349bool
350PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
351                                  unsigned SrcReg, bool isKill,
352                                  int FrameIdx,
353                                  const TargetRegisterClass *RC,
354                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
355  DebugLoc DL;
356  if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
357    if (SrcReg != PPC::LR) {
358      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
359                                         .addReg(SrcReg,
360                                                 getKillRegState(isKill)),
361                                         FrameIdx));
362    } else {
363      // FIXME: this spills LR immediately to memory in one step.  To do this,
364      // we use R11, which we know cannot be used in the prolog/epilog.  This is
365      // a hack.
366      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
367      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
368                                         .addReg(PPC::R11,
369                                                 getKillRegState(isKill)),
370                                         FrameIdx));
371    }
372  } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
373    if (SrcReg != PPC::LR8) {
374      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
375                                         .addReg(SrcReg,
376                                                 getKillRegState(isKill)),
377                                         FrameIdx));
378    } else {
379      // FIXME: this spills LR immediately to memory in one step.  To do this,
380      // we use X11, which we know cannot be used in the prolog/epilog.  This is
381      // a hack.
382      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
383      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
384                                         .addReg(PPC::X11,
385                                                 getKillRegState(isKill)),
386                                         FrameIdx));
387    }
388  } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
389    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
390                                       .addReg(SrcReg,
391                                               getKillRegState(isKill)),
392                                       FrameIdx));
393  } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
394    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
395                                       .addReg(SrcReg,
396                                               getKillRegState(isKill)),
397                                       FrameIdx));
398  } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
399    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
400        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
401      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
402                                         .addReg(SrcReg,
403                                                 getKillRegState(isKill)),
404                                         FrameIdx));
405      return true;
406    } else {
407      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
408      // it's possible for the stack frame to be so big the save location is
409      // out of range of immediate offsets, necessitating another register.
410      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
411      // at the moment.
412
413      bool is64Bit = TM.getSubtargetImpl()->isPPC64();
414      // We need to store the CR in the low 4-bits of the saved value.  First,
415      // issue a MFCR to save all of the CRBits.
416      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
417                              (is64Bit ? PPC::X2 : PPC::R2) :
418                              (is64Bit ? PPC::X0 : PPC::R0);
419      NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
420                                             PPC::MFCRpseud), ScratchReg)
421                               .addReg(SrcReg, getKillRegState(isKill)));
422
423      // If the saved register wasn't CR0, shift the bits left so that they are
424      // in CR0's slot.
425      if (SrcReg != PPC::CR0) {
426        unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
427        // rlwinm scratch, scratch, ShiftBits, 0, 31.
428        NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
429                           PPC::RLWINM), ScratchReg)
430                       .addReg(ScratchReg).addImm(ShiftBits)
431                       .addImm(0).addImm(31));
432      }
433
434      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
435                                           PPC::STW8 : PPC::STW))
436                                         .addReg(ScratchReg,
437                                                 getKillRegState(isKill)),
438                                         FrameIdx));
439    }
440  } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
441    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
442    // backend currently only uses CR1EQ as an individual bit, this should
443    // not cause any bug. If we need other uses of CR bits, the following
444    // code may be invalid.
445    unsigned Reg = 0;
446    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
447        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
448      Reg = PPC::CR0;
449    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
450             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
451      Reg = PPC::CR1;
452    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
453             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
454      Reg = PPC::CR2;
455    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
456             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
457      Reg = PPC::CR3;
458    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
459             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
460      Reg = PPC::CR4;
461    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
462             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
463      Reg = PPC::CR5;
464    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
465             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
466      Reg = PPC::CR6;
467    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
468             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
469      Reg = PPC::CR7;
470
471    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
472                               PPC::CRRCRegisterClass, NewMIs);
473
474  } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
475    // We don't have indexed addressing for vector loads.  Emit:
476    // R0 = ADDI FI#
477    // STVX VAL, 0, R0
478    //
479    // FIXME: We use R0 here, because it isn't available for RA.
480    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
481                                       FrameIdx, 0, 0));
482    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
483                     .addReg(SrcReg, getKillRegState(isKill))
484                     .addReg(PPC::R0)
485                     .addReg(PPC::R0));
486  } else {
487    llvm_unreachable("Unknown regclass!");
488  }
489
490  return false;
491}
492
493void
494PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
495                                  MachineBasicBlock::iterator MI,
496                                  unsigned SrcReg, bool isKill, int FrameIdx,
497                                  const TargetRegisterClass *RC,
498                                  const TargetRegisterInfo *TRI) const {
499  MachineFunction &MF = *MBB.getParent();
500  SmallVector<MachineInstr*, 4> NewMIs;
501
502  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
503    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
504    FuncInfo->setSpillsCR();
505  }
506
507  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
508    MBB.insert(MI, NewMIs[i]);
509
510  const MachineFrameInfo &MFI = *MF.getFrameInfo();
511  MachineMemOperand *MMO =
512    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
513                            MachineMemOperand::MOStore,
514                            MFI.getObjectSize(FrameIdx),
515                            MFI.getObjectAlignment(FrameIdx));
516  NewMIs.back()->addMemOperand(MF, MMO);
517}
518
519bool
520PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
521                                   unsigned DestReg, int FrameIdx,
522                                   const TargetRegisterClass *RC,
523                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
524  if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
525    if (DestReg != PPC::LR) {
526      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
527                                                 DestReg), FrameIdx));
528    } else {
529      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
530                                                 PPC::R11), FrameIdx));
531      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
532    }
533  } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
534    if (DestReg != PPC::LR8) {
535      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
536                                         FrameIdx));
537    } else {
538      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
539                                                 PPC::X11), FrameIdx));
540      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
541    }
542  } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
543    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
544                                       FrameIdx));
545  } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
546    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
547                                       FrameIdx));
548  } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
549    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
550        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
551      NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
552                                                 get(PPC::RESTORE_CR), DestReg)
553                                         , FrameIdx));
554      return true;
555    } else {
556      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
557      // it's possible for the stack frame to be so big the save location is
558      // out of range of immediate offsets, necessitating another register.
559      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
560      // at the moment.
561      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
562                                                            PPC::R2 : PPC::R0;
563      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
564                                         ScratchReg), FrameIdx));
565
566      // If the reloaded register isn't CR0, shift the bits right so that they are
567      // in the right CR's slot.
568      if (DestReg != PPC::CR0) {
569        unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
570        // rlwinm r11, r11, 32-ShiftBits, 0, 31.
571        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
572                      .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
573                      .addImm(31));
574      }
575
576      NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
577                         PPC::MTCRF8 : PPC::MTCRF), DestReg)
578                       .addReg(ScratchReg));
579    }
580  } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
581
582    unsigned Reg = 0;
583    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
584        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
585      Reg = PPC::CR0;
586    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
587             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
588      Reg = PPC::CR1;
589    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
590             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
591      Reg = PPC::CR2;
592    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
593             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
594      Reg = PPC::CR3;
595    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
596             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
597      Reg = PPC::CR4;
598    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
599             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
600      Reg = PPC::CR5;
601    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
602             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
603      Reg = PPC::CR6;
604    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
605             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
606      Reg = PPC::CR7;
607
608    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
609                                PPC::CRRCRegisterClass, NewMIs);
610
611  } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
612    // We don't have indexed addressing for vector loads.  Emit:
613    // R0 = ADDI FI#
614    // Dest = LVX 0, R0
615    //
616    // FIXME: We use R0 here, because it isn't available for RA.
617    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
618                                       FrameIdx, 0, 0));
619    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
620                     .addReg(PPC::R0));
621  } else {
622    llvm_unreachable("Unknown regclass!");
623  }
624
625  return false;
626}
627
628void
629PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
630                                   MachineBasicBlock::iterator MI,
631                                   unsigned DestReg, int FrameIdx,
632                                   const TargetRegisterClass *RC,
633                                   const TargetRegisterInfo *TRI) const {
634  MachineFunction &MF = *MBB.getParent();
635  SmallVector<MachineInstr*, 4> NewMIs;
636  DebugLoc DL;
637  if (MI != MBB.end()) DL = MI->getDebugLoc();
638  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
639    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
640    FuncInfo->setSpillsCR();
641  }
642  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
643    MBB.insert(MI, NewMIs[i]);
644
645  const MachineFrameInfo &MFI = *MF.getFrameInfo();
646  MachineMemOperand *MMO =
647    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
648                            MachineMemOperand::MOLoad,
649                            MFI.getObjectSize(FrameIdx),
650                            MFI.getObjectAlignment(FrameIdx));
651  NewMIs.back()->addMemOperand(MF, MMO);
652}
653
654MachineInstr*
655PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
656                                       int FrameIx, uint64_t Offset,
657                                       const MDNode *MDPtr,
658                                       DebugLoc DL) const {
659  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
660  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
661  return &*MIB;
662}
663
664bool PPCInstrInfo::
665ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
666  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
667  // Leave the CR# the same, but invert the condition.
668  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
669  return false;
670}
671
672/// GetInstSize - Return the number of bytes of code the specified
673/// instruction may be.  This returns the maximum number of bytes.
674///
675unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
676  switch (MI->getOpcode()) {
677  case PPC::INLINEASM: {       // Inline Asm: Variable size.
678    const MachineFunction *MF = MI->getParent()->getParent();
679    const char *AsmStr = MI->getOperand(0).getSymbolName();
680    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
681  }
682  case PPC::PROLOG_LABEL:
683  case PPC::EH_LABEL:
684  case PPC::GC_LABEL:
685  case PPC::DBG_VALUE:
686    return 0;
687  default:
688    return 4; // PowerPC instructions are all 4 bytes
689  }
690}
691