PPCInstrInfo.cpp revision 7a79fcb55b83b8b98b9853c390cc5bf8ce382dd3 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/MC/MCAsmInfo.h"
30
31namespace llvm {
32extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
33extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
34}
35
36using namespace llvm;
37
38PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
39  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
40    RI(*TM.getSubtargetImpl(), *this) {}
41
42bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
43                               unsigned& sourceReg,
44                               unsigned& destReg,
45                               unsigned& sourceSubIdx,
46                               unsigned& destSubIdx) const {
47  sourceSubIdx = destSubIdx = 0; // No sub-registers.
48
49  unsigned oc = MI.getOpcode();
50  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
51      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
52    assert(MI.getNumOperands() >= 3 &&
53           MI.getOperand(0).isReg() &&
54           MI.getOperand(1).isReg() &&
55           MI.getOperand(2).isReg() &&
56           "invalid PPC OR instruction!");
57    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
58      sourceReg = MI.getOperand(1).getReg();
59      destReg = MI.getOperand(0).getReg();
60      return true;
61    }
62  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
63    assert(MI.getNumOperands() >= 3 &&
64           MI.getOperand(0).isReg() &&
65           MI.getOperand(2).isImm() &&
66           "invalid PPC ADDI instruction!");
67    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
68      sourceReg = MI.getOperand(1).getReg();
69      destReg = MI.getOperand(0).getReg();
70      return true;
71    }
72  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
73    assert(MI.getNumOperands() >= 3 &&
74           MI.getOperand(0).isReg() &&
75           MI.getOperand(1).isReg() &&
76           MI.getOperand(2).isImm() &&
77           "invalid PPC ORI instruction!");
78    if (MI.getOperand(2).getImm() == 0) {
79      sourceReg = MI.getOperand(1).getReg();
80      destReg = MI.getOperand(0).getReg();
81      return true;
82    }
83  } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC FMR instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
92    assert(MI.getNumOperands() >= 2 &&
93           MI.getOperand(0).isReg() &&
94           MI.getOperand(1).isReg() &&
95           "invalid PPC MCRF instruction");
96    sourceReg = MI.getOperand(1).getReg();
97    destReg = MI.getOperand(0).getReg();
98    return true;
99  }
100  return false;
101}
102
103unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
104                                           int &FrameIndex) const {
105  switch (MI->getOpcode()) {
106  default: break;
107  case PPC::LD:
108  case PPC::LWZ:
109  case PPC::LFS:
110  case PPC::LFD:
111    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
112        MI->getOperand(2).isFI()) {
113      FrameIndex = MI->getOperand(2).getIndex();
114      return MI->getOperand(0).getReg();
115    }
116    break;
117  }
118  return 0;
119}
120
121unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
122                                          int &FrameIndex) const {
123  switch (MI->getOpcode()) {
124  default: break;
125  case PPC::STD:
126  case PPC::STW:
127  case PPC::STFS:
128  case PPC::STFD:
129    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
130        MI->getOperand(2).isFI()) {
131      FrameIndex = MI->getOperand(2).getIndex();
132      return MI->getOperand(0).getReg();
133    }
134    break;
135  }
136  return 0;
137}
138
139// commuteInstruction - We can commute rlwimi instructions, but only if the
140// rotate amt is zero.  We also have to munge the immediates a bit.
141MachineInstr *
142PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
143  MachineFunction &MF = *MI->getParent()->getParent();
144
145  // Normal instructions can be commuted the obvious way.
146  if (MI->getOpcode() != PPC::RLWIMI)
147    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
148
149  // Cannot commute if it has a non-zero rotate count.
150  if (MI->getOperand(3).getImm() != 0)
151    return 0;
152
153  // If we have a zero rotate count, we have:
154  //   M = mask(MB,ME)
155  //   Op0 = (Op1 & ~M) | (Op2 & M)
156  // Change this to:
157  //   M = mask((ME+1)&31, (MB-1)&31)
158  //   Op0 = (Op2 & ~M) | (Op1 & M)
159
160  // Swap op1/op2
161  unsigned Reg0 = MI->getOperand(0).getReg();
162  unsigned Reg1 = MI->getOperand(1).getReg();
163  unsigned Reg2 = MI->getOperand(2).getReg();
164  bool Reg1IsKill = MI->getOperand(1).isKill();
165  bool Reg2IsKill = MI->getOperand(2).isKill();
166  bool ChangeReg0 = false;
167  // If machine instrs are no longer in two-address forms, update
168  // destination register as well.
169  if (Reg0 == Reg1) {
170    // Must be two address instruction!
171    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
172           "Expecting a two-address instruction!");
173    Reg2IsKill = false;
174    ChangeReg0 = true;
175  }
176
177  // Masks.
178  unsigned MB = MI->getOperand(4).getImm();
179  unsigned ME = MI->getOperand(5).getImm();
180
181  if (NewMI) {
182    // Create a new instruction.
183    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
184    bool Reg0IsDead = MI->getOperand(0).isDead();
185    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
186      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
187      .addReg(Reg2, getKillRegState(Reg2IsKill))
188      .addReg(Reg1, getKillRegState(Reg1IsKill))
189      .addImm((ME+1) & 31)
190      .addImm((MB-1) & 31);
191  }
192
193  if (ChangeReg0)
194    MI->getOperand(0).setReg(Reg2);
195  MI->getOperand(2).setReg(Reg1);
196  MI->getOperand(1).setReg(Reg2);
197  MI->getOperand(2).setIsKill(Reg1IsKill);
198  MI->getOperand(1).setIsKill(Reg2IsKill);
199
200  // Swap the mask around.
201  MI->getOperand(4).setImm((ME+1) & 31);
202  MI->getOperand(5).setImm((MB-1) & 31);
203  return MI;
204}
205
206void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
207                              MachineBasicBlock::iterator MI) const {
208  DebugLoc DL;
209  BuildMI(MBB, MI, DL, get(PPC::NOP));
210}
211
212
213// Branch analysis.
214bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
215                                 MachineBasicBlock *&FBB,
216                                 SmallVectorImpl<MachineOperand> &Cond,
217                                 bool AllowModify) const {
218  // If the block has no terminators, it just falls into the block after it.
219  MachineBasicBlock::iterator I = MBB.end();
220  if (I == MBB.begin())
221    return false;
222  --I;
223  while (I->isDebugValue()) {
224    if (I == MBB.begin())
225      return false;
226    --I;
227  }
228  if (!isUnpredicatedTerminator(I))
229    return false;
230
231  // Get the last instruction in the block.
232  MachineInstr *LastInst = I;
233
234  // If there is only one terminator instruction, process it.
235  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
236    if (LastInst->getOpcode() == PPC::B) {
237      if (!LastInst->getOperand(0).isMBB())
238        return true;
239      TBB = LastInst->getOperand(0).getMBB();
240      return false;
241    } else if (LastInst->getOpcode() == PPC::BCC) {
242      if (!LastInst->getOperand(2).isMBB())
243        return true;
244      // Block ends with fall-through condbranch.
245      TBB = LastInst->getOperand(2).getMBB();
246      Cond.push_back(LastInst->getOperand(0));
247      Cond.push_back(LastInst->getOperand(1));
248      return false;
249    }
250    // Otherwise, don't know what this is.
251    return true;
252  }
253
254  // Get the instruction before it if it's a terminator.
255  MachineInstr *SecondLastInst = I;
256
257  // If there are three terminators, we don't know what sort of block this is.
258  if (SecondLastInst && I != MBB.begin() &&
259      isUnpredicatedTerminator(--I))
260    return true;
261
262  // If the block ends with PPC::B and PPC:BCC, handle it.
263  if (SecondLastInst->getOpcode() == PPC::BCC &&
264      LastInst->getOpcode() == PPC::B) {
265    if (!SecondLastInst->getOperand(2).isMBB() ||
266        !LastInst->getOperand(0).isMBB())
267      return true;
268    TBB =  SecondLastInst->getOperand(2).getMBB();
269    Cond.push_back(SecondLastInst->getOperand(0));
270    Cond.push_back(SecondLastInst->getOperand(1));
271    FBB = LastInst->getOperand(0).getMBB();
272    return false;
273  }
274
275  // If the block ends with two PPC:Bs, handle it.  The second one is not
276  // executed, so remove it.
277  if (SecondLastInst->getOpcode() == PPC::B &&
278      LastInst->getOpcode() == PPC::B) {
279    if (!SecondLastInst->getOperand(0).isMBB())
280      return true;
281    TBB = SecondLastInst->getOperand(0).getMBB();
282    I = LastInst;
283    if (AllowModify)
284      I->eraseFromParent();
285    return false;
286  }
287
288  // Otherwise, can't handle this.
289  return true;
290}
291
292unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
293  MachineBasicBlock::iterator I = MBB.end();
294  if (I == MBB.begin()) return 0;
295  --I;
296  while (I->isDebugValue()) {
297    if (I == MBB.begin())
298      return 0;
299    --I;
300  }
301  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
302    return 0;
303
304  // Remove the branch.
305  I->eraseFromParent();
306
307  I = MBB.end();
308
309  if (I == MBB.begin()) return 1;
310  --I;
311  if (I->getOpcode() != PPC::BCC)
312    return 1;
313
314  // Remove the branch.
315  I->eraseFromParent();
316  return 2;
317}
318
319unsigned
320PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
321                           MachineBasicBlock *FBB,
322                           const SmallVectorImpl<MachineOperand> &Cond,
323                           DebugLoc DL) const {
324  // Shouldn't be a fall through.
325  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
326  assert((Cond.size() == 2 || Cond.size() == 0) &&
327         "PPC branch conditions have two components!");
328
329  // One-way branch.
330  if (FBB == 0) {
331    if (Cond.empty())   // Unconditional branch
332      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
333    else                // Conditional branch
334      BuildMI(&MBB, DL, get(PPC::BCC))
335        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
336    return 1;
337  }
338
339  // Two-way Conditional Branch.
340  BuildMI(&MBB, DL, get(PPC::BCC))
341    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
342  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
343  return 2;
344}
345
346void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
347                               MachineBasicBlock::iterator I, DebugLoc DL,
348                               unsigned DestReg, unsigned SrcReg,
349                               bool KillSrc) const {
350  unsigned Opc;
351  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
352    Opc = PPC::OR;
353  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
354    Opc = PPC::OR8;
355  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
356    Opc = PPC::FMR;
357  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
358    Opc = PPC::MCRF;
359  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
360    Opc = PPC::VOR;
361  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
362    Opc = PPC::CROR;
363  else
364    llvm_unreachable("Impossible reg-to-reg copy");
365
366  const TargetInstrDesc &TID = get(Opc);
367  if (TID.getNumOperands() == 3)
368    BuildMI(MBB, I, DL, TID, DestReg)
369      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
370  else
371    BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
372}
373
374bool
375PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
376                                  unsigned SrcReg, bool isKill,
377                                  int FrameIdx,
378                                  const TargetRegisterClass *RC,
379                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
380  DebugLoc DL;
381  if (RC == PPC::GPRCRegisterClass) {
382    if (SrcReg != PPC::LR) {
383      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
384                                         .addReg(SrcReg,
385                                                 getKillRegState(isKill)),
386                                         FrameIdx));
387    } else {
388      // FIXME: this spills LR immediately to memory in one step.  To do this,
389      // we use R11, which we know cannot be used in the prolog/epilog.  This is
390      // a hack.
391      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
392      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
393                                         .addReg(PPC::R11,
394                                                 getKillRegState(isKill)),
395                                         FrameIdx));
396    }
397  } else if (RC == PPC::G8RCRegisterClass) {
398    if (SrcReg != PPC::LR8) {
399      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
400                                         .addReg(SrcReg,
401                                                 getKillRegState(isKill)),
402                                         FrameIdx));
403    } else {
404      // FIXME: this spills LR immediately to memory in one step.  To do this,
405      // we use R11, which we know cannot be used in the prolog/epilog.  This is
406      // a hack.
407      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
408      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
409                                         .addReg(PPC::X11,
410                                                 getKillRegState(isKill)),
411                                         FrameIdx));
412    }
413  } else if (RC == PPC::F8RCRegisterClass) {
414    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
415                                       .addReg(SrcReg,
416                                               getKillRegState(isKill)),
417                                       FrameIdx));
418  } else if (RC == PPC::F4RCRegisterClass) {
419    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
420                                       .addReg(SrcReg,
421                                               getKillRegState(isKill)),
422                                       FrameIdx));
423  } else if (RC == PPC::CRRCRegisterClass) {
424    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
425        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
426      // FIXME (64-bit): Enable
427      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
428                                         .addReg(SrcReg,
429                                                 getKillRegState(isKill)),
430                                         FrameIdx));
431      return true;
432    } else {
433      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
434      // it's possible for the stack frame to be so big the save location is
435      // out of range of immediate offsets, necessitating another register.
436      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
437      // at the moment.
438
439      // We need to store the CR in the low 4-bits of the saved value.  First,
440      // issue a MFCR to save all of the CRBits.
441      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
442                                                           PPC::R2 : PPC::R0;
443      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
444                               .addReg(SrcReg, getKillRegState(isKill)));
445
446      // If the saved register wasn't CR0, shift the bits left so that they are
447      // in CR0's slot.
448      if (SrcReg != PPC::CR0) {
449        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
450        // rlwinm scratch, scratch, ShiftBits, 0, 31.
451        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
452                       .addReg(ScratchReg).addImm(ShiftBits)
453                       .addImm(0).addImm(31));
454      }
455
456      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
457                                         .addReg(ScratchReg,
458                                                 getKillRegState(isKill)),
459                                         FrameIdx));
460    }
461  } else if (RC == PPC::CRBITRCRegisterClass) {
462    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
463    // backend currently only uses CR1EQ as an individual bit, this should
464    // not cause any bug. If we need other uses of CR bits, the following
465    // code may be invalid.
466    unsigned Reg = 0;
467    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
468        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
469      Reg = PPC::CR0;
470    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
471             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
472      Reg = PPC::CR1;
473    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
474             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
475      Reg = PPC::CR2;
476    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
477             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
478      Reg = PPC::CR3;
479    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
480             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
481      Reg = PPC::CR4;
482    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
483             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
484      Reg = PPC::CR5;
485    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
486             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
487      Reg = PPC::CR6;
488    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
489             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
490      Reg = PPC::CR7;
491
492    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
493                               PPC::CRRCRegisterClass, NewMIs);
494
495  } else if (RC == PPC::VRRCRegisterClass) {
496    // We don't have indexed addressing for vector loads.  Emit:
497    // R0 = ADDI FI#
498    // STVX VAL, 0, R0
499    //
500    // FIXME: We use R0 here, because it isn't available for RA.
501    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
502                                       FrameIdx, 0, 0));
503    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
504                     .addReg(SrcReg, getKillRegState(isKill))
505                     .addReg(PPC::R0)
506                     .addReg(PPC::R0));
507  } else {
508    llvm_unreachable("Unknown regclass!");
509  }
510
511  return false;
512}
513
514void
515PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
516                                  MachineBasicBlock::iterator MI,
517                                  unsigned SrcReg, bool isKill, int FrameIdx,
518                                  const TargetRegisterClass *RC,
519                                  const TargetRegisterInfo *TRI) const {
520  MachineFunction &MF = *MBB.getParent();
521  SmallVector<MachineInstr*, 4> NewMIs;
522
523  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
524    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
525    FuncInfo->setSpillsCR();
526  }
527
528  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
529    MBB.insert(MI, NewMIs[i]);
530
531  const MachineFrameInfo &MFI = *MF.getFrameInfo();
532  MachineMemOperand *MMO =
533    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
534                            MachineMemOperand::MOStore, /*Offset=*/0,
535                            MFI.getObjectSize(FrameIdx),
536                            MFI.getObjectAlignment(FrameIdx));
537  NewMIs.back()->addMemOperand(MF, MMO);
538}
539
540void
541PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
542                                   unsigned DestReg, int FrameIdx,
543                                   const TargetRegisterClass *RC,
544                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
545  if (RC == PPC::GPRCRegisterClass) {
546    if (DestReg != PPC::LR) {
547      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
548                                                 DestReg), FrameIdx));
549    } else {
550      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
551                                                 PPC::R11), FrameIdx));
552      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
553    }
554  } else if (RC == PPC::G8RCRegisterClass) {
555    if (DestReg != PPC::LR8) {
556      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
557                                         FrameIdx));
558    } else {
559      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
560                                                 PPC::R11), FrameIdx));
561      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
562    }
563  } else if (RC == PPC::F8RCRegisterClass) {
564    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
565                                       FrameIdx));
566  } else if (RC == PPC::F4RCRegisterClass) {
567    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
568                                       FrameIdx));
569  } else if (RC == PPC::CRRCRegisterClass) {
570    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
571    // it's possible for the stack frame to be so big the save location is
572    // out of range of immediate offsets, necessitating another register.
573    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
574    // at the moment.
575    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
576                                                          PPC::R2 : PPC::R0;
577    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
578                                       ScratchReg), FrameIdx));
579
580    // If the reloaded register isn't CR0, shift the bits right so that they are
581    // in the right CR's slot.
582    if (DestReg != PPC::CR0) {
583      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
584      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
585      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
586                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
587                    .addImm(31));
588    }
589
590    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
591                     .addReg(ScratchReg));
592  } else if (RC == PPC::CRBITRCRegisterClass) {
593
594    unsigned Reg = 0;
595    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
596        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
597      Reg = PPC::CR0;
598    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
599             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
600      Reg = PPC::CR1;
601    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
602             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
603      Reg = PPC::CR2;
604    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
605             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
606      Reg = PPC::CR3;
607    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
608             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
609      Reg = PPC::CR4;
610    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
611             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
612      Reg = PPC::CR5;
613    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
614             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
615      Reg = PPC::CR6;
616    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
617             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
618      Reg = PPC::CR7;
619
620    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
621                                PPC::CRRCRegisterClass, NewMIs);
622
623  } else if (RC == PPC::VRRCRegisterClass) {
624    // We don't have indexed addressing for vector loads.  Emit:
625    // R0 = ADDI FI#
626    // Dest = LVX 0, R0
627    //
628    // FIXME: We use R0 here, because it isn't available for RA.
629    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
630                                       FrameIdx, 0, 0));
631    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
632                     .addReg(PPC::R0));
633  } else {
634    llvm_unreachable("Unknown regclass!");
635  }
636}
637
638void
639PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
640                                   MachineBasicBlock::iterator MI,
641                                   unsigned DestReg, int FrameIdx,
642                                   const TargetRegisterClass *RC,
643                                   const TargetRegisterInfo *TRI) const {
644  MachineFunction &MF = *MBB.getParent();
645  SmallVector<MachineInstr*, 4> NewMIs;
646  DebugLoc DL;
647  if (MI != MBB.end()) DL = MI->getDebugLoc();
648  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
649  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
650    MBB.insert(MI, NewMIs[i]);
651
652  const MachineFrameInfo &MFI = *MF.getFrameInfo();
653  MachineMemOperand *MMO =
654    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
655                            MachineMemOperand::MOLoad, /*Offset=*/0,
656                            MFI.getObjectSize(FrameIdx),
657                            MFI.getObjectAlignment(FrameIdx));
658  NewMIs.back()->addMemOperand(MF, MMO);
659}
660
661MachineInstr*
662PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
663                                       int FrameIx, uint64_t Offset,
664                                       const MDNode *MDPtr,
665                                       DebugLoc DL) const {
666  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
667  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
668  return &*MIB;
669}
670
671bool PPCInstrInfo::
672ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
673  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
674  // Leave the CR# the same, but invert the condition.
675  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
676  return false;
677}
678
679/// GetInstSize - Return the number of bytes of code the specified
680/// instruction may be.  This returns the maximum number of bytes.
681///
682unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
683  switch (MI->getOpcode()) {
684  case PPC::INLINEASM: {       // Inline Asm: Variable size.
685    const MachineFunction *MF = MI->getParent()->getParent();
686    const char *AsmStr = MI->getOperand(0).getSymbolName();
687    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
688  }
689  case PPC::DBG_LABEL:
690  case PPC::EH_LABEL:
691  case PPC::GC_LABEL:
692  case PPC::DBG_VALUE:
693    return 0;
694  default:
695    return 4; // PowerPC instructions are all 4 bytes
696  }
697}
698