PPCInstrInfo.cpp revision c50e2bcdf7bff1f9681ab80e52691f274950fab5
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCInstrInfo.h" 15#include "PPCGenInstrInfo.inc" 16#include "PPCTargetMachine.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include <iostream> 19using namespace llvm; 20 21PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 22 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm), 23 RI(*TM.getSubtargetImpl()) {} 24 25/// getPointerRegClass - Return the register class to use to hold pointers. 26/// This is used for addressing modes. 27const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { 28 if (TM.getSubtargetImpl()->isPPC64()) 29 return &PPC::G8RCRegClass; 30 else 31 return &PPC::GPRCRegClass; 32} 33 34 35bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 36 unsigned& sourceReg, 37 unsigned& destReg) const { 38 MachineOpCode oc = MI.getOpcode(); 39 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 40 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 41 assert(MI.getNumOperands() == 3 && 42 MI.getOperand(0).isRegister() && 43 MI.getOperand(1).isRegister() && 44 MI.getOperand(2).isRegister() && 45 "invalid PPC OR instruction!"); 46 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 47 sourceReg = MI.getOperand(1).getReg(); 48 destReg = MI.getOperand(0).getReg(); 49 return true; 50 } 51 } else if (oc == PPC::ADDI) { // addi r1, r2, 0 52 assert(MI.getNumOperands() == 3 && 53 MI.getOperand(0).isRegister() && 54 MI.getOperand(2).isImmediate() && 55 "invalid PPC ADDI instruction!"); 56 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { 57 sourceReg = MI.getOperand(1).getReg(); 58 destReg = MI.getOperand(0).getReg(); 59 return true; 60 } 61 } else if (oc == PPC::ORI) { // ori r1, r2, 0 62 assert(MI.getNumOperands() == 3 && 63 MI.getOperand(0).isRegister() && 64 MI.getOperand(1).isRegister() && 65 MI.getOperand(2).isImmediate() && 66 "invalid PPC ORI instruction!"); 67 if (MI.getOperand(2).getImmedValue()==0) { 68 sourceReg = MI.getOperand(1).getReg(); 69 destReg = MI.getOperand(0).getReg(); 70 return true; 71 } 72 } else if (oc == PPC::FMRS || oc == PPC::FMRD || 73 oc == PPC::FMRSD) { // fmr r1, r2 74 assert(MI.getNumOperands() == 2 && 75 MI.getOperand(0).isRegister() && 76 MI.getOperand(1).isRegister() && 77 "invalid PPC FMR instruction"); 78 sourceReg = MI.getOperand(1).getReg(); 79 destReg = MI.getOperand(0).getReg(); 80 return true; 81 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 82 assert(MI.getNumOperands() == 2 && 83 MI.getOperand(0).isRegister() && 84 MI.getOperand(1).isRegister() && 85 "invalid PPC MCRF instruction"); 86 sourceReg = MI.getOperand(1).getReg(); 87 destReg = MI.getOperand(0).getReg(); 88 return true; 89 } 90 return false; 91} 92 93unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 94 int &FrameIndex) const { 95 switch (MI->getOpcode()) { 96 default: break; 97 case PPC::LD: 98 case PPC::LWZ: 99 case PPC::LFS: 100 case PPC::LFD: 101 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 102 MI->getOperand(2).isFrameIndex()) { 103 FrameIndex = MI->getOperand(2).getFrameIndex(); 104 return MI->getOperand(0).getReg(); 105 } 106 break; 107 } 108 return 0; 109} 110 111unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 112 int &FrameIndex) const { 113 switch (MI->getOpcode()) { 114 default: break; 115 case PPC::STD: 116 case PPC::STW: 117 case PPC::STFS: 118 case PPC::STFD: 119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 120 MI->getOperand(2).isFrameIndex()) { 121 FrameIndex = MI->getOperand(2).getFrameIndex(); 122 return MI->getOperand(0).getReg(); 123 } 124 break; 125 } 126 return 0; 127} 128 129// commuteInstruction - We can commute rlwimi instructions, but only if the 130// rotate amt is zero. We also have to munge the immediates a bit. 131MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 132 // Normal instructions can be commuted the obvious way. 133 if (MI->getOpcode() != PPC::RLWIMI) 134 return TargetInstrInfo::commuteInstruction(MI); 135 136 // Cannot commute if it has a non-zero rotate count. 137 if (MI->getOperand(3).getImmedValue() != 0) 138 return 0; 139 140 // If we have a zero rotate count, we have: 141 // M = mask(MB,ME) 142 // Op0 = (Op1 & ~M) | (Op2 & M) 143 // Change this to: 144 // M = mask((ME+1)&31, (MB-1)&31) 145 // Op0 = (Op2 & ~M) | (Op1 & M) 146 147 // Swap op1/op2 148 unsigned Reg1 = MI->getOperand(1).getReg(); 149 unsigned Reg2 = MI->getOperand(2).getReg(); 150 MI->getOperand(2).setReg(Reg1); 151 MI->getOperand(1).setReg(Reg2); 152 153 // Swap the mask around. 154 unsigned MB = MI->getOperand(4).getImmedValue(); 155 unsigned ME = MI->getOperand(5).getImmedValue(); 156 MI->getOperand(4).setImmedValue((ME+1) & 31); 157 MI->getOperand(5).setImmedValue((MB-1) & 31); 158 return MI; 159} 160 161void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 162 MachineBasicBlock::iterator MI) const { 163 BuildMI(MBB, MI, PPC::NOP, 0); 164} 165 166 167// Branch analysis. 168bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 169 MachineBasicBlock *&FBB, 170 std::vector<MachineOperand> &Cond) const { 171 // If the block has no terminators, it just falls into the block after it. 172 MachineBasicBlock::iterator I = MBB.end(); 173 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) 174 return false; 175 176 // Get the last instruction in the block. 177 MachineInstr *LastInst = I; 178 179 // If there is only one terminator instruction, process it. 180 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { 181 if (LastInst->getOpcode() == PPC::B) { 182 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 183 return false; 184 } else if (LastInst->getOpcode() == PPC::COND_BRANCH) { 185 // Block ends with fall-through condbranch. 186 TBB = LastInst->getOperand(2).getMachineBasicBlock(); 187 Cond.push_back(LastInst->getOperand(0)); 188 Cond.push_back(LastInst->getOperand(1)); 189 return true; 190 } 191 // Otherwise, don't know what this is. 192 return true; 193 } 194 195 // Get the instruction before it if it's a terminator. 196 MachineInstr *SecondLastInst = I; 197 198 // If there are three terminators, we don't know what sort of block this is. 199 if (SecondLastInst && I != MBB.begin() && 200 isTerminatorInstr((--I)->getOpcode())) 201 return true; 202 203 // If the block ends with PPC::B and PPC:COND_BRANCH, handle it. 204 if (SecondLastInst->getOpcode() == PPC::COND_BRANCH && 205 LastInst->getOpcode() == PPC::B) { 206 TBB = SecondLastInst->getOperand(2).getMachineBasicBlock(); 207 Cond.push_back(SecondLastInst->getOperand(0)); 208 Cond.push_back(SecondLastInst->getOperand(1)); 209 FBB = LastInst->getOperand(0).getMachineBasicBlock(); 210 return false; 211 } 212 213 // Otherwise, can't handle this. 214 return true; 215} 216 217void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 218 MachineBasicBlock::iterator I = MBB.end(); 219 if (I == MBB.begin()) return; 220 --I; 221 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::COND_BRANCH) 222 return; 223 224 // Remove the branch. 225 I->eraseFromParent(); 226 227 I = MBB.end(); 228 229 if (I == MBB.begin()) return; 230 --I; 231 if (I->getOpcode() != PPC::COND_BRANCH) 232 return; 233 234 // Remove the branch. 235 I->eraseFromParent(); 236} 237 238void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 239 MachineBasicBlock *FBB, 240 const std::vector<MachineOperand> &Cond) const { 241 // Fall through? 242 if (TBB == 0 && FBB == 0) return; 243 244 assert(Cond.size() == 2 && "PPC branch conditions have two components!"); 245 246 // Conditional branch 247 BuildMI(&MBB, PPC::COND_BRANCH, 3) 248 .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB); 249 250 if (FBB) // Two-way branch. 251 BuildMI(&MBB, PPC::B, 1).addMBB(FBB); 252} 253 254bool PPCInstrInfo:: 255ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 256 return true; 257} 258