PPCInstrInfo.cpp revision 0839033cbca20a1d1348bdf1c9f63fb263b248a6 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCTargetMachine.h"
19#include "PPCHazardRecognizers.h"
20#include "MCTargetDesc/PPCPredicates.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/ADT/STLExtras.h"
32
33#define GET_INSTRINFO_CTOR
34#include "PPCGenInstrInfo.inc"
35
36namespace llvm {
37extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
38extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
39}
40
41using namespace llvm;
42
43PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
44  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
45    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46
47/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
48/// this target when scheduling the DAG.
49ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
50  const TargetMachine *TM,
51  const ScheduleDAG *DAG) const {
52  // Should use subtarget info to pick the right hazard recognizer.  For
53  // now, always return a PPC970 recognizer.
54  const TargetInstrInfo *TII = TM->getInstrInfo();
55  (void)TII;
56  assert(TII && "No InstrInfo?");
57
58  unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
59  if (Directive == PPC::DIR_440) {
60    // Disable the hazard recognizer for now, as it doesn't support
61    // bottom-up scheduling.
62    //const InstrItineraryData *II = TM->getInstrItineraryData();
63    //return new PPCHazardRecognizer440(II, DAG);
64    return new ScheduleHazardRecognizer();
65  }
66  else {
67    // Disable the hazard recognizer for now, as it doesn't support
68    // bottom-up scheduling.
69    //return new PPCHazardRecognizer970(*TII);
70    return new ScheduleHazardRecognizer();
71  }
72}
73
74unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
75                                           int &FrameIndex) const {
76  switch (MI->getOpcode()) {
77  default: break;
78  case PPC::LD:
79  case PPC::LWZ:
80  case PPC::LFS:
81  case PPC::LFD:
82    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
83        MI->getOperand(2).isFI()) {
84      FrameIndex = MI->getOperand(2).getIndex();
85      return MI->getOperand(0).getReg();
86    }
87    break;
88  }
89  return 0;
90}
91
92unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
93                                          int &FrameIndex) const {
94  switch (MI->getOpcode()) {
95  default: break;
96  case PPC::STD:
97  case PPC::STW:
98  case PPC::STFS:
99  case PPC::STFD:
100    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
101        MI->getOperand(2).isFI()) {
102      FrameIndex = MI->getOperand(2).getIndex();
103      return MI->getOperand(0).getReg();
104    }
105    break;
106  }
107  return 0;
108}
109
110// commuteInstruction - We can commute rlwimi instructions, but only if the
111// rotate amt is zero.  We also have to munge the immediates a bit.
112MachineInstr *
113PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
114  MachineFunction &MF = *MI->getParent()->getParent();
115
116  // Normal instructions can be commuted the obvious way.
117  if (MI->getOpcode() != PPC::RLWIMI)
118    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
119
120  // Cannot commute if it has a non-zero rotate count.
121  if (MI->getOperand(3).getImm() != 0)
122    return 0;
123
124  // If we have a zero rotate count, we have:
125  //   M = mask(MB,ME)
126  //   Op0 = (Op1 & ~M) | (Op2 & M)
127  // Change this to:
128  //   M = mask((ME+1)&31, (MB-1)&31)
129  //   Op0 = (Op2 & ~M) | (Op1 & M)
130
131  // Swap op1/op2
132  unsigned Reg0 = MI->getOperand(0).getReg();
133  unsigned Reg1 = MI->getOperand(1).getReg();
134  unsigned Reg2 = MI->getOperand(2).getReg();
135  bool Reg1IsKill = MI->getOperand(1).isKill();
136  bool Reg2IsKill = MI->getOperand(2).isKill();
137  bool ChangeReg0 = false;
138  // If machine instrs are no longer in two-address forms, update
139  // destination register as well.
140  if (Reg0 == Reg1) {
141    // Must be two address instruction!
142    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
143           "Expecting a two-address instruction!");
144    Reg2IsKill = false;
145    ChangeReg0 = true;
146  }
147
148  // Masks.
149  unsigned MB = MI->getOperand(4).getImm();
150  unsigned ME = MI->getOperand(5).getImm();
151
152  if (NewMI) {
153    // Create a new instruction.
154    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
155    bool Reg0IsDead = MI->getOperand(0).isDead();
156    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
157      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
158      .addReg(Reg2, getKillRegState(Reg2IsKill))
159      .addReg(Reg1, getKillRegState(Reg1IsKill))
160      .addImm((ME+1) & 31)
161      .addImm((MB-1) & 31);
162  }
163
164  if (ChangeReg0)
165    MI->getOperand(0).setReg(Reg2);
166  MI->getOperand(2).setReg(Reg1);
167  MI->getOperand(1).setReg(Reg2);
168  MI->getOperand(2).setIsKill(Reg1IsKill);
169  MI->getOperand(1).setIsKill(Reg2IsKill);
170
171  // Swap the mask around.
172  MI->getOperand(4).setImm((ME+1) & 31);
173  MI->getOperand(5).setImm((MB-1) & 31);
174  return MI;
175}
176
177void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
178                              MachineBasicBlock::iterator MI) const {
179  DebugLoc DL;
180  BuildMI(MBB, MI, DL, get(PPC::NOP));
181}
182
183
184// Branch analysis.
185bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
186                                 MachineBasicBlock *&FBB,
187                                 SmallVectorImpl<MachineOperand> &Cond,
188                                 bool AllowModify) const {
189  // If the block has no terminators, it just falls into the block after it.
190  MachineBasicBlock::iterator I = MBB.end();
191  if (I == MBB.begin())
192    return false;
193  --I;
194  while (I->isDebugValue()) {
195    if (I == MBB.begin())
196      return false;
197    --I;
198  }
199  if (!isUnpredicatedTerminator(I))
200    return false;
201
202  // Get the last instruction in the block.
203  MachineInstr *LastInst = I;
204
205  // If there is only one terminator instruction, process it.
206  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
207    if (LastInst->getOpcode() == PPC::B) {
208      if (!LastInst->getOperand(0).isMBB())
209        return true;
210      TBB = LastInst->getOperand(0).getMBB();
211      return false;
212    } else if (LastInst->getOpcode() == PPC::BCC) {
213      if (!LastInst->getOperand(2).isMBB())
214        return true;
215      // Block ends with fall-through condbranch.
216      TBB = LastInst->getOperand(2).getMBB();
217      Cond.push_back(LastInst->getOperand(0));
218      Cond.push_back(LastInst->getOperand(1));
219      return false;
220    }
221    // Otherwise, don't know what this is.
222    return true;
223  }
224
225  // Get the instruction before it if it's a terminator.
226  MachineInstr *SecondLastInst = I;
227
228  // If there are three terminators, we don't know what sort of block this is.
229  if (SecondLastInst && I != MBB.begin() &&
230      isUnpredicatedTerminator(--I))
231    return true;
232
233  // If the block ends with PPC::B and PPC:BCC, handle it.
234  if (SecondLastInst->getOpcode() == PPC::BCC &&
235      LastInst->getOpcode() == PPC::B) {
236    if (!SecondLastInst->getOperand(2).isMBB() ||
237        !LastInst->getOperand(0).isMBB())
238      return true;
239    TBB =  SecondLastInst->getOperand(2).getMBB();
240    Cond.push_back(SecondLastInst->getOperand(0));
241    Cond.push_back(SecondLastInst->getOperand(1));
242    FBB = LastInst->getOperand(0).getMBB();
243    return false;
244  }
245
246  // If the block ends with two PPC:Bs, handle it.  The second one is not
247  // executed, so remove it.
248  if (SecondLastInst->getOpcode() == PPC::B &&
249      LastInst->getOpcode() == PPC::B) {
250    if (!SecondLastInst->getOperand(0).isMBB())
251      return true;
252    TBB = SecondLastInst->getOperand(0).getMBB();
253    I = LastInst;
254    if (AllowModify)
255      I->eraseFromParent();
256    return false;
257  }
258
259  // Otherwise, can't handle this.
260  return true;
261}
262
263unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
264  MachineBasicBlock::iterator I = MBB.end();
265  if (I == MBB.begin()) return 0;
266  --I;
267  while (I->isDebugValue()) {
268    if (I == MBB.begin())
269      return 0;
270    --I;
271  }
272  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
273    return 0;
274
275  // Remove the branch.
276  I->eraseFromParent();
277
278  I = MBB.end();
279
280  if (I == MBB.begin()) return 1;
281  --I;
282  if (I->getOpcode() != PPC::BCC)
283    return 1;
284
285  // Remove the branch.
286  I->eraseFromParent();
287  return 2;
288}
289
290unsigned
291PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
292                           MachineBasicBlock *FBB,
293                           const SmallVectorImpl<MachineOperand> &Cond,
294                           DebugLoc DL) const {
295  // Shouldn't be a fall through.
296  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
297  assert((Cond.size() == 2 || Cond.size() == 0) &&
298         "PPC branch conditions have two components!");
299
300  // One-way branch.
301  if (FBB == 0) {
302    if (Cond.empty())   // Unconditional branch
303      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
304    else                // Conditional branch
305      BuildMI(&MBB, DL, get(PPC::BCC))
306        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
307    return 1;
308  }
309
310  // Two-way Conditional Branch.
311  BuildMI(&MBB, DL, get(PPC::BCC))
312    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
313  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
314  return 2;
315}
316
317void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
318                               MachineBasicBlock::iterator I, DebugLoc DL,
319                               unsigned DestReg, unsigned SrcReg,
320                               bool KillSrc) const {
321  unsigned Opc;
322  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
323    Opc = PPC::OR;
324  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
325    Opc = PPC::OR8;
326  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
327    Opc = PPC::FMR;
328  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
329    Opc = PPC::MCRF;
330  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
331    Opc = PPC::VOR;
332  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
333    Opc = PPC::CROR;
334  else
335    llvm_unreachable("Impossible reg-to-reg copy");
336
337  const MCInstrDesc &MCID = get(Opc);
338  if (MCID.getNumOperands() == 3)
339    BuildMI(MBB, I, DL, MCID, DestReg)
340      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
341  else
342    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
343}
344
345bool
346PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
347                                  unsigned SrcReg, bool isKill,
348                                  int FrameIdx,
349                                  const TargetRegisterClass *RC,
350                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
351  DebugLoc DL;
352  if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
353    if (SrcReg != PPC::LR) {
354      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
355                                         .addReg(SrcReg,
356                                                 getKillRegState(isKill)),
357                                         FrameIdx));
358    } else {
359      // FIXME: this spills LR immediately to memory in one step.  To do this,
360      // we use R11, which we know cannot be used in the prolog/epilog.  This is
361      // a hack.
362      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
363      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
364                                         .addReg(PPC::R11,
365                                                 getKillRegState(isKill)),
366                                         FrameIdx));
367    }
368  } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
369    if (SrcReg != PPC::LR8) {
370      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
371                                         .addReg(SrcReg,
372                                                 getKillRegState(isKill)),
373                                         FrameIdx));
374    } else {
375      // FIXME: this spills LR immediately to memory in one step.  To do this,
376      // we use R11, which we know cannot be used in the prolog/epilog.  This is
377      // a hack.
378      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
379      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
380                                         .addReg(PPC::X11,
381                                                 getKillRegState(isKill)),
382                                         FrameIdx));
383    }
384  } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
385    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
386                                       .addReg(SrcReg,
387                                               getKillRegState(isKill)),
388                                       FrameIdx));
389  } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
390    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
391                                       .addReg(SrcReg,
392                                               getKillRegState(isKill)),
393                                       FrameIdx));
394  } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
395    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
396        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
397      // FIXME (64-bit): Enable
398      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
399                                         .addReg(SrcReg,
400                                                 getKillRegState(isKill)),
401                                         FrameIdx));
402      return true;
403    } else {
404      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
405      // it's possible for the stack frame to be so big the save location is
406      // out of range of immediate offsets, necessitating another register.
407      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
408      // at the moment.
409
410      // We need to store the CR in the low 4-bits of the saved value.  First,
411      // issue a MFCR to save all of the CRBits.
412      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
413                                                           PPC::R2 : PPC::R0;
414      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
415                               .addReg(SrcReg, getKillRegState(isKill)));
416
417      // If the saved register wasn't CR0, shift the bits left so that they are
418      // in CR0's slot.
419      if (SrcReg != PPC::CR0) {
420        unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
421        // rlwinm scratch, scratch, ShiftBits, 0, 31.
422        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
423                       .addReg(ScratchReg).addImm(ShiftBits)
424                       .addImm(0).addImm(31));
425      }
426
427      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
428                                         .addReg(ScratchReg,
429                                                 getKillRegState(isKill)),
430                                         FrameIdx));
431    }
432  } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
433    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
434    // backend currently only uses CR1EQ as an individual bit, this should
435    // not cause any bug. If we need other uses of CR bits, the following
436    // code may be invalid.
437    unsigned Reg = 0;
438    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
439        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
440      Reg = PPC::CR0;
441    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
442             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
443      Reg = PPC::CR1;
444    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
445             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
446      Reg = PPC::CR2;
447    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
448             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
449      Reg = PPC::CR3;
450    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
451             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
452      Reg = PPC::CR4;
453    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
454             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
455      Reg = PPC::CR5;
456    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
457             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
458      Reg = PPC::CR6;
459    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
460             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
461      Reg = PPC::CR7;
462
463    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
464                               PPC::CRRCRegisterClass, NewMIs);
465
466  } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
467    // We don't have indexed addressing for vector loads.  Emit:
468    // R0 = ADDI FI#
469    // STVX VAL, 0, R0
470    //
471    // FIXME: We use R0 here, because it isn't available for RA.
472    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
473                                       FrameIdx, 0, 0));
474    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
475                     .addReg(SrcReg, getKillRegState(isKill))
476                     .addReg(PPC::R0)
477                     .addReg(PPC::R0));
478  } else {
479    llvm_unreachable("Unknown regclass!");
480  }
481
482  return false;
483}
484
485void
486PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
487                                  MachineBasicBlock::iterator MI,
488                                  unsigned SrcReg, bool isKill, int FrameIdx,
489                                  const TargetRegisterClass *RC,
490                                  const TargetRegisterInfo *TRI) const {
491  MachineFunction &MF = *MBB.getParent();
492  SmallVector<MachineInstr*, 4> NewMIs;
493
494  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
495    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
496    FuncInfo->setSpillsCR();
497  }
498
499  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
500    MBB.insert(MI, NewMIs[i]);
501
502  const MachineFrameInfo &MFI = *MF.getFrameInfo();
503  MachineMemOperand *MMO =
504    MF.getMachineMemOperand(
505                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
506                            MachineMemOperand::MOStore,
507                            MFI.getObjectSize(FrameIdx),
508                            MFI.getObjectAlignment(FrameIdx));
509  NewMIs.back()->addMemOperand(MF, MMO);
510}
511
512void
513PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
514                                   unsigned DestReg, int FrameIdx,
515                                   const TargetRegisterClass *RC,
516                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
517  if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
518    if (DestReg != PPC::LR) {
519      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
520                                                 DestReg), FrameIdx));
521    } else {
522      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
523                                                 PPC::R11), FrameIdx));
524      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
525    }
526  } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
527    if (DestReg != PPC::LR8) {
528      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
529                                         FrameIdx));
530    } else {
531      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
532                                                 PPC::R11), FrameIdx));
533      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
534    }
535  } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
536    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
537                                       FrameIdx));
538  } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
539    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
540                                       FrameIdx));
541  } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
542    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
543    // it's possible for the stack frame to be so big the save location is
544    // out of range of immediate offsets, necessitating another register.
545    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
546    // at the moment.
547    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
548                                                          PPC::R2 : PPC::R0;
549    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
550                                       ScratchReg), FrameIdx));
551
552    // If the reloaded register isn't CR0, shift the bits right so that they are
553    // in the right CR's slot.
554    if (DestReg != PPC::CR0) {
555      unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
556      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
557      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
558                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
559                    .addImm(31));
560    }
561
562    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
563                     .addReg(ScratchReg));
564  } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
565
566    unsigned Reg = 0;
567    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
568        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
569      Reg = PPC::CR0;
570    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
571             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
572      Reg = PPC::CR1;
573    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
574             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
575      Reg = PPC::CR2;
576    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
577             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
578      Reg = PPC::CR3;
579    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
580             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
581      Reg = PPC::CR4;
582    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
583             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
584      Reg = PPC::CR5;
585    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
586             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
587      Reg = PPC::CR6;
588    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
589             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
590      Reg = PPC::CR7;
591
592    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
593                                PPC::CRRCRegisterClass, NewMIs);
594
595  } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
596    // We don't have indexed addressing for vector loads.  Emit:
597    // R0 = ADDI FI#
598    // Dest = LVX 0, R0
599    //
600    // FIXME: We use R0 here, because it isn't available for RA.
601    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
602                                       FrameIdx, 0, 0));
603    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
604                     .addReg(PPC::R0));
605  } else {
606    llvm_unreachable("Unknown regclass!");
607  }
608}
609
610void
611PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
612                                   MachineBasicBlock::iterator MI,
613                                   unsigned DestReg, int FrameIdx,
614                                   const TargetRegisterClass *RC,
615                                   const TargetRegisterInfo *TRI) const {
616  MachineFunction &MF = *MBB.getParent();
617  SmallVector<MachineInstr*, 4> NewMIs;
618  DebugLoc DL;
619  if (MI != MBB.end()) DL = MI->getDebugLoc();
620  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
621  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
622    MBB.insert(MI, NewMIs[i]);
623
624  const MachineFrameInfo &MFI = *MF.getFrameInfo();
625  MachineMemOperand *MMO =
626    MF.getMachineMemOperand(
627                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
628                            MachineMemOperand::MOLoad,
629                            MFI.getObjectSize(FrameIdx),
630                            MFI.getObjectAlignment(FrameIdx));
631  NewMIs.back()->addMemOperand(MF, MMO);
632}
633
634MachineInstr*
635PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
636                                       int FrameIx, uint64_t Offset,
637                                       const MDNode *MDPtr,
638                                       DebugLoc DL) const {
639  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
640  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
641  return &*MIB;
642}
643
644bool PPCInstrInfo::
645ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
646  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
647  // Leave the CR# the same, but invert the condition.
648  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
649  return false;
650}
651
652/// GetInstSize - Return the number of bytes of code the specified
653/// instruction may be.  This returns the maximum number of bytes.
654///
655unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
656  switch (MI->getOpcode()) {
657  case PPC::INLINEASM: {       // Inline Asm: Variable size.
658    const MachineFunction *MF = MI->getParent()->getParent();
659    const char *AsmStr = MI->getOperand(0).getSymbolName();
660    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
661  }
662  case PPC::PROLOG_LABEL:
663  case PPC::EH_LABEL:
664  case PPC::GC_LABEL:
665  case PPC::DBG_VALUE:
666    return 0;
667  default:
668    return 4; // PowerPC instructions are all 4 bytes
669  }
670}
671